digital integrated circuits a design...
TRANSCRIPT
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© Digital Integrated Circuits2nd Combinational Circuits
Designing CombinationalDesigning CombinationalLogic CircuitsLogic Circuits
Digital Integrated CircuitsDigital Integrated CircuitsA Design PerspectiveA Design PerspectiveJan M. Rabaey et al.
Adapted from Chapter 6 of
Copyright 2003 Prentice Hall/Pearson
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© Digital Integrated Circuits2nd Combinational Circuits
Combinational vs. Sequential LogicCombinational vs. Sequential Logic
Combinational Sequential
Output = f(In) Output = f(In, Previous In)
CombinationalLogicCircuit
OutInCombinational
LogicCircuit
OutIn
State
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Static CMOS CircuitStatic CMOS Circuit
At every point in time (except during the switching transients) each gate output is connected to eitherVDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods).
This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.
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Static Complementary CMOSStatic Complementary CMOSVDD
F(In1,In2,…InN)
In1In2
InN
In1In2InN
PUN
PDN
PMOS only
NMOS only
PUN and PDN are dual logic networks
……
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NMOS Transistors NMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
X Y
A B
Y = X if A and B
X Y
A
B Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1
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PMOS Transistors PMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection
X Y
A B
Y = X if A AND B = A + B
X Y
A
B Y = X if A OR B = AB
PMOS Transistors pass a “strong” 1 but a “weak” 0
PMOS switch closes when switch control input is low
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Threshold DropsThreshold DropsVDD
VDD → 0PDN
0 → VDD
CL
CL
PUN
VDD
0 → VDD - VTn
CL
VDD
VDD
VDD → |VTp|
CL
S
D S
D
VGS
S
SD
D
VGS
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Complementary CMOS Logic StyleComplementary CMOS Logic Style
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© Digital Integrated Circuits2nd Combinational Circuits
Example Gate: NANDExample Gate: NAND
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© Digital Integrated Circuits2nd Combinational Circuits
Example Gate: NORExample Gate: NOR
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© Digital Integrated Circuits2nd Combinational Circuits
Complex CMOS GateComplex CMOS Gate
OUT = D + A • (B + C)
DA
B C
D
AB
C
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© Digital Integrated Circuits2nd Combinational Circuits
Constructing a Complex GateConstructing a Complex Gate
C
(a) pull-down network
SN1 SN4
SN2
SN3D
FF
A
DB
C
D
F
A
B
C
(b) Deriving the pull-up networkhierarchically by identifyingsub-nets
D
A
A
B
C
VDD VDD
B
(c) complete gate
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Cell DesignCell Design
Standard CellsGeneral purpose logicCan be synthesizedSame height, varying width
Datapath CellsFor regular, structured designs (arithmetic)Includes some wiring in the cellFixed height and width
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Standard Cell Layout Methodology Standard Cell Layout Methodology ––1980s1980s
signals
Routingchannel
VDD
GND
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© Digital Integrated Circuits2nd Combinational Circuits
Standard Cell Layout Methodology Standard Cell Layout Methodology ––1990s1990s
M2
No Routingchannels VDD
GNDM3
VDD
GND
Mirrored Cell
Mirrored Cell
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Standard CellsStandard Cells
Cell boundary
N WellCell height 12 metal tracksMetal track is approx. 3λ + 3λPitch = repetitive distance between objects
Cell height is “12 pitch”
2λ
Rails ~10λ
InOut
VDD
GND
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Standard CellsStandard Cells
InOut
VDD
GND
In Out
VDD
GND
With silicideddiffusion
With minimaldiffusionrouting
OutIn
VDD
M2
M1
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Standard CellsStandard Cells
A
Out
VDD
GND
B
2-input NAND gate
B
VDD
A
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Stick DiagramsStick Diagrams
Contains no dimensionsRepresents relative positions of transistors
In
Out
VDD
GND
Inverter
A
Out
VDD
GNDB
NAND2
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Stick DiagramsStick Diagrams
C
A B
X = C • (A + B)
B
AC
i
j
j
VDDX
X
i
GND
AB
C
PUN
PDNABC
Logic Graph
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Two Versions of C Two Versions of C •• (A + B)(A + B)
X
CA B A B C
X
VDD
GND
VDD
GND
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Consistent Euler PathConsistent Euler Path
j
VDDX
X
i
GND
AB
C
A B C
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OAI22 Logic GraphOAI22 Logic Graph
C
A B
X = (A+B)•(C+D)
B
A
D
VDDX
X
GND
AB
C
PUN
PDN
C
D
D
ABCD
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Example: x = Example: x = ab+cdab+cd
GND
x
a
b c
d
VDDx
GND
x
a
b c
d
VDDx
(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}
a c d
x
VDD
GND
(c) stick diagram for ordering {a b c d}b
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MultiMulti--Fingered TransistorsFingered TransistorsOne finger Two fingers (folded)
Less diffusion capacitance
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Properties of Complementary CMOS Gates Properties of Complementary CMOS Gates SnapshotSnapshot
High noise margins: VOH and VOL are at VDD and GND, respectively.
No static power consumption:There never exists a direct path between VDD and VSS (GND) in steady-state mode.
Comparable rise and fall times:(under appropriate sizing conditions)
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CMOS PropertiesCMOS PropertiesFull rail-to-rail swing; high noise marginsLogic levels not dependent upon the relative device sizes; ratiolessAlways a path to Vdd or Gnd in steady state; low output impedanceExtremely high input resistance; nearly zero steady-state input currentNo direct path steady state between power and ground; no static power dissipationPropagation delay function of load capacitance and resistance of transistors
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Switch Delay ModelSwitch Delay Model
A
Req
A
Rp
A
Rp
A
Rn CL
A
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
B
Rp
A
Rp
A
Rn
B
Rn CL
Cint
NAND2 INV NOR2
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Input Pattern Effects on DelayInput Pattern Effects on Delay
Delay is dependent on the pattern of inputsLow to high transition
both inputs go low– delay is 0.69 Rp/2 CL
one input goes low– delay is 0.69 Rp CL
High to low transitionboth inputs go high
– delay is 0.69 2Rn CL
CL
B
Rn
ARp
BRp
A
Rn Cint
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Delay Dependence on Input PatternsDelay Dependence on Input Patterns
-0.5
0
0.5
1
1.5
2
2.5
3
0 100 200 300 400
A=B=1→0
A=1, B=1→0
A=1 →0, B=1
time [ps]
Vol
tage
[V]
81A= 1→0, B=1
80A=1, B=1→0
45A=B=1→0
61A= 0→1, B=1
64A=1, B=0→1
67A=B=0→1
Delay(psec)
Input DataPattern
NMOS = 0.5µm/0.25 µmPMOS = 0.75µm/0.25 µmCL = 100 fF
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Transistor SizingTransistor Sizing
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
B
Rp
A
Rp
A
Rn
B
Rn CL
Cint
2
2
2 2
11
4
4
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Transistor Sizing a Complex Transistor Sizing a Complex CMOS GateCMOS Gate
OUT = D + A • (B + C)
DA
B C
D
AB
C
1
2
2 2
4
48
8
6
36
6
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FanFan--In ConsiderationsIn Considerations
DCBA
D
C
B
A CL
C3
C2
C1
Distributed RC model(Elmore delay)
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
Propagation delay deteriorates rapidly as a function of fan-in –quadratically in the worst case.
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ttpp as a Function of Fanas a Function of Fan--InIn
tpLH
t p(p
sec)
fan-in
Gates with a fan-in greater than 4 should be avoided.
0
250
500
750
1000
1250
2 4 6 8 10 12 14 16
tpHL
quadratic
linear
tp
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ttpp as a Function of Fanas a Function of Fan--OutOut
2 4 6 8 10 12 14 16
tpNOR2
t p(p
sec)
eff. fan-out
All gates have the same drive current.
tpNAND2
tpINV
Slope is a function of “driving strength”
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ttpp as a Function of Fanas a Function of Fan--In and FanIn and Fan--OutOut
Fan-in: quadratic due to increasing resistance and capacitanceFan-out: each additional fan-out gate adds two gate capacitances to CL
tp = a1FI + a2FI2 + a3FO
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Fast Complex Gates:Fast Complex Gates:Design Technique 1Design Technique 1
Transistor sizingas long as fan-out capacitance dominates
Progressive sizing
InN CL
C3
C2
C1In1
In2
In3
M1
M2
M3
MNDistributed RC line
M1 > M2 > M3 > … > MN(the fet closest to theoutput is the smallest)
Can reduce delay by more than 20%; decreasing gains as technology shrinks
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Fast Complex Gates:Fast Complex Gates:Design Technique 2Design Technique 2
Transistor ordering
C2
C1In1
In2
In3
M1
M2
M3 CL
C2
C1In3
In2
In1
M1
M2
M3 CL
critical path critical path
charged1
0→1charged
charged1
delay determined by time to discharge CL, C1 and C2
delay determined by time to discharge CL
1
1
0→1 charged
discharged
discharged
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Fast Complex Gates:Fast Complex Gates:Design Technique 3Design Technique 3Alternative logic structures
F = ABCDEFGH
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Fast Complex Gates:Fast Complex Gates:Design Technique 4Design Technique 4
Isolating fan-in from fan-out using buffer insertion
CLCL
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Fast Complex Gates:Fast Complex Gates:Design Technique 5Design Technique 5
Reducing the voltage swing
linear reduction in delayalso reduces power consumption
But the following gate is much slower!Or requires use of “sense amplifiers” on the receiving end to restore the signal level (memory design)
tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )
= 0.69 (3/4 (CL Vswing)/ IDSATn )
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RatioedRatioed LogicLogic
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RatioedRatioed LogicLogic
VDD
VSS
PDNIn1In2In3
F
RLLoad
VDD
VSS
In1In2In3
F
VDD
VSS
PDNIn1In2In3
FVSS
PDN
Resistive DepletionLoad
PMOSLoad
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
VT < 0
Goal: to reduce the number of devices over complementary CMOS
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RatioedRatioed LogicLogicVDD
VSS
PDNIn1In2In3
F
RLLoadResistive
N transistors + Load
• VOH = VDD
• VOL = RPN
RPN + RL
• Assymetrical response
• Static power consumption
•
• tpL= 0.69 RLCL
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Active LoadsActive LoadsVDD
VSS
In1In2In3
F
VDD
VSS
PDNIn1In2In3
F
VSS
PDN
DepletionLoad
PMOSLoad
depletion load NMOS pseudo-NMOS
VT < 0
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PseudoPseudo--NMOSNMOS
VDD
A B C D
FCL
VOH = VDD (similar to complementary CMOS)
kn VDD VTn–( )VOLVOL
2
2-------------–
kp
2------ VDD VTp–( )
2=
VOL VDD VT–( ) 1 1kpkn------–– (assuming that VT VTn VTp )= = =
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!
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PseudoPseudo--NMOS VTCNMOS VTC
0.0 0.5 1.0 1.5 2.0 2.50.0
0.5
1.0
1.5
2.0
2.5
3.0
Vin [V]
Vou
t[V
]
W/Lp = 4
W/Lp = 2
W/Lp = 1
W/Lp = 0.25
W/Lp = 0.5
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Improved LoadsImproved Loads
A B C D
F
CL
M1M2 M1 >> M2Enable
VDD
Adaptive Load
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Improved Loads (2)Improved Loads (2)VDD
VSS
PDN1
Out
VDD
VSS
PDN2
Out
AABB
M1 M2
Differential Cascode Voltage Switch Logic (DCVSL)
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DCVSL ExampleDCVSL Example
B
A A
B B B
Out
Out
XOR-NXOR gate
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DCVSL Transient ResponseDCVSL Transient Response
0 0.2 0.4 0.6 0.8 1.0-0.5
0.5
1.5
2.5
Time [ns]
Vol
tage
[V] A B
A B
A,BA,B
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PassPass--TransistorTransistorLogicLogic
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PassPass--Transistor LogicTransistor Logic
Inpu
ts Switch
Network
OutOut
A
B
B
B
• N transistors• No static consumption
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Example: AND GateExample: AND Gate
B
B
A
F = AB
0
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NMOSNMOS--Only LogicOnly Logic
VDD
In
Outx
0.5µm/0.25µm0.5µm/0.25µm
1.5µm/0.25µm
0 0.5 1 1.5 20.0
1.0
2.0
3.0
Time [ns]
Vol ta
ge[V
]
xOut
In
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NMOSNMOS--only Switchonly Switch
A = 2.5 V
B
C = 2.5V
CL
A = 2.5 V
C = 2.5 V
BM2
M1
Mn
Threshold voltage loss causesstatic power consumption
VB does not pull up to 2.5V, but 2.5V -VTN
NMOS has higher threshold than PMOS (body effect)
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NMOS Only Logic: NMOS Only Logic: Level Restoring TransistorLevel Restoring Transistor
M2
M1
Mn
Mr
OutA
B
VDDVDDLevel Restorer
X
• Advantage: Full Swing• Restorer adds capacitance, takes away pull down current at X• Ratio problem
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Restorer SizingRestorer Sizing
0 100 200 300 400 5000.0
1.0
2.0
W/Lr =1.0/0.25 W/Lr =1.25/0.25
W/Lr =1.50/0.25
W/Lr =1.75/0.25
Vol
tage
[V]
Time [ps]
3.0•Upper limit on restorer size•Pass-transistor pull-downcan have several transistors in stack
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Solution 2: Single Transistor Pass Gate with Solution 2: Single Transistor Pass Gate with VVTT=0=0
Out
VDD
VDD
2.5V
VDD
0V 2.5V
0V
WATCH OUT FOR LEAKAGE CURRENTS
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Complementary Pass Transistor LogicComplementary Pass Transistor Logic
A
B
A
B
B B B B
A
B
A
B
F=AB
F=AB
F=A+B
F=A+B
B B
A
A
A
A
F=A⊕ΒÝ
F=A⊕ΒÝ
OR/NOR EXOR/NEXORAND/NAND
F
F
Pass-TransistorNetwork
Pass-TransistorNetwork
AABB
AABB
Inverse
(a)
(b)
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Solution 3: Transmission GateSolution 3: Transmission Gate
A B
C
C
A B
C
C
BCL
C = 0 V
A = 2.5 V
C = 2.5 V
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Resistance of Transmission GateResistance of Transmission Gate
Vout
0 V
2.5 V
2.5 VRn
Rp
0.0 1.0 2.00
10
20
30
Vout, V
Res
ista
nce,
ohm
s
Rn
Rp
Rn || Rp
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PassPass--Transistor Based MultiplexerTransistor Based Multiplexer
AM2
M1
B
S
S
S F
VDD
GND
VDD
In1 In2S S
S S
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Transmission Gate XORTransmission Gate XOR
A
B
F
B
A
B
BM1
M2
M3/M4
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Delay in Transmission Gate NetworksDelay in Transmission Gate Networks
V1 Vi-1
C
2.5 2.5
0 0
Vi Vi+1
CC
2.5
0
Vn-1 Vn
CC
2.5
0
In
V1 Vi Vi+1
C
Vn-1 Vn
CC
InReqReq Req Req
CC
(a)
(b)
C
Req Req
C C
Req
C C
Req Req
C C
Req
CIn
m
(c)
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Delay OptimizationDelay Optimization
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Transmission Gate Full AdderTransmission Gate Full Adder
A
B
P
Ci
VDDA
A A
VDD
Ci
A
P
AB
VDD
VDD
Ci
Ci
Co
S
Ci
P
P
P
P
P
Sum Generation
Carry Generation
Setup
Similar delays for sum and carry
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Dynamic LogicDynamic Logic
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Dynamic CMOSDynamic CMOS
In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.
fan-in of n requires 2n (n N-type + n P-type) devices
Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.
requires on n + 2 (n+1 N-type + 1 P-type) transistors
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Dynamic GateDynamic Gate
In1
In2 PDNIn3
Me
Mp
Clk
ClkOut
CL
Out
Clk
Clk
A
BC
Mp
Me
Two phase operationPrecharge (CLK = 0)Evaluate (CLK = 1)
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Dynamic GateDynamic Gate
In1
In2 PDNIn3
Me
Mp
Clk
ClkOut
CL
Out
Clk
Clk
A
BC
Mp
Me
Two phase operationPrecharge (Clk = 0)Evaluate (Clk = 1)
on
off
1off
on
((AB)+C)
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Conditions on OutputConditions on Output
Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.Inputs to the gate can make at most one transition during evaluation.
Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL
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Properties of Dynamic GatesProperties of Dynamic GatesLogic function is implemented by the PDN only
number of transistors is N + 2 (versus 2N for static complementary CMOS)
Full swing outputs (VOL = GND and VOH = VDD)Non-ratioed - sizing of the devices does not affect the logic levelsFaster switching speeds
reduced load capacitance due to lower input capacitance (Cin)reduced load capacitance due to smaller output loading (Cout)no Isc, so all the current provided by PDN goes into discharging CL
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Properties of Dynamic GatesProperties of Dynamic GatesOverall power dissipation usually higher than static CMOS
no static current path ever exists between VDD and GND (including Psc)no glitchinghigher transition probabilitiesextra load on Clk
PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn
low noise margin (NML)Needs a precharge/evaluate clock
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Issues in Dynamic Design 1: Issues in Dynamic Design 1: Charge LeakageCharge Leakage
CL
Clk
ClkOut
A
Mp
Me
Leakage sources
CLK
VOut
Precharge
Evaluate
Dominant component is subthreshold current
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Solution to Charge LeakageSolution to Charge Leakage
CL
Clk
Clk
Me
Mp
A
B
Out
Mkp
Same approach as level restorer for pass-transistor logic
Keeper
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Issues in Dynamic Design 2: Issues in Dynamic Design 2: Charge SharingCharge Sharing
CL
Clk
Clk
CA
CB
B=0
AOut
Mp
Me
Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness
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Charge Sharing ExampleCharge Sharing Example
CL=50fF
Clk
Clk
A A
B B B !B
CC
Out
Ca=15fF
Cc=15fF
Cb=15fF
Cd=10fF
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Charge SharingCharge Sharing
CLVDD CLVout t( ) Ca VDD VTn VX( )–( )+=
or
∆Vout Vout t( ) VDD–CaCL-------- VDD VTn VX( )–( )–= =
∆Vout VDDCa
Ca CL+----------------------
–=
case 1) if ∆Vout < VTn
case 2) if ∆Vout > VTnB = 0
Clk
X
CL
Ca
Cb
A
Out
Mp
Ma
VDD
Mb
Clk Me
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Solution to Charge RedistributionSolution to Charge Redistribution
Clk
Clk
Me
Mp
A
B
OutMkp
Clk
Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)
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Issues in Dynamic Design 3: Issues in Dynamic Design 3: BackgateBackgate CouplingCoupling
CL1
Clk
Clk
B=0
A=0
Out1Mp
Me
Out2
CL2In
Dynamic NAND Static NAND
=1 =0
EE14182
© Digital Integrated Circuits2nd Combinational Circuits
BackgateBackgate Coupling EffectCoupling Effect
-1
0
1
2
3
0 2 4 6
Vol
tage
Time, ns
Clk
In
Out1
Out2
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EE14183
© Digital Integrated Circuits2nd Combinational Circuits
Issues in Dynamic Design 4: Clock Issues in Dynamic Design 4: Clock FeedthroughFeedthrough
CL
Clk
Clk
B
AOut
Mp
Me
Coupling between Out and Clk input of the prechargedevice due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.
EE14184
© Digital Integrated Circuits2nd Combinational Circuits
Clock Clock FeedthroughFeedthrough
-0.5
0.5
1.5
2.5
0 0.5 1
Clk
Clk
In1
In2
In3
In4
Out
In &Clk
Out
Time, ns
Vol
tage
Clock feedthrough
Clock feedthrough
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EE14185
© Digital Integrated Circuits2nd Combinational Circuits
Other EffectsOther Effects
Capacitive couplingSubstrate couplingMinority charge injectionSupply noise (ground bounce)
EE14186
© Digital Integrated Circuits2nd Combinational Circuits
Cascading Dynamic GatesCascading Dynamic Gates
Clk
Clk
Out1In
Mp
Me
Mp
Me
Clk
Clk
Out2
V
t
Clk
In
Out1
Out2 ∆V
VTn
Only 0 → 1 transitions allowed at inputs!
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EE14187
© Digital Integrated Circuits2nd Combinational Circuits
Domino LogicDomino Logic
In1
In2 PDNIn3
Me
Mp
Clk
Clk Out1
In4 PDNIn5
Me
Mp
Clk
ClkOut2
Mkp
1 → 11 → 0
0 → 00 → 1
EE14188
© Digital Integrated Circuits2nd Combinational Circuits
Why Domino?Why Domino?
Clk
Clk
Ini PDNInj
IniInj
PDN Ini PDNInj
Ini PDNInj
Like falling dominos!
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EE14189
© Digital Integrated Circuits2nd Combinational Circuits
Properties of Domino LogicProperties of Domino Logic
Only non-inverting logic can be implementedVery high speed
static inverter can be skewed, only L-H transitionInput capacitance reduced – smaller logical effort
EE14190
© Digital Integrated Circuits2nd Combinational Circuits
Designing with Domino LogicDesigning with Domino Logic
Mp
Me
VDD
PDN
Clk
In1In2
In3
Out1
Clk
Mp
Me
VDD
PDN
Clk
In4
Clk
Out2
Mr
VDD
Inputs = 0during precharge
Can be eliminated!
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EE14191
© Digital Integrated Circuits2nd Combinational Circuits
Footless DominoFootless Domino
The first gate in the chain needs a foot switchPrecharge is rippling – short-circuit currentA solution is to delay the clock for each stage
VDD
Clk Mp
Out1
In1
1 0
VDD
Clk Mp
Out2
In2
VDD
Clk Mp
Outn
InnIn3
1 0
0 1 0 1 0 1
1 0 1 0
EE14192
© Digital Integrated Circuits2nd Combinational Circuits
Differential (Dual Rail) DominoDifferential (Dual Rail) Domino
A
B
Me
Mp
Clk
ClkOut = AB
!A !B
MkpClk
Out = ABMkp Mp
Solves the problem of non-inverting logic
1 0 1 0
onoff
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EE14193
© Digital Integrated Circuits2nd Combinational Circuits
npnp--CMOSCMOS
In1
In2 PDNIn3
Me
Mp
Clk
Clk Out1
In4 PUNIn5
Me
MpClk
Clk
Out2(to PDN)
1 → 11 → 0
0 → 00 → 1
Only 0 → 1 transitions allowed at inputs of PDN Only 1 → 0 transitions allowed at inputs of PUN
EE14194
© Digital Integrated Circuits2nd Combinational Circuits
NORA LogicNORA Logic
In1
In2 PDNIn3
Me
Mp
Clk
Clk Out1
In4 PUNIn5
Me
MpClk
Clk
Out2(to PDN)
1 → 11 → 0
0 → 00 → 1
to otherPDN’s
to otherPUN’s
WARNING: Very sensitive to noise!