high-level test generation
DESCRIPTION
High-Level Test Generation. Test Generation by Enhancing Validation Test Sets*. * L. Lingappan, et al., VLSI Design, 2007 (Paper available on the class website). Basic Idea. Reuse validation test sequences Fixed control sequence, only data path values need to be determined - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/1.jpg)
High-Level Test Generation
![Page 2: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/2.jpg)
Test Generation by Enhancing Validation Test
Sets*
* L. Lingappan, et al., VLSI Design, 2007 (Paper available on the class website)
![Page 3: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/3.jpg)
SAT-Based Diagnosis 3
Basic Idea
Reuse validation test sequencesFixed control sequence, only data path values need to be determinedPrecomputed module tests are usedIf validation sequences are instruction-level, so are the generated testsRTL level analysis means faster times
![Page 4: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/4.jpg)
SAT-Based Diagnosis 4
Details
Basis for analysis:RTL circuit and controller FSMCDFG and state transition sequence for a given validation test sequence
Not all test sequences are analyzed for all precomputed test vectors because this could be computationally expensive. Instead, heuristics are used to determine compatibility.
![Page 5: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/5.jpg)
SAT-Based Diagnosis 5
ProcessFault simulate validation test sequences and determine the activation time cycle for each detected fault.If a detected fault falls within a module, the sequence is a candidate for applying precomputed test vectors
Determine compatibility of each test vector with the sequenceIf compatible, then justify and propagate
![Page 6: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/6.jpg)
SAT-Based Diagnosis 6
Example RTL Circuit
![Page 7: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/7.jpg)
SAT-Based Diagnosis 7
Controller Specification
![Page 8: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/8.jpg)
SAT-Based Diagnosis 8
CDFG and State Transition Sequence Exercised by test
T1
![Page 9: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/9.jpg)
SAT-Based Diagnosis 9
Activation and Detection Cycle
for Target Fault
![Page 10: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/10.jpg)
SAT-Based Diagnosis 10
Justification of Required Values-1
![Page 11: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/11.jpg)
SAT-Based Diagnosis 11
Justification of Required Values-2
![Page 12: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/12.jpg)
SAT-Based Diagnosis 12
Circuits Used in Experiments
![Page 13: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/13.jpg)
SAT-Based Diagnosis 13
Test Generation Results
![Page 14: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/14.jpg)
Test Generation with Functional Fault Modleing*
* Hansen and Hayes, VLSI Test Symposium, 1995, pp. 20-28.
![Page 15: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/15.jpg)
SAT-Based Diagnosis 15
Summary
High-level fault modeling ensuring coverage of low-level (physical or single-stuck-line) faults.Fault effects induced from low (gate) to high (RTL or functional) levelAllows discovery of minimum test sets at the high level that are hard to find by low (gate-level) techniques
![Page 16: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/16.jpg)
SAT-Based Diagnosis 16
Functional Fault ModelsGeneral Faults (Universal)Pin FaultsBoth of the above are implementation and
technology independent
Induced faults: Physically Induced Faults (PIFs) Derived from an implementation by the induction process, hence implementation dependent and may be technology dependent.PIFs derived from single stuck-at faults are denoted as SIFs in the paper.
![Page 17: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/17.jpg)
SAT-Based Diagnosis 17
Faults, Functions, and Tests
![Page 18: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/18.jpg)
SAT-Based Diagnosis 18
Example
Consider the effect of some sample SAFs on the circuit function:
A SA0A SA1AP SA0
![Page 19: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/19.jpg)
SAT-Based Diagnosis 19
SIFs of the Example CircuitConsider Fault Dominance:
Top 6 dominate the rest, hence only need to cover these.
![Page 20: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/20.jpg)
SAT-Based Diagnosis 20
Minimal SIF Test Set
![Page 21: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/21.jpg)
SAT-Based Diagnosis 21
Dependence on Implementation
(b) and (c) havefault functions notcovered by thoseof (a). Hence requireadditional SIFs
![Page 22: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/22.jpg)
SAT-Based Diagnosis 22
Extension to Ripple-Carry Circuit
Ci+1
M
Ci
Ai
Bi
MC0
A0
B0
MC1
A1
B1
MC2
A2
B2
MC3
A3
B3
C4
How many SIF tests are required for the RCC?
![Page 23: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/23.jpg)
SAT-Based Diagnosis 23
Test Set Sizes
![Page 24: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/24.jpg)
SAT-Based Diagnosis 24
Larger Examples
CLA Generator (74182)
• Eliminate the logic gates for G and P in the carry circuit• Cascade the above module as in the RCC.
How do the SIFs change for the module?How many tests for the whole circuit?
![Page 25: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/25.jpg)
SAT-Based Diagnosis 25
Tests Required for 4-bit CLA Generator
![Page 26: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/26.jpg)
SAT-Based Diagnosis 26
4-bit Adder (74283)The 10 tests for CLA can be extended to cover the XOR modules. Hence 10 tests suffice for this circuit also.
![Page 27: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/27.jpg)
SAT-Based Diagnosis 27
ALU Circuit (74181)CLA again dominates the test generation.12 Tests are required, of which 10 correspond to testing CLA.
![Page 28: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/28.jpg)
SAT-Based Diagnosis 28
Summary of Results(For Medium Circuits)
![Page 29: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/29.jpg)
SAT-Based Diagnosis 29
The paper goes on to apply the technique to ISCAS85 circuits. They needed to extract high-level models for these circuits by painstaking reverse-engineering. These models are available from Prof. Hayes’ website at U. Michigan.
![Page 30: High-Level Test Generation](https://reader035.vdocuments.us/reader035/viewer/2022062314/5681327c550346895d991724/html5/thumbnails/30.jpg)
SAT-Based Diagnosis 30
ConclusionPhysical fault effects induced at the functional levelUnlike prior high-level models, PIFs allow complete low-level coverage.However, the analysis is not automatic and the results do depend on the implementationThe technique allowed obtaining provably minimum test sets for various common known implementations.