1

HENDA and PataraA solid state neutron detector and a prototype readout chip for the SNS

Steven C. Bunch, Jonathan L. Britton, Benjamin J. BlalockThe University of Tennessee

Charles L. Britton, Jr.The University of Tennessee/Oak Ridge National Laboratory

Douglas S. McGregor (P.I.), Russell Taylor, Tim Sobering, David Huddleston, Walter McNeil, Troy Unruh, Blake Rice, Steven Bellinger, Brian Cooper

Kansas State University

Lowell CrowSpallation Neutron Source/Oak Ridge National Laboratory

A research project funded by the National Science Foundation

2

Outline

• Spallation Neutron Source (SNS) Overview

• Neutron Detector Overview (HENDA)

• Chip Architecture (Patara)

• Measurements

• Next Steps

• Conclusion

3

SNS Overview

The Spallation Neutron Source (SNS)

• Accelerator-based neutron source being built in Oak Ridge, Tennessee, by the U.S. Department of Energy.

• It will provide the most intense pulsed neutron beams in the world for scientific research and industrial development.

• At a total cost of $1.4 billion, construction began in 1999 and will be completed in 2006.

• The construction of SNS was a partnership of six U.S. Department of Energy national laboratories: Argonne, Brookhaven, Jefferson, Lawrence Berkeley, Los Alamos, and Oak Ridge.

• This collaboration was one of the largest of its kind in U.S. scientific history and was used to bring together the best minds and experience from many different fields.

For more information see http://www.sns.gov

The SNS at ORNL is changing from a project into a facility! The first spallation neutrons were produced on April 28, 2006

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SNS InstrumentsVULCAN is a compound diffractometer for engineering applications

PSD

ElasticallyBent Si Xtal

Sample

Bragg focusing can achieve spatial resolution of 0.1 mm, but a 1D high resolution neutron detector is required to use it efficiently.

SNAPSNAP (Spallation Neutrons and Pressure) is a Neutron (Spallation Neutrons and Pressure) is a Neutron Diffraction Instrument Dedicated to High Pressure ResearchDiffraction Instrument Dedicated to High Pressure Research

Diamond anvil cell samples may be very small, so high resolution detectors are needed to resolve the diffraction pattern.

Motivates development of a 2D version

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Neutron Detector Overview

High Efficiency Neutron Detector Array (HENDA)

• Semiconductor linear thermal neutron detection imaging array• Reaction - n + 6Li 4He + 3H + 4.79 MeV• Pixel dimensions are 80 microns wide, and 4 cm long, with a 100 micron pitch• Contains 1000 pixels, each with expected intrinsic thermal neutron detection efficiency of

>20%• Millions of holes filled with neutron reactive material increase the detector efficiency

Linear pixels and bonding pads Etched holes >170

microns deep30 micron diameter holes with 6LiF

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Measured results show that the efficiency is greatly increased with the perforated design

6LiF Film Thickness (microns)

0 5 10 15 20 25 30 35 40

Per

cent

The

rmal

Neu

tron

Det

ectio

n E

ffici

ency

0123456789

10111213

Holes Unfilled Predicted for Planar Device

Holes Filled with 6LiF

With the perforated surface coated with 6LiF material, with holes not yet filled, already shows improvement over basic planar designs

With the holes backfilled with 6LiF, the thermal neutron detection efficiency is greatly increased

Detector Measurements

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Prototype Chip Architecture “Patara”

Specifications– Pulse-Processing Requirements

• Pulse rate – 10 kcps

• Pulse-Pair Resolution – 1s

– General Signal-Processing Requirements• For 10B detector coatings

– 300 keV – 1.47 MeV or 12.8 fC – 65.6 fC

• For 6Li detector coatings– 300 keV – 2.7 MeV or 12.8 fC – 120 fC

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Chip Design Specifications

• Preamplifier– Noise dominated by input FET < 1000 rms electrons

• System uncertainties of a few keV necessary for lower-level gamma discrimination threshold of ~300 keV

– Accept positive or negative input– Detector leakage current compensation– Able to handle detector capacitance up to 10 pF– Pole/Zero compensation network– Full gain or half gain adjustment

• Shaper– Adjustable polarity– Four complex conjugate poles– Low noise < 10% of preamplifier (low-gain system)– FWHM ~ 270 ns– Settling time ~ 600 ns

• Baseline Restorer– “Ground sensing” inputs

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Preamplifier

• Regulated cascode topology

• M1 designed to optimize noise for detector capacitance of 5 pF using Cgs = method

3detC

• M2 & M3 sized to contribute < 10% of M1 noise

• Cc of 0.3 pF used to control stability of negative feedback loop between M2 & M3

• Feedback network needed to allow Cf to discharge after a charge pulse

VDD

Qin

Vout

M1

M2

M3

Cc

Ibias

CfFeedbackNetwork

M4

M5M6 M7 M8 M9

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Final Preamplifier Pole/Zero Compensation

Ibias

2 x Ibias

Vref

A

Vdd

Vdd

V-

Cf

15 x Ibias

30 x Ibias

Vref Vdd

Vdd

15 x CfA

Cf2

Rf2

To Shaping Circuit

15x

15x

• Based on MOSFET feedback network and pole/zero compensation – Ludewigt, et al., TNS, vol. 41, no. 4, 1994.

• Adapted from Low Frequency Feedback Loop topology

• Increase Ibias to compensate for detector leakage up to 15 nA

• Adjustable Vref sets dynamic range for either polarity input

• Approximately 1.6 mW/channel

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Preamplifier Feedback Network Biasing

Ibias

Vdd

2 x Ibias

To Feedback Network

DS0 DS1 DS2 DS3 DS0 DS1 DS2 DS3

W 2 x W 4 x W 8 x W 16 x W2 x W 4 x W 8 x W

Henri J. Oguey and Daniel Aebischer, “CMOS Current Reference Without Resistance,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 7, pp. 1132-1135, 1997.

• Nanoampere current reference

• Switchable bias current for detector leakage current compensation

• Allows pole/zero compensation network to track feedback bias

To Pole/Zero Compensation Network Bias

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Shaper Design Process

• Shape pulse using 5-pole complex-conjugate semi-Gaussian filter

• Pole-zero constellation optimized using MATLAB to approximate Gaussian shape

• MATLAB script iterations using ‘radial variation’ and sensitivity analyses

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Shaper Fundamentals

• Semi-Gaussian pulse response with 1 real, 4 complex poles• 1 μ-sec pulse-pair resolution with gated baseline restoration (SNS synchronous)• Current-mode quasi-linear operation

Real Pole 2

Real Pole 3

Real Pole 4

Real Pole 5H(s) = G

323

2

2

11)(

ss

KsH

545

2

3

11)(

ss

KsH

V to I Converter Localized Feedback Localized Feedback

VoutReal Pole 1(Op-Amp)

Ideally, G

1 Real Pole

1

1

1)(

s

KsH

Vbaseline

Vin

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Complex Conjugate Topology

• Modified R-lens magnification

• Intrinsically low-noise

• R magnification allows small physical R to give low-frequency pole

• At higher signal levels, circuit is dynamic, but magnified small physical R dominates 1/gm for improved linearity over Gm-C filters

Vdd

Iout(to next CC stage)

Ibias

Iin

Vout(last stageonly)

R RC2C1

G. Bertuccio, et al., “‘R-lens filter’: An (RC)n current-mode lowpass filter,” Electronics Letters, vol. 35, no. 15, 22nd July 1999.

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Noise MeasurementsSingle Channel Noise vs Detector Capacitance

300

400

500

600

700

800

900

1000

1100

1200

1300

0 5 10 15 20 25

Cdet (pF)

Noi

se (r

ms

elec

tron

s)

Measured

Simulated

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Noise MeasurementsSingle Channel Noise vs Input FET Bias

300

500

700

900

1100

1300

1500

60 80 100 120 140 160 180 200 220

Bias Current (uA)

Noi

se (r

ms

elec

tron

s)

0pF Detector Capacitance

Simulated

Measured

Measured

Simulated

15pF Detector Capacitance

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Gain MeasurementsSystem Gain vs Channel

4

5

6

7

8

9

10

1 4 7 10 13 16

Channel

Gai

n (m

V/fC

)

Full Gain Setting

Half Gain Setting Positive Polarity Input

Positive Polarity Input

Negative Polarity Input

Negative Polarity Input

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• Pulse shape matches simulations very closely

• FWHM ≈ 290 nsec

• Full analysis of ‘dynamic noise’ upcoming

• End-to-end nonlinearity < 5% in range of interest

• Approximately 2.1 mW/channel

Linearity - End-to-end (all)

0

100

200

300

400

500

600

700

0 100 200 300 400 500 600 700

Vin (mV)

Vout

(mV)

Shaper Measurements

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Next Steps

• Discriminator, zero suppression, “SNS standard interface”

• 64-128 channels

• Interface with KSU HENDA

• Integrate with SNS system for tests

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Conclusions

• Prototype chip fully functional on first-cut silicon with 3.7mW/channel power dissipation

• Second fabrication pass in July 2006 for BLR offset improvements

• Test at SNS in late summer 2006 with 252Cf sources

• Submission of large final chip late in 2006