hardware part 1

8/7/2019 hardware part 1

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Shivashankar B. Nair

Associate Professor,

De artment of Com uter Science &Engineering,

IITG

Tuesday, January 25, 2011



a se or rue1 True (or False)

current in a massively complex circuit to obtain the

desired net effect!




numbers – 0 and 1. Numbers could be – 00 01 10 11 meanin

0,1,2,3 in decimal)

Bit: Binar Di it

4 bits make a Nibble and 8 bits make a Byte

Usin 2 bits we can enerate 4 combinations

Using n bits we can generate 2n combinations




The Truth TablePCBA

0100

0000

Alarm system ActiveB

A

P

0001

0110C

The buzzer sounds onlyunder this condition -

A . B . C1011

0101


0111



must be closed Logic notation AB = C

00 00 00

11 00 00




Logic notation A + B = C

00 00 00

11 00 11




A + B = B + A A B = B A

Same as




AA QQ

11 00

AQ =Logic:




AA BB SS

Either A or B, but not both

This is sometimes called the inequality

11 00 11

detector, because the result will be 0when the inputs are the same and 1when the are different.

00 11 1111 11 00

The truth table is the same as for=


.



S1 S0 Q0 Q1 Q2 Q3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1




xx yy zz DD DD DD DD DD DD DD DD

00 00 00 11 00 00 00 00 00 00 00

D0D1D2

D3D4

InputCode

Only one output is activated (HIGH)3 x 8Decoder

22

21

x

y

00 11 00 00 00 11 00 00 00 00 00

D5D6D7

z

11 00 00 00 00 00 00 11 00 00 00

11 11 00 00 00 00 00 00 00 11 00

11 11 11 00 00 00 00 00 00 00 11




Application (Firefox/Netscape)

peration ystem

(Unix, Windows

9x)

Compiler

AssemblerSoftware

InstructionSetArchitectur

Processor Memory I/O systemHardwar

e

Data path & Control

Digital Design

e


rcu es gn

Transistors, IC design



° Application Level - All kinds of application programs written inHigh Level Languages

° Compilation Level - Each high level program is compiled intomac ine co e

° Operation System Level - Set of services for managing resources ofa computer

° ns ruc on e rc ec ure eve - e es gn o s eveinvolves specification of

a) memory space

c) instruction format

…..

°

croarc ec ure eve - mp emen a on an rgan za on ohardware components

° Logic & Circuit Design Level - Design of Components in specific

° Device and Technology Level - Manufacturing , packing etc.




High Level LanguageProgram ( e.g., C , C++)

temp = v[k];v[k] = v[k+1];

Compiler

v[k+1] = temp;

lw $15, 0($2)

ssem y anguage

Program

Assembler

sw $16, 0($2)

sw $15,4($2)

Machine LanguageProgram

0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 01101100 0110 1010 1111 0101 1000 0000 1001

Machine Interpretation

<- <- +


Specification



Processor (CPU)

Input

Address Bus

contro Devices

Data Bus

MemoryI/O

ALU &Datapath Output

Devices

Control Bus




CPU MemoryAddress Bus

Data Bus

m

n

Control Bus k

I/O Device I/O Device

…….


u -sys em



S1 S0 Q0 Q1 Q2 Q3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

S1 S0 Q0 Q1 Q2 Q3

I0 I0

0

0 1 0 I1 0 0

1 0 0 0 I2 0

1 1 0 0 0 I3

I1

I2

I1

I2

I3 I3S1 S0 Output

0 0 I0


1 0 I2

1 1 I3



Capable of performing :Arithmetic and Logic operations

Takes inputs, A,B and outputs R based on the function Frequired to be performed

Also has side outputs D that indicate, for instance,

Carry, Borrow, Zero, Parity,…

Flags??

–

How is it designed?Si nificance of ALU and the rocessin ca abilit of the CPU




Block for storing data for later retrieval.

instructions). Conce tuall , a com uter memor is sim l a

collection of locations where information can be

stored as bits. os o en, memory s y e-a ressa e. smeans it is divided into bytes (8-bit quantities)each identified b a uni ue address.

Generally, bytes are addressed sequentially,beginning with address 0.




No. of words X No. of bits bit/word= =. . , ,…

Read Only Memory (ROM)




Both could be RAMs

Huh, how is that?


hardware part 1

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