hardware part-ii
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Multiplexer: Transforming a decoder into a
MUXS1 S0 Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
S1 S0 Q0 Q1 Q2 Q3
I0
I0
0
0 1 0 I1 0 0
1 0 0 0 I2 0
1 1 0 0 0 I3
I1
I2
I1
I2
I3 I3S1 S0 Output
0 0 I0
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1 0 I2
1 1 I3
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D0
D1
.
.
.
.
..
D
.
.
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Select Lines S0,S1…
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Capable of performing :
Arithmetic and Logic operations
Takes inputs, A,B and outputs R based on the function F required to
be performed
Also has side outputs D that indicate, for instance,
Carry, Borrow, Zero, Parity,…
Flags??
–
How is it designed?
Si nificance of ALU and the rocessin ca abilit of the CPU
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Memory
• Block for storing data for later retrieval.
• .
• Conceptually, a computer memory is simply a
collection of locations where information can be
stored as bits.
• Most often, memory is byte‐addressable. This means
s v e n o y es ‐ quan es eac
identified by a unique address.
• ,
,
with address 0.
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Memor Subs stem
• S ecified as:
No. of words X No. of bits bit/wordE.g. 1024X1 = 1Kbit, 2048X8=2KByte,…
• Main Types of (Semiconductor) MemoryRead Only Memory (ROM)
Random Access Memory (RAM)
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• Both could be RAMs
• Huh, how is that?
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Read Onl Memor ROM
• PC uses it to hold BIOS both for system and I/O
adapters.• Slow (100 – 200 nanoseconds).
• o en cop e n o
• Various forms:
EPROM
EEPROM
• Non volatile.
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Random Access Memory ‐ Read/Write MemoryKey Features
• s are pac age as a c p.
• Basic storage unit is a cell ( one bit per cell).
• Multiple RAM chips form a memory unit.
• Volatile.
Static RAM (SRAM)• Each cell stores a bit with a six‐transistor circuit.
• e a ns va ue n e n e y, as ong as s ep powere .
• Relatively insensitive to disturbances such as electrical noise.
• Faster and more expensive than DRAMs.
• Low packing density
• Bipolar based
Dynamic RAM (DRAM)
.• Value must be refreshed every 10‐100 ms.
• Sensitive to disturbances.
• Slower and cheaper than SRAMs.
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• High Packing density
• MOS Unipolar based.
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RAM: One bit ‐
• Note that data goes to both S and R
•
• Read/write enables read or write, but not both
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RAM (R/W Memory)One WordData input
Sel
Inp
Out
Address Bus
R/W
Control Bus
° How many address bits
would I need for 16
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wor s
4x4 RAMData output
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RAM
• Address inputs go into
1 0 0 1
decoder
– Only one output active
• Word line selects a row of
1
0
bits (word)
• Data passes through OR
gate•
** * * *> >>>1
stores one bit
• Input data stored if Read/Write is 0
1
• u pu
a a
r ven
Read/Write is 1
Thursday, February 17, 20114x4
RAM
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RAM Reading
1
0
** * * *1 0 0 1
0
Thursday, February 17, 20114x4
RAM
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Memor
•
Din
Data input bus CS
Address Memory
Addr
ea r e con ro
Chip SelectR/W
Size: m x n
where m = no. of words & n = bits/word
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Dout
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MemoryAddress Bus
Control Bus
Data bus ‐
Bidirectional
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• ‐ , ,
• Tri‐state Buffers
Input
Control
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Memor Access Methods 1
• Sequential
– Start
at
the
beginning
and
read
through
in
order – Access time depends on location of data and previous
location
– e.g. tape
• Direct – n v ua oc s ave un que a ress
– Access is by jumping to vicinity plus sequential search
– Access time depends on location and previous location
– e.g. disk
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Memor Access Methods 2
• Random
– Individual addresses identify locations exactly – Access time is independent of location or previous access
– e.g. RAM
• Associative
–
of the store
– Access time is independent of location or previous access
– e.g. cache
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The Goal: Lar e fast chea memor
• ,
memories are small (?)
,
cheap and fast (most of the time)?
– erarc y
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An Ex anded View of the Memor S stem
processor
control
Data ath
m e m o
m e m o r
memorymemory
memory
r y
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Speed:Size:
Cost:
Fastes
tSmallest
Highest
Slowest
BiggestLowest
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Wh a hierarch
•
A Program accesses a relatively small portion of the
.
Probabilit of
reference
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0 Address space
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• Temporal locality: (Locality in Time): If an item is
, . .,
loops, reuse)
• S atial localit : If an item is referenced items whose
addresses are close by tend to be referenced soon
(e.g., straight-line code, array access)
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Levels of the Memory HierarchyUpper Level
Capacity Access Time
Cost
Staging Xfer Unit faster
100s Bytes
<10s ns
Registers
Cache
prog./compiler1‐8 bytesInstr. Operands
10‐100 ns1‐0.1 cents/bit
Main Memory
cache cntl8‐128 bytesBlocks
Memory200ns‐ 500ns$.0001‐.00001 cents /bit
Disk OS512‐4K bytes
Pages
Disk
,
(10,000,000 ns)
10 ‐ 10 cents/bituser/operatorMbytesFiles
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Tape
apeinfinitesec‐min
10 Lower Level
Larger
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Memory Hierarchy: Cache
• : a a per a n ng o e accesse a ress s oun n a oc
in the cache
– Hit Rate: the fraction of cache memory access
– Hit Time: Time to access the cache
• Miss: Data needs to be retrieved from the Main Memory – Miss Rate = 1 ‐ (Hit Rate)
– Miss Penalty: Time to replace a block in the cache +
Time to deliver the data to the processor
• Hit Time << Miss Penalt
MemoryCacheMemory
To Processor
Blk X
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Blk Y
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Different levels of cache memory
CPU chipUNIFIED
L2 CACHE UNIFIED
CPU
Package
‐ n ‐
CACHEMAINmemory
Keyboard Graphics
Controller
Disk
Controller
Processor
Board
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SPLIT L1 Instruction and Data CacheBoard‐Level Cache
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Cache o eration‐
overview
•
• Checks cache for this data.• , .
• If not present, reads required block from the main
• Subsequent accessions are (hopefully) delivered
from cache to CPU.
• Cache includes tags to identify which block of main
memory is in each cache slot.
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Cache Desi n
•
• Replacement Algorithm
• Write Po icy
• Block Size• Number of Caches
•
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