Group M3Jacob ThomasNick MarwahaCraig LeVanDarren ShultzProject Manager: Zachary Menegakis April 11, 2005

MILESTONE 12 Final LVS & Simulation

DSP 'Swiss Army Knife'

Overall Project Objective: General Purpose Digital Signal Processing Chip

STATUS

Design Proposal (Done) Architecture (Done) Size Estimates/Floorplan/Verilog (Done) Gate Level Design (Done) Testing of Top-Level Schematic (Done) LVS of Entire Chip (Done!) Simulations (75%) Soft IP (Done!) To Be Done

Instantiate Remaining Buffered Components Simulations of Top Level with Buffers

DESIGN DECISIONS

Rewired top level to remove white space on the bottom of the circuit.

Buffers after FP Adders & FP Mults Vdd Rails need to be widened as

power drops in circuit

TOP LEVEL LAYOUT – OLD

TOP LEVEL LAYOUT – LVS’d!

@(#)$CDS: LVS version 5.0.0 06/02/2003 20:45 (intelibm5) $

Like matching is enabled.Using terminal names as correspondence points.

Net-list summary for /afs/ece.cmu.edu/usr/nmarwaha/cds/LVS/layout/netlist count

14738 nets88

terminals16592

pmos16592

nmos

Net-list summary for /afs/ece.cmu.edu/usr/nmarwaha/cds/LVS/schematic/netlist count

15103 nets90

terminals365

cds_thru16592

pmos16592

nmos

Terminal correspondence points 1 N 2 Xn<0> 3 Xn<10>…

The net-lists match…

SIZE ESTIMATES

Transistor Count: 33,184Area: ~ 395x435 µm

(172,000 µm2)Density: ~0.193 (w/o buffers)

Aspect Ratio: ~1:1

FP Adder - Verified

•Outputs of Layout Match Schematic!

•Buffered Adder has much improved Rise/Fall Time of ~350ps vs. 1.5ns unbuffered

Wallace Tree - Verified

•Outputs of Layout Match Schematic!

•Wallace here is unbuffered

Top Level – Awaiting Sims

• CRITICAL PATH: Input->comb_16->adder->mult->adder->Output

• To Test Top Level: Using inputs from our main ‘Swiss Army Knife’ Paper to verify all functions

SOFT IP – Done!

Top Level Verilog Verified Complex Function

PROBLEMS & QUESTIONS

Difficulty Extracting & Simulating Frequently get error when trying to extract circuit (happens randomly) Slows down progress when trying to simulate modified versions

(currently waiting on top level simulation)

Buffering Added to FP Adder Added to FP Multiplier (currently working on more versions to better fit w/

chip) Added to Outputs in Top Level Need to stretch wires & instantiate layouts with buffers for top level

Would like to reduce white space in the center of circuit