Group M3Nick MarwahaCraig LeVanJacob ThomasDarren ShultzProject Manager: Zachary Menegakis April 4, 2005

MILESTONE 11 LVS & Simulation

DSP 'Swiss Army Knife'

Overall Project Objective: General Purpose Digital Signal Processing Chip

STATUS

Design Proposal (Done) Architecture (Done) Size Estimates/Floorplan/Verilog (Done) Gate Level Design (Done) Testing of Top-Level Schematic (Done) LVS of Entire Chip (98%)

LVS of FP Adder (Done) LVS of FP Multiplier (Done) LVS of Delay for Comb (Done)

Simulations (50%) To Be Done

Connect Few Remaining Bus Lines at Top Level Top Level Simulation Optimizations – Add Buffers & Reduce White Space

DESIGN DECISIONS

Modified Registers to Improve TestingAdded Reset

Vertically Stretched FP AdderReduces need to use Metal4 to allow

room for global routing along left side

STRATEGY for TESTING &CRITICAL PATH ESTIMATION

Strategy for Testing Test the main components individually

• Floating Point Adder• Floating Point Multiplier• Comb

Test the top level• Simpler to more complex inputs

Critical Path Currently determining, but believe it’s a

particular path through the FP_Adder

LAYOUT – Delay (Comb)

LAYOUT – FP Adder@(#)$CDS: LVS version 5.0.0 06/02/2003 20:45 (intelibm5) $

Like matching is enabled.Using terminal names as correspondence points.

Net-list summary for /afs/ece.cmu.edu/usr/nmarwaha/cds/LVS/layout/netlist count

949 nets39 terminals1111 pmos1111 nmos

Net-list summary for /afs/ece.cmu.edu/usr/nmarwaha/cds/LVS/schematic/netlist count

960 nets39 terminals11 cds_thru1111 pmos1111 nmos

Terminal correspondence points 1 A<0> 2 A<10> 3 A<11> 4 A<1> 5 A<2> 6 A<3> 7 A<4> 8 A<5> 9 A<6> 10 A<7> 11 A<8> 12 A<9> 13 B<0>…

The net-lists match.

….It LVS’d!

LAYOUT – FP Multiplier@(#)$CDS: LVS version 5.0.0 06/02/2003 20:45 (intelibm5) $

Like matching is enabled.Using terminal names as correspondence points.

Net-list summary for /afs/ece.cmu.edu/usr/nmarwaha/cds/LVS/layout/netlist count

1068 nets37 terminals1232 pmos1232 nmos

Net-list summary for /afs/ece.cmu.edu/usr/nmarwaha/cds/LVS/schematic/netlist count

1130 nets39 terminals62 cds_thru1232 pmos1232 nmos

Terminal correspondence points 1 FP_1<0> 2 FP_1<10> 3 FP_1<11> 4 FP_1<1> 5 FP_1<2> 6 FP_1<3> 7 FP_1<4> 8 FP_1<5> 9 FP_1<6> 10 FP_1<7> 11 FP_1<8> 12 FP_1<9> 13 FP_2<0>…

The net-lists match.

…

It LVS’d!

FLOORPLAN – Last Week

TOP LEVEL LAYOUT - Current

SIZE ESTIMATES

Transistor Count: 33,654Area: 423x429 µm

(181,467 µm2)Density: ~0.185Aspect Ratio: ~1:1

VERIFICATION – Top Level

•Verified all of the functions for the ‘Swiss Army Knife’ in Schematic.

•Plotted outputs using custom made code & MatLab.

•From plots it is evident that the accuracy is excellent.

SIMULATIONS – FP Adder

ExtractedRC:

Rise Time / Fall Time: ~ 1.5ns

SIMULATIONS – FP Mult

ExtractedRC:

Rise Time / Fall Time: ~ 1.5ns / 500ps

PROBLEMS & QUESTIONS

Buffering – Need to Reduce Rise/Fall Times

Need to Reduce White SpaceImprove Density

Verified Design & Applications of Both Circuits (w/ & w/o Complex Numbers - Soft IP) w/ DSP TA