gct source card status 11.5.06 john jones imperial college london [email protected]
TRANSCRIPT
John Jones (IC - [email protected]), GCT ESR 210.5.06
Role of the Source Card
Capture data from RCT Relay data from RCT via optical links to GCT Leaf Card with minimal latency Provide test pattern transmission to Leaf Card for run-time debugging
RCT Crate
Source Card Crate
Leaf Card
RCT Crate
RCT Crate
Leaf Card
RCT Crate
RCT Crate
John Jones (IC - [email protected]), GCT ESR 310.5.06
Design Summary
6U VME Card USB 2.0 Interface 2xVHDCI SCSI RCT Inputs 4xSFP optical outputs TTC input QPLL, TTCrx Spartan-3 1M FPGA Digital/Analogue supplies Limited spare I/O for debug Front panel JTAG Limited remote update ability On-board LVDS test clock 6 spare clock outputs
John Jones (IC - [email protected]), GCT ESR 410.5.06
Source Card RCT Emulator Card
Developed to drive RCT inputs of source card
John Jones (IC - [email protected]), GCT ESR 510.5.06
Source Card Status
Components ordered (awaiting lead time estimate)
PCBs soon ready for manufacture (ahead of components)
Board should be available in 4-6 weeks (depends on component lead time)
Firmware test-benched & synthesised (see later)
Software under development (see J. Brooke’s talk)
John Jones (IC - [email protected]), GCT ESR 610.5.06
Registered
Initial mode of operation Easier, but higher latency – can be tuned and not as bad as one might think…
6+2+(14+)+2+(21.25<->23.75) = 45.25<->47.75ns
Source Card
Source Card Latency I
RCT VHDCI BUFFERDECL->TTL
SERDESLeaf~100ns
3m, ~15ns6ns
2ns
14+ns
2ns21.25-23.75ns
Extra register with phase-shifted clock
FPGA
John Jones (IC - [email protected]), GCT ESR 710.5.06
Unregistered
Tricky, not initial mode of operation as skew in FPGA difficult to control Phase of SERDES clock controlled via CLKDES on TTCrx
6+2+10+2+(21.25<->23.75) = 41.25<->43.75ns Doubtful whether this will be worth the effort…
Source Card
Source Card Latency II
RCT VHDCI BUFFERDECL->TTL
FPGA
SERDESLeaf~100ns
3m, ~15ns6ns
2ns
10ns
2ns21.25-23.75ns
John Jones (IC - [email protected]), GCT ESR 810.5.06
Source Card Firmware - Architecture
USBWishbone
Transcoder
Data MUX
LED Encoder
SERDES Clock
Local Clock
Transmitter FSM
Counter
LFSR
A-5
WishboneBridge
RCT Data
EMU/JET Switch
Bit Mask
Data Capture
SERDES
CRC-16
TransmitterControl
TTC I2C Temp. I2C
TTC Clock
TTC Interface
SystemInterface
RAM
John Jones (IC - [email protected]), GCT ESR 910.5.06
Source Card Firmware - Status
USBWishbone
Transcoder
Data MUX
LED Encoder
Simulated
Transmitter FSM
Counter
LFSR
A-5
WishboneBridge
RCT Data
Data Capture
SERDES
CRC-16
TransmitterControl
TTC I2C Temp. I2C
Real-World Tested
TTC Interface
SystemInterface
RAMBit Mask
EMU/JET Switch
John Jones (IC - [email protected]), GCT ESR 1010.5.06
Drive RCT inputs using Source Card Test Card via IDAQ Send via IDAQ USB, readout via Source Card USB Synchronising clock provided locally / via TTC Verify A-5, PRBS, counter
Source Card Testing Plan I
SCTC
Source Card
USB
USB
RCT IN
IDAQ
OPTO 1
OPTO 2
OPTO 4
OPTO 3
FPGA
TTC
CLKBUF
John Jones (IC - [email protected]), GCT ESR 1110.5.06
Demonstrate fake data capture at leaf Synchronise via TTC / local
Source Card Testing Plan II
Source Card
USB
RCT IN
OPTO 1
OPTO 2
OPTO 4
OPTO 3
FPGA
TTC
LEAF
SCTC
IDAQ
CLKBUF
John Jones (IC - [email protected]), GCT ESR 1210.5.06
Demonstrate RCT data capture in Source Card Synchronise via TTC
Source Card Testing Plan III
RCT
Source Card
USB
USB
RCT IN
FPGA
TTC
John Jones (IC - [email protected]), GCT ESR 1310.5.06
Demonstrate RCT data capture at Leaf Card Synchronise via TTC / local
Source Card Testing Plan IV
Source Card
USB
RCT IN
OPTO 1
OPTO 2
OPTO 4
OPTO 3
FPGA
TTC
LEAF
RCT
CLKBUF
John Jones (IC - [email protected]), GCT ESR 1410.5.06
Proposed Source Card Crate Layout
4 Source Card crates serve 18 RCT crates
John Jones (IC - [email protected]), GCT ESR 1510.5.06
USB 2.0 Hardware Interface
VMEbus SBCrunning Linux
3 front panelUSB port
10/100BaseTX Ethernet
InternalHard drive
PentiumProcessor
7-portUSB hub
7-portUSB hub
Source CardSource CardSource CardSource CardSource CardSource Card
Source CardSource CardSource CardSource CardSource CardSource Card
To monitor a 12-card crate
To monitor a 15-card crate
7-portUSB hub
7-portUSB hub
Source CardSource CardSource CardSource CardSource CardSource Card
John Jones (IC - [email protected]), GCT ESR 1610.5.06
USB 2.0 Hub Board
Artwork for hub mounting card has been completed and prototype is in production at Imperial
John Jones (IC - [email protected]), GCT ESR 1710.5.06
Summary
Submission of Source Card PCB slightly delayed… …but other associated components on track…
Plan to complete interfaces (software/PC) before PCB return in mid-late June