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FPGA REFERENCE CLOCK PHASE JITTER SPECIFICATIONS

1. Introduction

Driven by market demand for ever-increasing network bandwidth, high-speed digital communications equipmentmanufacturers look to communication semiconductor suppliers for the latest in high-speed standards-based digitalcommunications protocol building blocks. Several Field Programmable Gate Array (FPGA) vendors have taken upthis challenge and produced products specifically targeted to various segments of high-speed serial digitalcommunications designs. As a result, communications and embedded computing product designs are increasinglyutilizing FPGAs with embedded serializer-deserializers (SerDes) for critical high-speed transceiver and serialprotocol processing. Within high-speed serial digital communications, controlling, reducing, and maintaining lowsignal path jitter is a paramount concern, especially as bit rates increase into the multi-gigabit realm and beyond.FPGA vendors and system designers alike have become increasingly aware that low jitter digital communicationsabsolutely requires low or ultra-low jitter clocks. Silicon Labs timing solutions can easily meet the low jitter clockingrequirements for high-speed serial digital communications.

2. FPGA Clock Jitter Requirements

The vast majority of the FPGA market share is split between two companies, Xilinx and Altera. These twocompanies have FPGA products that specifically address various high-speed serial digital communications marketsegments. As a result of this market focus, these FPGA companies have published specifications for inputreference clock jitter requirements that allow their FPGA based products to implement spec-compliant serial digitalcommunications protocols. Although clock jitter can be specified in different forms, the almost universally acceptedformat for high-speed serial digital communications links is that of a phase noise (jitter) mask in the frequencydomain. (For an excellent technical explanation of jitter and phase noise, refer to Silicon Labs’ application note“AN687: A Primer on Jitter, Jitter Measurement and Phase-Locked Loops”.) Tables 1 and 2 provide the inputreference clock jitter specifications published by the two main FPGA vendors for FPGA products targeted for use inhigh-speed serial digital communications. In addittion to these jitter requirements,Table 1 and Table 2 also providethe jitter specifications for a selection of Silicon Labs’ timing devices. The selected devices include the Si51x 0.1–250 MHz programmable XO, Si53x/Si570 10–1417 MHz programmable XO, the Si5338 any frequency, any-outputclock generator, and the Si5326/68 any-frequency jitter attenuating clock. As shown in the following tables, thespecified Silicon Labs timing devices easily meet or exceed the FPGA’s input reference clock jitter requirementswith substantial margin and are well suited for use in high-speed digital serial communications applications.

Rev. 0.1 7/12 Copyright © 2012 by Silicon Laboratories AN699

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Table 1. Silicon Labs Phase Jitter Performance vs. Xilinx Phase Jitter Requirements

XilinxFamily

Ref Clock Freq(MHz)

Phase Noise (dBc/Hz) @ CalculatedPhase Jitterfrom Mask

Data(ps RMS)

Silicon Labs Jitter Performanceover same Jitter Mask Points

(ps RMS)

10 kHz 100 kHz 1 MHz 10 MHz Si51x Si5338 Si53xSi57x

Si5326Si5368

Spartan-6 GTP-LXT

100 –112 –130 –130 –135 2.22 1.1 0.38 0.23 0.11

Virtex-6 GTH-HXT

155.52 –120 –128 –139 –142 0.67 0.38 0.23 0.11

Virtex-6 GTX-CXT, HXT, LXT, SXT

100 –126 –128 –130 –135 1.92 0.38 0.23 0.11

7 Series GTXRing Osc

100 –126 –132 –136 N/S 0.52 0.38 0.23 0.11

7 Series GTXLC Osc

100 –126 –130 –134 N/S 0.63 0.38 0.23 0.11

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Table 2. Silicon Labs Phase Jitter Performance vs. Altera Phase Jitter Requirements

Altera Device Jitter Requirements Silicon Labs Performance

Device Transmitter RefClk

Parameter

RefClkFreq

(MHz)

Offset / Conditions

Max(For all Speed

Grades)

Units Si51x Si5338 Si53xSi57x

Si5326Si5368

Stratix VGX & GS

RMS Phase Jitter

(based on Altera jitter

mask*)

100 100 Hz–1 MHz

3.8 psRMS

2.1 1.0 0.3 1.1

REFCLK Phase Jitter

(rms)

10 kHz–20 MHz

3.0 ps 1.0 1.0 0.6 0.4

Stratix IVGT & GX

RMS Phase Jit-ter

(based on Altera jitter

mask*)

100 100 Hz–1 MHz

3.8 psRMS

2.1 1.0 0.3 1.1

REFCLK Phase Jitter

(rms)

10 kHz–20 MHz

3.0 ps 1.0 1.0 0.6 0.4

Arria II GX RMS Phase Jitter

(based on Altera jitter

mask*)

100 100 Hz –1 MHz

3.8 psRMS

2.1 1.0 0.3 1.1

REFCLK Phase Jitter

(rms)

10 kHz–20 MHz

3.0 ps 1.0 1.0 0.6 0.4

Cyclone IVGX

REFCLK Phase Noise

100 1–8 MHz –123 dBc/Hz

–138.9 –137.9 –145.6 –147.9

REFCLK Total Jitter (rms)

1–8 MHz 42.3 ps 11 36 14 5.4

Table 3. Altera Jitter Mask (100 MHz RefClk)

Frequency Offset Level Unit

100 kHz –80 dBc/Hz

1 kHz –110 dBc/Hz

10 kHz –120 dBc/Hz

100 kHz –120 dBc/Hz

> 1 MHz –130 dBc/Hz

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Altera has also recently released a software phase noise calculation tool to assist developers in assessing systemjitter/phase noise when using Stratix IV or Stratix V FPGAs. This tool is called “Altera Transceiver Reference ClockPhase Noise Jitter Calculator”. Figure 1 and Figure 2 show screen captures of this tool when data for the Si5338any frequency, any-output clock generator and the Si5326/68 any-frequency jitter attenuating clock are used. Notethe field “Contribution from Ref Clk” is virtually zero.

Figure 1. Si5326 Phase Noise Data in Altera Phase Noise Tool

Figure 2. Si5338 Phase Noise Data in Altera Phase Noise Tool

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3. Conclusion

Silicon Labs timing devices are well suited for use as reference clock sources for FPGAs with embedded SerDes inhigh-speed serial digital communications applications. With additional built-in features such as any frequencyflexibility with 0 ppm frequency error, superior PSRR, and jitter attenuation with digitally-programmable loopbandwidth, Silicon Labs timing products provide real system benefits over simple PLL clock solutions.

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DisclaimerSilicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.

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