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1

1

Abstract— This paper proposes a FPGA based software

defined radio (SDR) implemented flight termination system

(FTS). This is purely a new kind of implementation of digital FTS

in SDR platform. The applied design procedure replaces a

multiple platform based system with a single platform. It also

guarantees reconfigurable, interoperable, portable and handy

FTS and maintains errorless, bug free and reliable

implementation. Real-time flight termination operation demands

a very highly reliable and ruggedized platform. Hence, the FTS is

implemented in FPGA. In order to minimize hardware resources

and to enable future up-gradation, efficient optimization

technique has been applied. LabVIEW, a high level

programming language is used to simulate and implement the

system in real-time and enables rapid prototyping. The system

was validated at sub systems level by measurements of different

parameters in various intermediate stages of processing and

further was validated as an integrated system at real-time

telecommunication operation environment.

Index Terms— Field-programmable gate array (FPGA), flight

termination system (FTS), real-time system, software defined

radio (SDR).

I. INTRODUCTION

newly developed, Flight Vehicle (FV) needs rigorous

testing to satisfy all expected performance. When testing

the FV dynamically, there are lots of uncertainties regarding

the flight performance. Hence at test facility, a flight

termination system (FTS) is utilized to secure the property and

human life. FTS basically involves in generation and

transmission of remote command signals to the airborne flight

vehicle to execute some operation inside the vehicle as

required.

FTS is used for termination of high speed FV under test.

Termination of test vehicle is mandatory if the high speed

1Manuscript received May 29, 2014; revised August 29, 2014; accepted

October 08, 2014. Date of publication . This work was

supported by Defence Research and Development Organization, Government

of India.

A. R. Panda is with the Department of Computer Data Processing,

Integrated Test Range, Defence Research and Development Organization,

India (e-mail: amiya87@gmail.com ).

D. Mishra is with the Department of Computer Science and Engineering,

Siksha ‘O’ Anusandhan University, Odisha, India (e-mail: debahutimishra

@soauniversity.ac.in).

H. K. Ratha is with Integrated Test Range, Defence Research and

Development Organization, India (e-mail: hk.ratha@itr.drdo.in).

Copyright (c) 2014 IEEE. Personal use of this material is permitted.

However, permission to use this material for any other purposes must be

obtained from the IEEE by sending a request to pubs-permissions@ieee.org.

vehicle deviates from its preset trajectory and takes different

course due to unpredictable failures of onboard system. In

such cases specific commands are transmitted from command

transmission system (CTS) for termination of test vehicle via

remote control unit (RCU). The commands are transmitted

when required during test. Real-time flight termination

operation demands a very highly reliable and ruggedized

platform. The commands transmitted by CTS is received and

decoded by onboard command reception system (CRS) at FV

and the commanded operation is done accordingly.

The design of FTS involves real-time signal generation,

transmission and analysis of the transmitted signal. The

system also has to ensure real-time communication with RCU

with various demanded protocols. The system versatility with

respect to different modulation schemes must be ensured for

future up-gradation.

A suitable software defined radio (SDR) platform has

proven itself to be very efficient platform for implementing

such versatile and reconfigurable system architecture [1], [2],

[3]. SDR in recent trend is a common term, which has been

used for rapid prototyping of different types of complex

communication system used in different fields, such as for

radar design [4], GPS receiver design [5], adaptive optics

system design [6], drive servo system design [7] etc. Many

real-time applications such as advanced control system design

[8], system performance measurement [9], data acquisition

[10] and processing [11] use the FPGA integrated with PXI

platform for implementation.

High robustness and high reliable flight termination

operations are strongly desired. High degree of versatility and

reconfigurable architecture with real-time response is

achievable through the combination of highly reliable software

with wide range of capabilities and suitable hardware platform

i.e. FPGA. It is necessary to have system which is flexible,

reconfigurable and dynamic to the environmental situations

and hardware modifications. SDR based on FPGA system

could be a good option for designing intelligent and

reconfigurable CTS for operations on a single platform [12],

[13], as compared to the previously used bulky CTS, which

was a discrete component based fixed configuration system.

Different hardware based CTS systems were used for test of

different flight vehicles. The newly developed SDR based FTS

system in turn, solves the problem of frequent hardware

replacements and cost of design as in SDR based system, only

software updation is required to implement new system.

The FPGAs are broadly used now-a-days for many

FPGA Implementation of Software Defined

Radio Based Flight Termination System

Amiya Ranjan Panda, Student Member, IEEE, Debahuti Mishra, and Hare Krishna Ratha, Member, IEEE

A

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Fig. 1. The block diagram of the FTS transmitting signal to flight vehicle

applications [14], [15]. Because of efficient computational

power, parallel data processing, low power consumption and

optimized area, FPGAs are presently taking over legacy

processor based applications. Current development in FPGA

technologies include as many as dedicated digital signal

processor (DSP) cores to fit several order complex algorithms

to be implemented. Further it is necessary to optimize the

design algorithms for optimal resource utilization.

The FTS algorithm has been implemented in FPGA, which

is optimized for DSP and memory intensive applications with

low power serial connectivity [16]. LabVIEW FPGA module

of NI Flex-RIO system has been used to simulate and design

the various modules of the system. LabVIEW FPGA module

enables to simulate various modules of the system in faster

way [17] and the advantage is that the same simulation applies

in real hardware implementation. Hence, rapid prototyping is

achieved using LabVIEW software. The design has been

implemented using fixed point data type, so as to optimize the

resource utilization within the FPGA [14], [15].

The CTS system consists of a real-time controller (RTC),

host computer and SDR based command transmission and

reception unit (Fig. 1.). The RTC offers a communication

interface between RCU and host computer with CTS system.

RCU is used for remote operation of the CTS. Host computer

is used for configuration, local mode operation and analysis of

intermediate signal processing of the CTS system.

The structure of this paper is as follows. Section II describes

the mathematical formulation of the problem. It continues with

the SDR based design approach presentation and the Flex-RIO

software communication architecture for FTS operation.

Section III describes the FPGA Implementation of SDR based

FTS. Section IV shows the laboratory set up and experimental

results. Finally, section V concludes the paper.

II. SDR BASED FTS ALGORITHM

A. Mathematical Formulation

The concept of FTS is depicted in Fig. 1. The RCU is

connected with the CTS through reliable serial communication

links. The commands are given from the RCU to CTS. The

commands are generated and transmitted from the CTS,

received by onboard CRS through RF link and required

operation is done accordingly.

The generated commands are a frame of binary bits. This

frame comprises of number of binary data bits, which is

headed by number of binary header bits and trailed by

number of stop bits. So the length of the frame is . The whole frame is encoded with Manchester

encoding scheme and total number of bits in a frame becomes

double i.e. .

The frame is converted to binary data wave form with

the logic = +1 or -1 corresponding to the binary bits 1or

0. Hence, the binary data waveform can be expressed as:

Here is the th number of bit of the frame. The bit takes on value 1 and -1 for binary bit 1 and 0 respectively.

is a rectangular pulse which can be represented as

. Here, is bit duration.

This binary data waveform modulates a carrier signal

using binary frequency shift keying (BFSK) modulation

scheme. In this scheme sinusoidal signal with higher

frequency ( ) and lower frequency ( ) are generated for bit

1 and 0 respectively. Thus, the BFSK modulated signal can be

represented as (2):

(2)

Here is a constant offset from the carrier frequency ( ).

Equation (2) can be written as (3):

(3)

Here for bit 1, and its corresponding higher

frequency ( ) and for bit 0, and its

corresponding lower frequency ( ).

This BFSK modulation is done in very low frequency i.e. in

very low frequency band. This signal is finally up-converted

to ultra high frequency band using FM modulation scheme.

The basic principle behind FM is to vary the carrier frequency

in proportion to the modulating signal . This means

instantaneous frequency ( ) of the carrier is changing in

proportion to . This can be written as,

Here, is career frequency, is a constant and is

RF Link

Receiving

Antenna

Transmitting

Antenna

Command Transmission System (CTS)

Ethernet

Link

Serial Link Remote

Control

Unit

Onboard command

reception system in

flight vehicle

Serial Link Comm.

Network Real-Time

Controller

Transmitter

Receiver Host

Computer

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a generalized angle. Equation (4) can be written as,

Equation (5) follows to,

So the corresponding FM signal can be written as,

Here, is amplitude of the career signal and modulating

signal is BFSK modulated signal .

In the receiving side, FM signal can be demodulated

by applying the signal to the differentiator. The output of the

differentiator is,

Equation (8) follows to,

This signal is both amplitude and frequency modulated. If

for all , can be recovered by

envelope detection of . Next step is to demodulate the BFSK signal for recovering

the command frame. The BFSK signal is demodulated by a

square law detection method [18].

B. SDR based design approach

For a conventional discrete component based design, it is

not possible to vary the functionality of the system beyond

certain range of specification. But a SDR based on FPGA

enhances the capability of the platform so as to design a

system with re-configurability and flexibility. The main

philosophy behind SDR is that it can flexibly alter the radio

waveforms by changing software and without changing the

SDR platform. As in SDR, large part of the waveforms are

defined in software, it allows us to flexibly change the

waveforms within certain bounds by implementing the

appropriate software modules [2], [3].

SDR can be implemented in different platforms [19]-[23]. A

SDR based FTS including its main elements implemented in

FPGA is depicted in Fig.2 (b). The heart of the system is real-

time operating system. The waveforms and their portability

which includes the middleware are realized through basic

functions and libraries provided by the software framework.

The combination of software communication architecture [24],

[25] and CORBA [26] forms the software framework.

C. LabVIEW FLEXRIO software communication architecture

In LabVIEW Flex-RIO Software Communication

Architecture [3], a host VI runs on a Windows PC, a real time

VI runs on RTC and FPGA get programmed through a bit file

generated according to the FPGA VI.

The architecture supports quick development of various

complex systems [27], [28]. Here program loops which are to

be executed concurrently and are highly time critical (in-line

signal processing, custom timing synchronization and digital

communication) are implemented on the FPGA. Due to

simultaneous running of the program loops, a very high loop

rate can be achieved. Floating point operations which are less

time critical can be run on the LabVIEW real-time module.

FPGAs support operations in parallel mode, compared to

common processors [29], which compute in sequential mode.

FPGA thus help us to achieve very time critical task [30].

Their only limitation is in the availability of space which is

related to the number of gates supported per FPGA.

III. FPGA IMPLEMENTATION OF SDR BASED FTS

A. Realization of signal generation in LabVIEW FPGA

In the presented application the SDR based

telecommunication operation is realized in FPGA, using high

level programming language (LabVIEW). The command

codes generation and encoding are done easily.

The essential problem during the implementation of SDR

based telecommunication operation is realization of signal

generation for modulation, digital up conversion (DUC),

digital down conversion (DDC), demodulation, signal filtering

etc. For this purpose, the signal is generated in LabVIEW

FPGA using a technique called direct digital synthesis (DDS)

[31].

In DDS, a time varying signal is generated in digital form

and then Digital to Analog Conversion is performed to obtain

an analog waveform usually a sine wave.

In LabVIEW 2013, the Xilinx DDS Compiler Logi CORE

4.0 IP provides direct digital synthesizer. In this project, 16

bits output sample precision is used. DDS Compiler core IP

can generate frequencies from less than 1 Hz up to 40 MHz

(based on a 100-MHz clock) [31].

B. LabVIEW code realization for FPGA

Optimization exists in the coding of FPGA and timing in

various ways. In this project, the fixed point notation is used,

which helps in achieving hardware resources utilization [15],

[16].

The Single Cycle Timed Loop is a special use of the

LabVIEW timed loop structure enabling optimization of

program. This loop executes all functions inside it within

one tick of the FPGA clock in FPGA target. It can be used

with derived clocks to operate the loop at a different rate and

can be used with faster global clock (80 MHz or above). Use

of shift register and feedback nodes in it enables us to

implement parallel execution of logic and passing of data

between subsequent iterations. The appropriate use of state

machine for implementing different parts of the application in

it provides speed and efficiency of the application.

The efficiency of the algorithm can be enhanced through

appropriate use of pipelining technique. In this scheme, the

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algorithm is broken into smaller parts and those parts which

can be executed independently are identified. Next, they are

executed in parallel manner. The length of code executed in

each iteration is reduced and the total time for implementing

the whole application becomes less [36], [37].

During this implementation two very important factors considered are balancing of pipeline stages and minimization

of memory transfer.

a)

b)

c)

d)

e)

Fig. 2. The block diagram of the proposed algorithm for the FPGA

implementation of flight termination system (a) Broad software

implementation scheme of FTS, (b) Details software communication scheme

of FTS, (c) Data flow diagram of transmission module implemented in FPGA,

(d) Data flow diagram of reception module implemented in FPGA, (e) Data

transfer methods used for transferring data in FPGA, RT and host VI.

Effective compilation of the program in the target

application may not be certain by applying these methods

while realizing the SDR based FTS. For surmounting this

problem a special program as depicted in Fig. 2, has been

developed.

The algorithm comprises of two parts: the main program

and the sub programs [Fig. 2(a)]. The SDR based command

transmission chain and command reception chain (CTS) are

realized in the main part of the program. The encoding

(Manchester Encoding), decoding, modulation (FM modulation followed by BFSK modulation), de-modulation

(Non coherent BFSK demodulation followed by FM

demodulation), DUC and DDC are implemented in two

FPGAs and are executed from the main program through bit

file of respective program. Modulation, de-modulation, DUC

and DDC are implemented as sub programs in FPGA VI,

which allow the program to optimally use the logic elements.

During the data processing in each chain (Transmission

chain and receiving chain), the main program transfers control

to sub-programs, where output values are calculated

simultaneously by the Sub VIs.

It should be noted that the application startup time of the

system is very fast as the application is deployed in RTC. The

change of any parameter setting can be done at real-time,

which is very easy and fast as the data transfer between RTC

and host occurs through TCP/IP and between RT and FPGA

through FIFO and memory element.

Block diagram of broad software implementation of FTS is presented in Fig. 2(a). Other parts of the FTS, implemented in

RT and FPGA are shown in Fig. 2(b) and the detailed FPGA

implemented parts are shown in Fig. 2(c) and Fig. 2(d)

respectively. Fig. 2 (e) shows the data transfer methods used

for transferring data within important modules of FPGA VI,

RT VI and Host VI. However, within the modules (among the

loops), data transfer occurs through FIFO and memory

elements.

Input

Output

Main

Program

SubProgram run as Bitfile

Baseband and IF level

processing of Transmitted Signal

SubProgram run as Bitfile

Baseband and IF level

processing of

Received Signal

Antenna

Input

Output

Antenna

RCU

and

Host Reception

Unit

Transmission

Unit

FPGA

Reception

Module

Command Code Reception

Decoding

Digital Demodulation

Analog Demodulation

Digital Down Conversion

Software Framework

FPGA

Transmission

Loops

Reception Loops

RTC

Transmission

Loop

Reception

Loop

Waveforms

RF Up Conversion

RF Down Conversion

Digital to

Analog

Conversion

Analog to

Digital Conversion

Pre Amplification

Antenna

Antenna

Power Amplification

Applications

FPGA

Transmission Module

Command Code

Generation

Encoding

Digital Modulation

Analog Modulation

Digital Up Conversion

Network

Published

Shared

variable

and I/O variable

Network

Stream

(TCP/IP)

Host

VI

UI Event Handler

Parameters

setting and

Command

sender

UI Update

Queue Read/

Write

Control

DMA

FIFO

Read/

Write

Control

FPGA VI

Transmission

Loops

Receiver Loops

Intermediate

Trans. and

Receive signal acquisition

Real-Time

VI Commands and

parameters Parser

RT Transmission Loop

Shared Variables

RT Receiver

Loop

DAQ and

analysis

(Time critical)

Store parameters in file

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Fig. 3. FPGA based FTS connected with Host computer and Remote Control Unit

C. Hardware Realization of SDR based FTS

The program for the Flex-RIO RTC, realized for performing

the command transmission and command reception operation

has two levels comprising the one portion related with the

FPGA and other portion related with the RTC. The RCU is

connected to the RTC through serial communication link, used

to send trigger for command generation and transmission. The

host portion of the controller takes the responsibility for

providing the transmission and reception analyzed signal and

setting the parameters for the total system. Direct Memory

Access enables synchronization of both of the controller parts,

and at the same time safeguards the efficiency and speed of data transfer. Optimization of data transmission is obtained by

this technique, which takes place between Flex-RIO

components and at the same time between the code parts

through the RAM memory and the First-In-First-Out (FIFO)

queues.

In this scheme, the transmitted commands from the RCU

are stored in the ROM memory of the Flex-RIO Controller

and to be conveyed to the SDR based CTS implemented in

FPGA. For making the transmission and reception of

commands reconfigurable, the programs are implemented in

FPGAs. In transmission chain, DUC is implemented in the

FPGA programmatically using interpolation filter, DDS and

mixer [33]. The digital mixer and DDS translate baseband

samples up to the IF frequency. The mixer generates one

output sample for each of its two input samples. To improve

the sampling frequency of baseband signal interpolation is

used. The primary reason to interpolate is simply to increase

the sampling rate at the output of one system, so that another

system operating at a higher sampling rate can operate the

signal. In reception chain, DDC is implemented in the FPGA

programmatically using DDS and low pass filter [33]. The

digital mixer and DDS translate the digital IF samples down to

baseband. The FIR low pass filter limits the signal bandwidth

and acts as a decimating low pass filter (Fig. 3).

For parallel implementation of DUC and DDC in FPGAs,

according to the presented algorithm realized in the NI

LabVIEW FPGA module, reentrant and non-reentrant

executions of the graphical code parts were used. Through this

tool, the developed algorithm can use all the features of the

FPGA; so suitable selection of the execution sequence for

some portions of the algorithm is possible.

The solution presented here is adequate for implementation

of the SDR based CTS, but more complicated task arises when

the system is used for real-time flight termination operation.

The commands are to be given from RCU, placed at remote

locations. In such cases, the RCU is connected to the real-time

controller via reliable serial communication link and one

additional loop is necessary for implementation. So in the

described solution, total four routines are working in the same

time: first one for host support, second one for RCU support,

third one for FPGA implemented SDR based CTS, fourth one

for FPGA implemented SDR based CRS. These four

subroutines have different time for calculation. Correct

operation of the FTS is guaranteed through disciplined data

transfer between them. LabVIEW supports few tools for

synchronization and the most important areas covered are

occurrences, interrupts and loops executed in sequential

manner. With the help of these tools, we can inhibit some part

of the code while realizing the other parts. In addition, it

facilitates enabling an order of the data transfer while

executing loops.

An algorithm capable of measuring the transmitted signal

and next received signal from the air is very much required to

carry out the test. The transmitted signal is received from air

through receiving antenna and fed to pre amplifier. Then the

signal is down converted and processed through FPGA

received chain (Fig. 3.). Several commands are sent to the transmission line of CTS

from RCU through RTC for transmission, and further, the

commands are received through reception line of CTS. The

maximum usable clock frequency of the FPGA is 100MHz.

However the baseband level implementation is done at

10MHz clock and IF level processing is done at 80MHz and

PXIe

Receiving

Antenna

TCP/IP Communication

Host

Computer

Serial Communication

Serial

Communication Comm. Network Remote

Control Unit

FPGA DUC

Command

Code

Generator Interpolation

Filter Digital

Mixer

DDS

FPGA

DDC

Low Pass Filter

Digital

Mixer

DDS

Command

Code

Interpreter

Real-Time

Controller

(RTC)

ADC RF Down

Converter

Pre

Amplifier

Transmitting Antenna

DAC RF Up

Converter

Power

Amplifier

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100 MHz clock. Whole application needs 86.4% of SLICEs

from hardware resources. Complete resource utilization is

summarized in Table I. TABLE I

HARDWARE RESOURCES UTILIZATION IN FTS APPLICATION

Device Utilization Used Total Percentage

Usage

Total Slices 12715 14720 86.4

Slice Registers 25777 58880 43.8

Slice LUTs 38167 58880 64.8

DSP48s 391 640 61.6

Block RAMs 60 244 24.6

IV. EXPERIMENTAL SETUP

A. Laboratory Setup

The SDR based FTS includes FPGA, RTOS and GPUs. The

communication algorithms, DDC and DUC are implemented

in FPGAs [32]. The analog to digital conversion, digital to

analog conversion, RF up conversion and RF down

conversions are implemented in high speed PXIe cards. The

remote command interface is implemented in GPU connected

to RTOS via reliable communication links. The SDR based

FTS algorithms were implemented using high level

programming language (LabVIEW) and were realized by NI

PXI-7966R with Xilinx Virtex 5, SXT, FPGA [34], [35]. The experiment was done in 2 phases. Offline: The onboard

receiver with decoder (nominal power of 12V DC) is kept in

laboratory (Fig. 4). Online: The onboard receiver with decoder

is kept inside helicopter and received the status through

ground telemetry stations (Fig. 5).

Fig. 4. The block diagram of Laboratory setup

Fig. 5. The block diagram of online test setup

The laboratory setup (Fig. 6) is composed of one onboard

receiver and decoder with receiving antenna. Initially different

command codes and frequency of operation are set in the on

board receiver. Then, the commands are transmitted from FTS

with the same command codes and frequency set in onboard

receiver. The delay between transmission and reception of

command codes are observed and analyzed by taking feedback

from the onboard decoder to the host computer.

Fig. 6. Laboratory setup

In online experimental setup, the onboard receiver with decoder is kept inside helicopter and received the status

through ground telemetry stations and the same is fed to the

host computer for analysis. In offline experimental setup, the

onboard receiver with decoder is kept in laboratory and the

received signal status information is fed to host computer

through ethernet link for analysis.

B. Experimental results

In both of the testing procedure, the commands are

transmitted at different frequency band such as HF, VHF and

UHF and the signal characteristics were analyzed. The system

parameters setting were depicted in Table II.

TABLE II

SDR BASED FTS PARAMETERS SETTING

Parameters Operation

Range Unit

Baseband Data rate 2-8 Kbps

BFSK Mark Frequency 0-50 kHz

BFSK Space Frequency 0-50 kHz

FM Deviation 100-200 kHz

IF Center Frequency 15-35 MHz

RF Up Conversion Center Frequency 25-2750 MHz

RF Down Conversion Center Frequency 25-2750 MHz

The overall performance of the system which includes

transmission, reception and medium has been validated using

bit error rate (BER) performance. The radio communication

systems and the radio links are generally identified with

parameters like signal to noise ratio and Eb/N0, which signifies

the capability of the facilities. BER is generally defined in

terms of Probability of Error (POE). The POE function for non

coherent BFSK is represented by equation 10.

The BER performance [38] of the transmitted signal is

analyzed and observed to be similar with the theoretical BER

Host

Computer

Flex-RIO system

(RTC, FPGA,

PXIe cards) Onboard

receiver

Power Amplifier 1

Onboard

parameter

display

Power Amplifier 2

Spectrum Analyzer

Antenna Antenna

Remote

Control

Unit

Host

Computer

Flex-RIO

System

(RTC, FPGA, PXIe cards)

Spectrum

Analyzer

Power

Amplifier (1+ 1)

Antenna

Antenna

Onboard

Parameters

display and

logging Unit

Onboard

Receiver and

decoder

Remote Control

Unit

FTS Comm.

N/w

Helicopter containing onboard

CRS

Telemetry

Stations

Data Logging and

Analysis Unit

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0 2 4 6 8 10 1210

-4

10-3

10-2

10-1

Eb/No (dB)

Bit

Err

or R

ate

theory:fsk-non coh

sim:fsk-non coh

0 400M 800M 1.2G 1.6G 2.0G 2.4G 2.8G20

22

24

26

28

30

32

34

36

38

40

Frequency (Hz)

Ga

in (

dB

)

Typical Gain, CH 0

Minimum Gain, CH 0

0 400M 800M 1.2G 1.6G 2.0G 2.4G 2.8G

2

4

6

8

10

Frequency(Hz)

No

ise F

igu

re(d

B)

Typical NF, CH 0

Maximum NF, CH 0

(a) (b) (c)

Fig. 7. (a) Plot between BER and Eb/N0 (theoretical vs. observed). Linearity measurement w.r.t (b) Gain and (c) Noise Figure.

(a) (b) (c)

Fig. 8. IF spectrum observed in spectrum analyzer at (a) 25 MHz at transmitter side, (b) 15 MHz at re ceiver side and (c) transmitted and received IF frequency

observed in oscilloscope simultaneously.

(a) (b) (c)

Fig. 9. RF Spectrum observed in spectrum analyzer at (a) 1.5 GHz , (b) 1 GHz and (c) 300MHz

performance of non coherent BFSK modulated signal, which

is shown in Fig. 7 (a).

At receiver chain, the RF signal conditioning is done by NI

PXI 5690 module which includes low noise / high gain

amplifier and programmable attenuators. It is a 100 kHz to 3

GHz, two-channel programmable amplifier and attenuator

with one fixed gain path and one programmable

gain/attenuation path. In this project, the fixed gain path is

used with a typical gain of 30 dB across all frequencies. The

channel offers a low noise figure and flat frequency response

as shown in Fig. 7(b). The linearity of gain with frequency is

shown in Fig. 7(c).

For proper validation of the performance of the FTS,

intermediate signal for each transmission data and reception

data are captured and analyzed. After verification of baseband

signal through a baseband decoder then only further

modulation and up conversion operation are carried out. The

time synchronization criticality has verified by capturing the

encoded data waveform and measuring the widths of the

pulses. The stability of the frequency generated by the DDS

algorithm through the hardware is measured and expected

results were obtained. The FM modulation and demodulation

are implemented using intermediate frequencies at 25 MHz

and 15 MHz respectively (Fig. 8 (a), (b)). Fig. 8 (c) shows

frequency spectrum for transmit IF and receive IF. Fig. 10

shows the measurement of the time duration of one cycle

duration when modulation was switched off. Time duration of

40 ns corresponds to 25 MHz IF signal.

Fig. 10. Measurement of time duration of one cycle at 25 MHz in

oscilloscope

For practical transmission purpose, transmit IF signal is up-

converted at different frequencies and transmitted in the air

(Fig. 9. shows spectrum at 1.5 GHz, 1GHz and 500MHz).

Various tests have been carried out to test and validate the

FTS. For a reliable operation of high power amplifier, the

1551-3203 (c) 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. Seehttp://www.ieee.org/publications_standards/publications/rights/index.html for more information.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI10.1109/TII.2014.2364557, IEEE Transactions on Industrial Informatics

8

200M 300M 400M 500M 600M 700M 800M-4

-2

0

2

4

Frequency (MHz)

Pow

er (

dB

m)

0 200M 400M 600M 800M 1,000M0

200

400

600

800

1,000

Input Frequency (MHz)

Ob

serv

ed

Freq

uen

cy

(M

Hz)

(a) (b)

Fig.11. Linearity measurement w.r.t (a) Power (Plot between input frequency and observed power), (b) frequency (Plot between input frequency and output

frequency)

(a) (b)

Fig. 12. (a) Frequency spectrum at 300 MHz showing zero harmonics at 600MHz and 900 MHz, (b) Measurement of band width for 99% channel power

output power linearity is very crucial for the transmitter over

the interest frequency of operation. It has been experienced

that the output power and frequency are very much linear in

the specified frequency range (Fig. 11. (a), (b)).

For a good transmitter design, designer must consider that

the harmonics must be eliminated, so that it shall not hamper

other communication system. When power amplified and

transmitted in air, by using a proper filter at the IF level,

harmonics are eliminated (Fig. 12.(a)). For faithfully

transmission purpose, the channel power also has been

measured and 99% channel power resides in 262 KHz of band

width (Fig. 12. (b)).

V. CONCLUSION

In this paper a SDR based FTS; a transceiver system

implementation is presented. The system has been

implemented using NI-Flex RIO configuration. Xilinx FPGA

integrated into the Flex RIO module has given a very highly

flexible platform for complex algorithms for FTS system

designing. The system has been designed using LabVIEW

FPGA module software and deployed through LabVIEW RT

running in to the controller chassis. The RT LabVIEW

provides a very reliable and fast communication between the

remote control unit and FTS transceiver system.

Suitable algorithms for signal generation, encoding,

baseband and pass band modulation, digital up conversion and

down conversion, filter design have been chosen and

implemented to ensure optimized uses of hardware.

The performance of the system is analyzed through study of

the intermediate signal processing. Analysis is done at both IF

and RF stages of transceiver and the system is validated by

linearity response at different frequencies and BER

measurement.

In future CDMA based FTS system can be implemented

using developed SDR based framework for control of multiple

flight object simultaneously.

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Amiya Ranjan Panda (S’14) was born in Odisha,

India on July 15, 1987. He received the B.Tech

degree in Information Technology from Biju Patnaik

University of Technology, Odisha, India in 2009 and

M.Tech degree in Computer Science and

Engineering from Kalinga Institute of Industrial

Technology, Deemed University, Odisha, India in

2012.

He is currently working as Senior Research Fellow

at Integrated Test Range, Defence Research and

Development Organization (DRDO), India and

worked as Junior Research Fellow from 2010 to 2012 in DRDO, India. He is

currently pursuing his Ph.D. degree in Siksha ‘O’ Anusandhan University,

Odisha, India. His research is mainly in real time data acquisition,

communication, software defined radio and flight termination system. His

research interests are supervisory control and data acquisition, machine

learning and soft computing.

Debahuti Mishra received the B.Tech degree in

Computer Science and Engineering from Utkal

University, Odisha, India in 1994 and M.Tech

degree from Kalinga Institute of Industrial

Technology Deemed University, Odisha, India in

2006. She did her Ph.D. in Computer Science and

Engineering from Siksha ‘O’ Anusandhan

University, Odisha, India in the year 2011.

She is an Associate Professor in the Department of

Computer Science and Engineering, Institute of

Technical Education & Research (ITER) under Siksha ‘O’ Anusandhan

University, Odisha, India. Her research areas include data mining,

bioinformatics, data acquisition, software engineering, soft computing and

machine learning. She has contributed three books and more than 65 research

level papers to many national and international journals and conferences.

Hare Krishna Ratha (M’14) received the B.Tech.

degree in Electronics & Telecommunication

Engineering and the M.Tech. degree in

Telecommunications System Engineering from

Sambalpur University, India and IIT Kharagpur,

India in 1988 and 1996 respectively.

He had been working as Scientist in Defence

Research & Development Organisation, India for the

last 25 years in various capacities. Currently he is

working as Additional Director at Integrated Test

Range, Defence Research & Development Organisation, India. His research

interests broadly include various range technologies like real time data

acquisition, communication, computing, and flight termination system.