FLOOR PLANNING

BY AMIT KR. CHAMOLI

Outlines Introduction Efficacy Merits Input/Output Floorplanning Problem Challenges Floorplanning Representations and Approaches Floorplanning Model Algorithms Assignment Conclusion

Introduction Floorplanning is an essential element of

hierarchical design flows, especially for large SoC(System On Chip) designs. A typical SoC could include hundreds of RAMs, soft and hard IP(Intellectual property), analog blocks, and multiple power domains.

A hierarchical methodology that extends the capacity of design-automation tools, improves tool runtimes, and mitigates overall design risk by minimizing last minute design changes

Floorplanning

block placement Pin assignment Design partitioning Time budgeting Power and clock planning

Efficacy Floorplanning is considered when the

Design has not met timing or does not meet timing consistently

Critical logic to Improve performance Reduce routing congestion Improve module-level performance

and Area Improve Implementation Run time

and consistency with partitions

Merits

Eliminate Guess work Minimize the impact of surprises in

chip assembly Reduce the risks associated with

Hierarchical Flows and Shorten the time to design closure Timing Congestion

More Flexibility in Design layout

Floorplanning phase Input A set of blocks with constraints on area,

shapes, relative positions, Constraints on chip area and aspect ratio, Netlist.

Output Shapes, Locations, Pin positions of the

blocks Objective Functions Performance, chip area, and wire length

Floorplanning Problem

The floorplanning problem is to plan the positions and shapes of the modules at the beginning of the design cycle to optimize the circuit performance: chip area total wirelength delay of critical path routability others, e.g., noise, heat dissipation, etc.

Floorplanning Challenges

Bad Input/output Pad and Macro placement

Inaccurate Timing ,Area and Power estimation

Inadequate Region shaping , Partitioning and Pin Assignment

Floorplanning strategies

Floorplanning must take into account blocks of varying function, size, shape.

Must design: space allocation signal routing power supply routing clock distribution

Purposes of Floorplanning

Early in design: Prepare a floorplan to budget area, wire

area/delay.Tradeoffs between blocks can be negotiated.

Late in design: Make sure the pieces fit together as

planned. Implement the global layout.

Floorplanning: Why Important?

Early stage of physical design Determines the location of large blocks

detailed placement easier (divide and conquer!)

Estimates of area, delay, power important design decisions

Impact on subsequent design steps (e.g., routing, heat dissipation analysis and optimization)

Floorplanning tips• Develop a wiring plan. Think about how

layers will be used to distribute important wires.

• Sweep small components into larger blocks. A floorplan with a single NAND gate in the middle will be hard to work with.

• Design wiring that looks simple. If it looks complicated, it is complicated.

• Draw separate wiring plans for power and clocking. These are important design tasks which should be tackled early.

Representations and Approaches

Two popular approaches to floorplan1. Simulated annealing2. Analytical formulation

Floorplan representations1. Normalized Polish expression2. B*-tree3. Sequence Pair4. Polar Graph

Floorplanning Model

1. Slicing floorplans2. Non-slicing floorplans Slicing Tree

A binary tree that models a slicing structure.

Each node represents a vertical cut line (V), or a horizontal cut line (H).

A third kind of node called Wheel (W) appears for non sliceable floorplans

Floorplanning Model (Cont)

A Non-Slicing FloorplanSlicing Floorplan and its Slicing Tree

Floorplanning Algorithms Components

“Placeholder” representation Usually in the form of a tree Slicing class: Polish expression Non-slicing class: O-tree, Sequence Pair, etc. Just defines the relative position of modules

Perturbation Going from one floorplan to another Usually done using Simulated Annealing

Floorplan sizing Choose the best shape for each module to minimize area Slicing: polynomial, bottom-up algorithm Non-slicing: Use mathematical programming (exact solution)

Cost function Area, wire-length, ...

Classification of Algorithms Simulated Annealing Constraint Based methods (Integer) Linear Programming

Methods Rectangular Dualization Based

Methods Hierarchical Tree Based Methods Timing Driven Floorplanning

Algorithms

Simulated Annealing In this process, a material is first heated up

to a temperature that allow all its molecules to move freely around and is then cooled down very slowly.

Perform computation that analogous to physical process. The energy corresponds to the cost function Molecular movement corresponds to a sequence

of moves in the set of feasible solution Temperature corresponds to a control parameter

T which control the acceptance probability for a move i.e. A good move

Wong-Liu Floorplanning Algorithm

Uses simulated annealing Normalized Polish expressions represent

floorplans Cost function:

cost = area + total WireLength Floorplan sizing is used to determine area After floorplan sizing, the exact location of each

module is known, hence wire-length can be calculated

Wong-Liu Floorplanning Algorithm (cont.)

Moves: OP1: Exchange two operands that have

no other operands in between OP2: Complement a series of operators

between two operands OP3: Exchange adjacent operand and operator if the

resulting expression still a normalized Polish exp.

OP1OP1OP1OP1 OP1OP1OP1OP1 OP1OP1OP1OP1

12 | 4 – 3 | 12 | 3 – 4 | 12 - 3 – 4 | 12 - 3 4 - |

Assignment

What are timing failure? What are the critical hierarchical

Block and Risk? Are changes/moves to the Floorplan

or critical logic going to be sufficient to meet timing?

Does anything else need to be Floorplaned?

Conclusion Floorplanning is the foundation of a quality

IC implementation. The decisions made regarding IO pad placement, macro placement, partitioning, pin assignment, and power planning ripple through the place-and-route flow. Designers need solutions that can handle extremely large data sets, design variability and complexity, in addition to enabling fast, high-quality floorplanning.

Q & A

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