floor planning lab

8/3/2019 Floor Planning Lab

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IO and Block Floor PlanningLab Exercises

I/O and Block Floor Planning Lab Exercises

April 24, 2006 Page 1IBM EDA Education - Do Not Copy


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Table Of Contents

Page 91Compiling our own Abstract Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 90Custom Compiling an Abstract Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 89Loading DSL and IOSpecLIst in Native ChipBench . . . . . . . . . . . . . . . . . . . . .Page 88Loading DSL and IOSpeclistin Native ChipBench . . . . . . . . . . . . . . . . . . . . . . .Page 82Data Specification for ChipBench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 81Loading without a Net Listin Native ChipBench . . . . . . . . . . . . . . . . . . . . . . . .

Page 80----------------- Appendix ---------------- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 78Detailing the Area Plan for Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 74Floorplanning with a netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 73NetList Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 70Making the terminal display more informative. . . . . . . . . . . . . . . . . . . . . . . . .Page 64IO Constraints for IO Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 59Creating an Initial Area Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 56Simple Model for a Black Box Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 54Preparing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 53IO FloorPlan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 50Flattening CHIPTOP to 1 macro level of hierarchy . . . . . . . . . . . . . . . . . . . . . .Page 49Selective Design Flatteningin ChipBench . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 48Working with a Netlist based Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 47Loading a Netlist Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 39The Hierarchy Planner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 38Hierarchy Planner Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 28Running Early Floorplanning with DSL I/Os . . . . . . . . . . . . . . . . . . . . . . . . .Page 27Loading a DSL model description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 26Early FloorPlanning w/DSL IOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 25Creating DSL from a block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 24Block Diagram for CHIPTOP Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 23Introduction to our Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 10Loading with an Empty Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 9Loading with an Empty Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 6Setup theGuide for the Class Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 5Configure theGuide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 4Manual Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 3Student Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 1IO and Block Floor Planning Lab Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . .




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Student Notes




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Manual Conventions

The following conventions are used in this document. Please be

sure to read and understand these conventions to prevent errorsduring the lab exercises.

The standard UNIX text editor "vi" is specified in the lab manual.You may use any editor you prefer. In the Common DesktopEnvironment, dtpad is available. On the IBM Internet, the ve (pclike) editor is available.

vi

Indicates that the string should be replaced by a value. Consultyour instructor if you are not sure of a value. For example, if myuserid is "student10" and the lab said:

cd /afs/eda/u//etcI would type in:

cd /afs/eda/u/student10/etc

Indicates a torn off drop down menu, for instance:

Selection>>Pre-Select::Ports>>

Indicates a menu section qualifier for otherwise ambiguousselections, for instance:

Selection//Balloon Help::Cells

::

Indicates a series of drop-down menu selections from a menu baror pop-up menu. An example would be:

Constraints//Fix//Self Location

//

Select an icon from the window icon bar:

Zoom In

Select an item from a tree view:

All Settings//PowerType//VDD2

Select an item from the window menu bar using the mouse:

File//Save//Vim...

Text following this symbol indicates the action menu item toselect using the right mouse button:

Edit//Move

Text following this symbol should be entered on the Tcl command

line on the ChipBench nutgui window.

Text following this symbol should be entered on an xterm windowcommand line on the server running ChipBench.

Used to indicate a series of selections on a ChipBench dialog.These are considered part of a numbered step.

Identifies a procedure heading. Immediately following eachprocedure heading will be a short explanation of what is to bedone. The steps to be performed are each numbered and followthe explanation. Only numbered steps are to be performed.




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Configure theGuide




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Setup theGuide for the Class ExampleWe will use theGuide to process our part thru the floorplanning methodology.

Starting an xterm on the compute serverIt is important to run the design tools in this class on the class compute server andnot the display server due to memory requirements.

1. To start an xterm on the compute server, right click on the gray background ofyour Citrix window and select:

Open Window on Compute Server

Be sure to run all your commands and applications beginning from this window.

Basic SetupWe will perform the basic setup for theGuide. We will force theGuide to start without

a project file so you get a chance to build a new project from scratch.1. From the student home directory:

./bin/theguide -gui -no_project -features cu08/* tk* &

The -features option tells the guide to load only the cu08 and toolkitcomponents. This prevents loading by default support for technologies that weare not using.

1. Press OKto confirm it was okay to start without a project file.

2. From theGuide menu bar:

File//New Project

3. Press OKon the new project information dialog.

4. In the methodoloogy advisor display, expand the item:

First Time User StartUp methodology

5. Expand the item:

Select Technology and Version

6. Follow the listed directions by selecting from theGuide menu bar:

Setup//Technology//cu08//7.0

Note: The above technology version (7.0) may be different in later toolkits. Askyour instructor for guidance if there is more than one selection available.

7. In the methodology advisor display, expand the item:

(Optional) Load Design Specific Data from ChipBench parms file

8. From theGuide menu bar, select:

Setup//Load ChipBench Parms




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9. Select the StartingDSL.parms file.

10.Press OPEN to confirm the selection.

11.Skip the Load Design Specific Data from ASOC Project File step.

12.On the methodology advisor dialog, expand the Enter Design Specific Data

flow option.13.From theGuide menu bar, select:

Setup//Design

14.On the General tab in the Design Setup dialog, enter:

Project Name as chiptop

Set the Working Directory to /work

Set the Design Vim Type to VIME (PHYSCELL)

15.Click on the Operating Conditions tab of the Design Setupdialog.

The values for the technology have already been set to the defaults.16.Click on the Design Specific Data tab on the Design Setupdialog.

Note that many of the values have been instantiated from the values in theChipBench parms file we read in earlier.

17.Enter the name of the IOSpecList file by:

Clicking the File icon to the right of the IOSpeclist File field.

In the left hand column, double click on the sub-directory usercntl

In the right hand column, select the file:

chiptop.iospec

Press OK

18.Enter the name of the DesignSpecList file by:

Clicking the File icon to the right of the DesignSpecList File field.

In the left hand column, double click on the sub-directory dsl

In the right hand column, select the file:

CHIPTOP_top_level_dsl.tcl

Press OK

19.Change the the Image Type to c4

20.Click on the Timing tab of the Design Setupdialog21.Change the hierarchical divider character to /

22.Switch to the Assertions sub-tab of the Timing tab

You will note that the assertion files have been filled in from the ChipBenchparms file we loaded earlier.




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23.Switch to the PLL sub-tab of the Timing tab

Leave the PLL count set to 0, we have an early netlist.

24.Switch to the Parasitic Files sub-tab of the Timing tab

We will let ChipBench calculate all parasitics dynamically so we will not enteranything on this page for now. Any parasitic read in from this dialog will bestatic, i.e., ChipBench will not recalculate a value for the parasitic even as thedesign changes. Reading in parasitics should be used with caution.

25.Switch to the Advanced sub-tab of the Timing tab

We will leave the default values in place for our lab exercise.

26.Click on the Overrides tab on the Design Setupdialog.

We will not enter any overrides or underrides for our design.

27.Click OKon the Design Setup dialog to confirm our choices.

28.On the Create Sandboxwindow set the following values: New Type = Sandbox

New Sandbox Name = chiptop_init

Transformation Template = standard

Initial Data = Create Empty Root Node

GUI Parameter Set = New Set Name = chiptop

29.Press OKto confirm your selections.

30.The Data Organizer Setupwindow will automatically appear.

31.Select the folder icon to the right of the VIMIN entry.

32.Select the folder icon at the bottom of the dialog.

33.On the resulting dialog, in the right hand column, select the VIM calledStartingNoData.

34.Press OKtwice to back out of the file selection dialog

35.Press OKto confirm your Data Organizer setup.

36.On the Save Changesconfirmation dialog, press OK.

This saves our choices to the CHIPTOP.proj project file. We are ready to beginusing some tools to floorplan under theGuide.




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Loading with an Empty Netlist




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Loading with an Empty NetlistWe will load our design into chipbench in two phases. In the first phase we will load thephysical parameters of the chip image and package. In the second phase we will loadour logic representation by reading in a DSL file The DSL file allows us to model

architecturally significant blocks in our design.

Invoking ChipBenchThis procedure will start ChipBench bringing up the ChipBench nutgui window and aseparate console window to display messages from the applications.

1. Expand theGuide item

Process Design

2. Expand the Guide item:

Run Tools or functions from Methodology Advisor

3. From theGuide menu bar, select

Methodologies//IO and Block Planning (Beta)

4. Using the right mouse button, select and execute:

Configure Methodology//Execute//with GUI

5. On the IO and Block Planning Configuration menu, set the following values:

On the Tool Tab:

For IO Style, select the file button to the right of the field and select:

AreaArray.

For Image, select the file button to the right of the field and select: generic.

For Design Source, select the file button to the right of the field and select:

IOSpecList. For Design SpecList, move your mouse over the Design Spec List input field

which is prefilled with a Guide variable.

Hover your mouse over the field and in the resulting information bubble, youshould see the variable evaluates to:

/dsl/CHIPTOP_top_level_dsl.tcl

On the Design Setup Tab:

Nothing needs to be specified on this page.

6. Make sure the action is set to launch and press OKto run the step.

You should now have a yellow checkmark indicating completion of the step.

The following diagram shows the methodology fully expanded as displayedunder the guide.




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7. Select and execute:

Create IO SpecList//Execute//with GUI

This step creates a header for the IO SpecList file that we will use later in theprocess. This header contains keywords based on the image and technology

which we have already selected.

8. On the dialog for Create IO Speclist Tool tab, move your cursor over the set theIO SpecList name and pause for the bubble information to pop up. You shouldsee that the variable evaluates to:

/usercntl/chiptop.iospec

9. Press the Launch editor button.

View the IO Speclist we loaded, DO NOT MAKE ANY CHANGES.

Do not perform any steps in the following description . I have alreadyperformed the actions for the purposes of time. The IO Speclist you are seeing

is the result of the following actions.I have provided you with the complete IOSpeclist required for the lab. Duringnormal operation, you would only have gotten the portion of the file about the #Port declarations comment created. Creation of the port declarationsthemselves are a user task at this time. If you already have a vim specifyingthese ports available, the following series of actions in a ChipBench session canadd the ports specified in the vim to the IOSpeclist file for you.

# read in any existing IO Speclist data

> iospec::read_io_speclist -file $env(HOME)/usercntl/chiptop.iospeclist

# add any ports specified in vim that are not present in iospeclist> chb::update_io_speclist -merge_missing_ports

# Write out updated speclist to a file

> iospec::write_io_speclist -file \/afs/btv/data/eda007/chip/u6200/fp2/usercntl/chiptop_out.iosp

10.Press PF3 to quit the IOSpec edit session without saving any changes

11.Press OK to complete the step

12.The Create IO SpecList step on the Methodology Advisor should now bechecked.

13.Select and execute:

Create VIM//Execute//with GUI

14.Uncheck the option for Top Level Insertion Parm File

15.Press OKto continue.

Notice that the chipbench consolewindow appears first.




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This window will contain messages about what ChipBench is doing.

dark blue text (theGuide) green text (native ChipBench)Tcl Commands

Displayed as red text, with an (S) in the message.Severe ErrorsDisplayed as red text, with a (E) in the messageErrorsDisplayed as yellow text, with a (W) in the messageWarningsblack text (theGuide) dark blue text (native ChipBench)Informational

Clicking on the Errors or Warnings icon in the ChipBench console icon bar willnow display a seperate window showing only errors or warnings. Clicking on anerror or warning in this seperate window will move the view screen of theChipBench console window to the location in the log where that error or warningoccured.

16.The ChipBenchnutgui window and a Top Level Insertion dialog are nowdisplayed.

17.Press Cancel on the Top Level Insertion window to close the dialog.

We have now started a ChipBench session under theGuide IO & BlockPlanning methodology flow and have initialized the design image withoutactually loading a netlist. We will load a DSL file to build our design model in afew minutes.

Note: The next lab exercise experiments with what we can see with only imagedata loaded. There are no actual design actions. If you have previously donethis next exercise, you can skip ahead to the section PreNetList DSL.

What you can see w/o a netlist loadedAlthough we do not have a netlist loaded, we can still inspect many aspects of ourdesign. Anything physically related to our chosen chip image and package should

be viewable.

1. Raise the ChipBench main window to the top of your display by clicking on itsborder.

2. Open a Graphic Windowfrom the ChipBench main window icon bar.

Graphic Win

3. From the Graphic Windowmenu bar, select:

Visuals//-----------

4. Move the Visuals Tear-offmenu to a convenient locations on the display.

Note: The GW1 in the motif window title indicates that this tear off is associatedwith Graphics Window 1. This allows you to determine which Graphic Windowwillbe affected when more than one Graphic Windowis open.

5. From the Visuals Tear-offmenu, select:

Terminal Visibility (Image)

You should now be able to see the terminal pattern on the back of the image.




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6. From the Visuals Tear-offmenu, select: Blockage Visibility (Image)

You should now be able to see blockage at the image level.




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7. From the Graphic Window icon bar, Mag in to a corner of the chip and be sureto include at least a few terminals.

You should be able to see the blockage shapes in the chip corners. You shouldalso be able to see blockage associated with the terminals.




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8. From the Visuals Tear-offmenu, select:

Circuit Row Visibility

You should now be able to see circuit rows on the design and now they truncateat the corner of the chip due to the blockage.

Note: In the previous picture, you can see rows of white circles running acrossthe design. These indicate the legal placement locations (circuit rows) forcircuits which are constraned to be placed on the IO cell placement grid definedin the technology PDL.

9. Turn off the circuit row visibility using the above switch again (Its a toggle)




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10.From the Visuals Tear-offmenu, select:

PST Visibility (Image)

1. Now Max out to view the entire chip.

You should now see the predefined PSTs in the image.




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2. Now select

Package Pin Visibility

3. From the Graphic Window icon bar, select:

Max

You should now see the package pins on the chosen package in physicalrelationship to the chip.

4. From the Graphic Window menu bar, select:

Selection//-------------

5. Reposition the Selection Tear-off Menu

6. Turn on both:

Terminals

Show Names::Terminals

7. From the Icon Bar, turn on:

Family Highlight

By the way, a yellow sun appears over the family in family highlight wheneverthis mode is active.




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8. Now select a terminal or package pin.

A fly-line will appear to show the connection between the selected item and itscounterpart as shown in the previous screen shot. The Show Names selectionalso causes the bubble information for the terminal to appear.

9. Select a terminal on the chip.

10.Press Mouse Button 3 and on the terminal action menu, select: Windows//Attribute

You will get an attribute window showing physical and electrical attributes forthe selected terminal as well as the technology restrictions on its usage.




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11.Change the selected terminal

The terminal attribute window will update with the values for the newly selectedterminal.

12.Select the Selection tear offmenu and press Escape to close it.

13.Press Max to restore the view of the chip in the Graphic Window

You can also view voltage regions in the Graphic Window with only the imagedata loaded. To turn on a voltage region:

14.Scroll to the bottom of the hotlist on the right hand side of the Graphic Window(Cu08 has many available and somewhat specialized voltage regions).

15.Turn on the voltage regions (supplies) for one of the available HSS locations byclicking mouse button 3 over:

HSS6AVTR

HSS6AVTT

16.Now press the refresh key (circular arrow) at the top of the hotlist and the HSS

position 6 regions will appear.

17.Turn on the voltage regions (supplies) for one of the available PLL locations byclicking mouse button 3 over:

PLL1AGND

PLL1AVDD

PLL1AVDD2

18.Now press the refresh key (circular arrow) at the top of the hotlist and the PLLposition 1 regions will appear.

19.Turn on one the voltage regions by pressing mouse button 3 while over each

voltage region matching volt_reg_VDD# where # is a value from 2 to 9 for ourimage.

volt_reg_VDD2

20.Then click the refresh icon at the upper left corner of the hotlist to force thedisplay to redraw.

Feel free to turn on and off the images voltage regions so you can understandthe voltage region layout.




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The chb::change_voltage_domain command allows switching second supplypower C4s to a different supply. This may only be used if the generic imageswitch was set at chipinit time.

You can also look at existing power structures in the design. The followingscreen shot shows the M7 power and M8 PST power structures on our design.

21.Now turn off the voltage regions by pressing mouse button 3 while over each of

the entries you have turned on. Each entries text should grey out as you turnoff the display.

22.Then click the refresh icon for the display to redraw.




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23.Make sure to turn off the following visibility's on the Visuals tear off menu:

Blockage Visibility (Image)

PST Visibility (Image)

Package Pin Visibility

Circuit Row Visibility

24.Press Escape to close the Visibility Tearoff menu.




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Introduction to our Design

The Design Spec List (DSL) language can used to create amodel of the design based on early architectural descriptions ofthe design at varying levels of complexity. In additionChipBench can create an abstracted model of a real netlist touse for post netlist floorplanning. I have used this second path

to construct the example DSL for our design lab.




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Block Diagram for CHIPTOP Design

BLKBOX

SM0

SM1

RU1 RU2 RU4RU3

Two 32-bit Data In Busses8-bit cmd bus

64-bit DATAOUT

(Bidi with DATAIN)

LOG_BLK

DO_MUX

Data Out (32)

Data Out (32)

Data In (32), CMD (8), ADDRESS (8)

BLACKBOXOUT (1)

ADDRESS (8), CMD(8)

(All 64 bit busses)

SRAM_READ(64)

FAIL (1)




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Creating DSL from a block diagramSince we want to get an early look at our part, even prior to the availability of netlists,we could construct a model of our design using the Design Spec List language to createa high level connection map of the design. SInce DSL commands are really Tcl

commands, the power of the Tcl languge can be used to help create repetative designstructures, etc.

If you have a machine readable netlist description in some format that you can convertand read into ChipBench, then you can use ChipBenchs abstracted netlist mechanismto create a simplified model of the design for floorplanning purposes.

Creating DSL (read only)

For expediancy on our class part, I have recreated the block diagram previously shown

using:

chb::compile_abstract_netlist

This command creates an abstracted netlist from the actual netlist by abstracting awaydust logic and creating representative connections to represent paths thru theabstracted logic. This abstracted netlist was then written out in DSL format using:

chb::write_abstract_netlist

This creates a DSL model of our design for all the architecturally significant elements

including IOs. Some change all commands were necessary to remove suffixes to cellnames to get them to match back to the real design later. Pseudo code editorcommands to achive this are:

change _CHIPTOP_VDEF change _CHIPTOP_VUSG

Once we have DSL ready we can then proceed to load our generic image and load theDSL into chipbench to perform some early floorplanning of our design.

Please use the DSL I have prepared for you as specified in the following lab.We dont want to spend precious class time debugging typographic errors.

Thank you!




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Early FloorPlanning w/DSL IOs




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Loading a DSL model description

Running the Top Level Insertion StepThis step will allow us to load a DSL and IOSpecList file to build our design model.

1. Enter the following command on the ChipBench main window command line:

chb::read_design_speclist -file $env(HOME)/dsl/CHIPTOP_top_level_dsl.tcl

2. Now load the physical data and attach it to the netlist created in memory fromthe DSL.

chb::prepare_physical_data

The following two steps are not actually run in our lab since this is ourfirst pass of the design but are here for documentation purposes.

Now read in the previous floorplan PDEF layout file if any exists: chb::read_pdef -file $env(HOME)/pdef3_pass1/CHIPTOP.pdef

Note that a dsl or vim netlist must be loaded before you can read in the PDEFphysical floorplan data. Also you will need to read in a PDEF file for eachhierarchical cell (chip, rlm) in the design in order to load a complete floorplan.The PDEF definition does not provide for any automatic hierarchical loadingcapability.

Repeat the above step for each macro in the design substituting the macro DEFname for the string CHIPTOP.

You can find the list of cells to be saved in the right hand pane of the

ChipBench main window. The names in the list are shown in the formatDefName:Instance Name. Enter only the DefName portion in thechb::read_pdef command.

For more information on the DSL language, see the DSL Command ReferenceManual.




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Running Early Floorplanning with DSL I/Os

Assigning Terminals and Placing I/O Cells

1. Reselect the root cell.2. Open a Graphic Window if one is not already open.

Graphic WIndow

3. On the cell action menu select:

Interface//Chip IO Assignment//Driver Type Match...

4. On the Driver Type Match dialog, switch on:

Move Driver Cell

Note: All the constraints supported by Driver Type Match could be used at thispoint including voltage regions, tethers and port areas. We have not set any up

in this lab exercise. We will do so in a subsequent lab You are free to usethese features on a DSL model of a design.

5. Press OK.

Early FloorplanningIn the following procedure we will use floorplan in stand alone mode.

1. Set the macro size estimates using the following pre-encoded tcl script:

source SetDSLSizes

Nothing magic in this script. We just encoded reasonable estimates for the

macro sizes rather than having you hand instantiate each macro.2. Look in $HOME/tcl/SetDSLSizes.tcl to see the declarations of macro size.




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The following screen shot shows what you should be seeing in the GraphicWindowat this point in the design process.

Note the IO books clusted about the center of the design, placed directly on top

of their assigned terminals (note this is not yet legalized) and you can see theRLMs we just sized shown in the lower left corner of the design.




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3. With the Graphic Window open, select:

Placement//FloorPlan...

4. To run floorplan, select the following items:

FloorPlan switch on

Optimize switch on

Turn off Legalize

Consider Large Objects switch on

Honor Fixed Leaf Cells switch on

Ignore Voltage Regions switch off

5. Select the Options... button for Optimize

6. Set the Large Object Displacement Weight slider to 0

7. Set the Wire Length Weight to 3.




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8. You can also try setting the cost of moving IO books to 5 rather than 1 asshown in the graphic below. Ive found this gives me better results.

9. Press OKto accept the Optimize Options... settings

10.Move the floorplan dialog window off the top of the Graphic Window.

11.Press Apply.

If you watch the console output window, you can see the reporting on eachphase of the floorplanner iteration




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12.View the placement.

We didnt legalize so there will be overlaps. The overlaps you are getting will beexcessively large with the macros in some cases basically center to center.When the macros are overlapped tightly like this, it means they are relativelyhighly connected. However, we have so many center to center overlaps herewe see that we need to raise the value for the overlap cost for floorplan.

We also see that the IO cells are wandering during the placement due to theeffects of the connected wires (we didnt fix them in position on this pass).

We could have raised the overlap weight on the first pass to reduce the numberof iterations at the expense of reducing the information available to help visuallyinterpret the density of connections. However legalizing on the first pass wouldcompletely obscure any information contained in overlaps. It is recommendedthat you do not immediately legalize on your first pass of floorplanning.

13.On the floorplan dialog, press the Option button next to Optimize.

14.Change the Overlap weight to 10.




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This will reduce overlaps between macros in the next pass of floorplanning.

15.Turn on Refresh Placement.

This will allow you to watch the placement change interactively.

16.Press OKon the Option dialog

17.Press Apply on the Floorplan menu.

You should see a much better result this time. However you will see that the IObooks have definitely started to wander around the design.

Snap the IO Books back to their original assigned terminalsThis action will cause the IO books to be snapped back to their original assignedterminals regardless of overlap undoing any placement movement on the IO booksby the floorplanner.

1. On the cell action menu select:

Interface//Driver Type Match...

2. On the Driver Type Match dialog, switch on:

Move Driver CellThis essentially gives priority to IO net length during the following legalization as youare defining the placement position directly over the IO cells as the optimum positionto floorplan legalization in the following step.

Legalize the floorplanIn legalization we will

remove overlaps between macros and I/Os

legally place the macros on circuit rows legally place I/Os on the IO placement grid

1. On the FloorPlandialog, turn offOptimize and turn on Legalize.

We will not turn on any of the detailed options for legalization since this is anextremely early floorplan and we dont need that level of detail yet.

2. Press OKto run FloorPlan and close the FloorPlan menu.

Optimize the IO wire length after LegalizationSince the wire lengths may have been damaged during legalizaiton, we can run

another IO assignment tool to see if we can make improvements. In the process thistool will also check to see if all the IO resistances are in spec.

1. To make the IO nets visible during the next action do the following from theaction menu using mouse button 3:

Select//Ports

Select//Internal Net//All




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2. On the Graphic Window menu bar, select:

Highlight//Highlight with Color

3. Select the color wheel

4. On the color menu, select Dark Orange.

5. Reselect the chip.Now you can see the IO nets show in orange even when not selected.

Heres an example situation from my floorplan.

6. On the Graphic Window action menu, select:

Interface//Optimal I/O Assignment

7. On the Optimal I/O assign dialog, you can set:

Max Resistance Factor to 1

Switch on Ignore Voltage Regions




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Vertical to 6

8. Press Apply

9. Check the console for resistance failures. Resistance failures will show up asthe entry in the console Total Ports Not Assigned being a value other than 0.

Heres the example shown above after Optimal IO processing.

If you can successfully assign IO below 1.00 Max Res. Factor, the difference isa design margin available to you. If you cannot assign at or below 1.00 Max

Resistance factor you have IO issues to resolve. However for class purposes,do not worry about fixing them if you see them, but on this class part youprobably will not find any resistance problems.

If there are no resistance failures try lowering the value of Max ResistanceFactor, say to 0.85. Keep lowering the resistance factors until you get somefailures. With the IO net highlighting on, it will be easy to see failed nets as




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the unassigned ports will cause the IO flylines for unassigned nets to form astar on the chip.

If there are resistance factors, slowly raise the resistance factor until thereare none.

Press Cancel to close the dialog when you have a good result

Note: If we had not run the chb::prepare_physical_data step earlier, theresistance values necessary for this analysis and calculation would not havebeen available.

Capture the placement data using PDEF

We can now use pdef format to save our design floorplan.1. On the chipbench command line, create the output directory:

mkdir $env(HOME)/pdef_plan_01

2. On the chipbench command line, now type:

chb::write_pdef -directory $env(HOME)/pdef_plan_01 -def CHIPTOP -syn_1998




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The PDEF information is useful for taking the current floorplan layout forward toa new drop of the netlist

3. Note: Please double check the $env(HOME)/pdef_plan_01 directory to makesure it now has data in it, we will be referencing this data later in the designprocess. From the chipbench command line:

ls $env(HOME)/pdef_plan_01 Save the VIM

1. On the ChipBench menu bar, select:

File//Save//Design....

2. On the Save Designdialog at the Directory field at the bottom of the page, press

the Select... Button.

3. Take note of the current Guide output node.

4. Press OKto save the design.

5. Exit ChipBench.




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Hierarchy Planner Lab

Exercising the Hierarchy Planner within the Chip Benchenvironment




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The Hierarchy PlannerIn this set of exercises we will use the hierarchy planner to manipulate our design.

Loading a design netlistFirst we need to load the design netlist into a new ChipBench session

1. Close your previous ChipBench session if you have not already done so.

2. On theGuide menu bar, select:

Tools//ChipBench Via Socket//With Gui

3. On theGuide Gui panel for ChipBench, make sure the switch Load Design isoff.

4. Press OKto start a ChipBench session.

5. From the ChipBench main window menu bar:

File//Load//Specify Data...

6. Select Read Parms...

7. Select StartingData.parms in the rightmost list.

8. Press OK

The Netlist search path should now have a value. This time we are loading ourdesign and a netlist exists for it in VIM format.

9. Make sure the Design Type is set to Chip.

10.Click on Initialize Image and select Options....11.Make sure a PDL Package File and Vim Chip Image are specified.

12.Under Options make sure Initialize Power is selected

13.Make sure Generic Image is selected

14.Press OK on the Initialize Imagepanel.

15.Press OKon the Design Specificationwindow.

16.Confirm creation of the work directory.

Our design will take a minute or so to load.Note: The design will appear to be empty, all cells are unplaced and theunplaced cell visibility is off. thats okay, we dont need placement data to workwith the hierarchy planer.

17.On the ChipBench icon bar, select:

Load Library




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18.Press OKto load the library to allow the hierarchy planner to count latches.

Creating some flat dataIn our case, our design data is already pretty hierarchical so in order to build an

interesting test case for the hierarchy planner, we will flatten our design.1. If a Graphic window is not open, open one now:

Graphic Window

2. Make sure you have CHIPTOP selected from the Graphic Windowmenu bar by:

Window//Select Root Cell

3. Use the following command to flatten the entire design:

chb::flatten_hierarchy -prefix_children_names -hierarchy_name hier_plan -to_leaf

You will get error messages about rule boxes and external views not loading.This is normal for all the RLM objects since they do not have rules yet (they will

be constructed as part of the design process later).You will also get warnings about physical data not being flattened. This is justtelling you that since the cells are not placed, the flattener cannot maintain theirrelative position on the chip which is the default behavior with placed objects soplacement data is not lost.

This command does the following:

flattens the entire hierarchy (-to_leaf)

creates a new hierarchy structure in memory called hier_plan(-hierarchy_name hier_plan)

Note: You can switch back and forth between our flattened design and theoriginal hierarchy at any time by selecting Hierarchy//Set Current.... on the cellaction menu for ChipTop. The original hierarchy is called ChipTop and the newhierarchy is called hier_plan.

prefixes the names of promoted cells with the name of the parent cell theywere contained within (-prefix_children_names)

4. If you look in the console, you will see that ChipBench used a . as thedelimiter to separate names during the prefixing.

Using the Hierarchy plannerIn this exercise we will open the hierarchy planner and explore our flattened design.

1. To ensure that you are looking at the hierarchy called hier_plan:

Hierarchy//Set Current...

2. Check that hier_plan is the selected hierarchy.

3. Press Cancel.




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If you press OK, you will get an error since hier_plan should normally be theactive hierarchy if you have followed the base directions.

4. Now, on the ChipBench icon bar, select:

Hier Planner

5. On the Cluster Cellsdialog, set the delimiter to the character ./ as shown above

6. Switch on the Ignore ISCAN* Nets to ignore the scan chains

7. Press OK.

The Bubble GuiWhen the Cluster Cells action has completed, the bubble hierarchy display windowis opened.

1. To view the Connectivity Viewwindow, on the Hierarchy Viewwindows menu bar,double click on the desired bubble and the Connectivity View window will opendisplaying that object.

First lets enlarge the text to make things a little easier to read.

2. From the Connectivity Viewwindow menu bar, select: Edit//Preferences




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3. On the bottom half of the window,

click on the Hierarchy Viewtab

set the text size to Large click on the Connectivity Viewtab

set the text size to Large

4. Press OK

5. To switch focus back to the Hierarchy Viewwindow, on the Connectivity Viewwindow menu bar, select:

Hierarchy View

Now lets explore some more information about the design.

6. Toggle back to the Hierarchy View

Notice the cursor in the above screen shot is pointing to the menu bar button totoggle to the Connectivity View. This menu bar button will raise an existing

Connectivity View window to the top of the Z-stack making it visible.

Also note the list of information about each bubble in the right hand pane.

7. Click on the headers for each column in the right hand pane one at a time.

The list will be sorted based an the data in that column. The sort is always intodescending order. In the screen shot above, note that the Area column ishighlighted in yellow. This indicates that this is the current sort.

8. Click on the bubble LB in the left hand pane.

Note: Single clicking selects the bubble item. Double clicking will raise thebubble view window and switch its viewing context to the selected bubble.

9. Raise the action menu by pressing the right mouse button and selecting:

Expand

Note that LB expands into its sub-component bubbles.

10.Sort the data right hand pane from the menu bar by selecting:

Area




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Note that the area column is not completely in descending order. All the entriesat the top level of the hierarchy are in order and all the expanded entries underLB are in order by Area. However the hierarchical structure is maintained andall the expanded entries under LB remain together as a group in the sorted list.They will move as a group with their parent LB as it moves in the sort order butwill remain nested under LB and sorted into descending order as a separate

subgroup

11.From the Hierarchy Viewmenu bar, select:

Connectivity View

12.Now double click the top level.

You should be looking at the top level of the design as bubbles. Note that theIOs and the CLKS bubbles are quite large. This is due to our testcase designwhich does not contain a lot of user logic.

Right now each bubble only contains its name. Lets make the bubble displaymore informative.

13.From the Connectivity Viewmenu bar, select:

Display//Big Instances

The bubbles update with an entries that shows the number of big instancescontained in the bubble.

14.From the Connectivity Viewmenu bar, select:

Display//Latches

You should now see the latch counts for each block in the Connectivity View.This latch count is cumulative, it shows the total latches below that level ofhierarchy.

15.To see this cumulative counting at work, note the number of latches indicated

for the SM1 bubble (216), then double click the SM1 entry on the Hierarchy Viewsnavigator.

The Connectivity Viewdives in one level of bubble hierarchy. We now see thesub-component bubbles under SM1.

16.On the Connectivity View, select the following:

Display//Latches

You will see the number of latches on the sub-components are:

SRAM0 = 0 latches SRAM1 = 0 latches BLOCK_LABEL = 192 CMD_DECODE = 24 BIST = 0 Total equals 216 as expected




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17.On the Hierarchy View, double click the topmost - entry to return to the top levelon the Connectivity View.

18.If a Graphic Windowis not open, on the ChipBench main windowicon bar, select:

Graphic Window

Creating an ordered placement for viewing purposesFor our next series of exercises it will help to have an ordered placement for thedesign. This is an extremely crude placement since we have not correctly dealt withIO assignment, etc. We will cover these issues elsewhere in the labs. Note that thisplacement is not necessary for the work we are doing with the bubble view but ratherto illustrate the cooperative nature of the hierarchy planner and the Graphic Window.

1. Raise the cell actionmenu for ChipTop (RMB) and select:

Placement//CPlace

2. On the CPlacedialog,

turn on the Perform Global phase turn offPerform Detailed phase

turn offPerform Legalization phase Set the XFactor to 1.4

Steiner Estimation Mode

Ignore Clock Nets

Ignore Scan Pins

3. Press OKto run CPlace

4. Now back on the Connectivity View, left click over the IOs bubble to select thebubble.

Cross Selection and HIghlighting with the Hierarchy plannerThe Hierarchy planner and ChipBench use common highlighting and selectionfunctions.

1. Raise the bubble action menuusing a right mouse click and select:

Cells//Select

Look at the Graphics Window. The cells we selected in the Connectivity Viewarenow selected in the Graphics WIndowas well.

2. On the Graphic Windowmenu bar, select:


This causes our previously selected cells to deselect and only ChipTop to beselected once more.

3. On the Connectivity View, left click over the IOs bubble again.

4. Now from the bubble action menuselect:




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Cells//Highlight

The cells which are members of the IOs bubble are now highlighted on theGraphics Windowin the same color as the IOs bubble on the Connectivity View.

5. On the Connectivity View, left click over another bubble and highlight itsassociated cells.

6. You can have multiple highlight colors displayed in the Graphic Windowvia theConnectivity Viewhighlighting mechanism.

We can now do the same with nets.

7. On the Connectivity Viewwindow, left click a bubble connection.

8. Raise the bubble net action menuand select:

Real Nets//Highlight

The nets will be highlighted in the Graphic Windowusing the same color used todisplay the bubble connection in the Connectivity View.

Editing the Bubble HierarchyWe can also edit the bubble hierarchy in the Hierarchy planner in addition to viewingthe bubble hierarchy. Lets dissolve the IOs bubble.

1. Left click the IOs bubble in the Connectivity View

2. Raise the bubble cell action menuand select:

Dissolve

The IOs group has now disappeared and in its place are 15 sub groupscontaining related IO cells. For instance, note that there is a group calledIOs.COMMAND() which contains 8 Big Instances. This is a 8 bit IO bus forcommands that the hierarchy planner has clustered based on their relatednames (only the strand names are different).

We can also merge components back together.

3. On the Hierarchy View, select IOs.PLL_TUNE.

4. On the Hierarchy View, multi-select (Cntl-LMB) PLL_RESET

5. Raise the bubble cell action menuand select:

Add

6. Enter a name (PLL_IOs) for the new bubble on the name dialog

7. Press OK

Now look at the Hierarchy View. You will see a new bubble called PLL_IOs in thelist.

8. Select the PLL_IOs bubble in the Hierarchy View

9. Double click the PLL_IOs bubble to expand it




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Note that you can see the original IOs.PLL_TUNE and IOs.PLL_RESET assub-bubbles within PLL_IOs.

Moving Bubbles within the Hierarchy PlannerYou can also create virtual layouts within the Hierarchy Planner

1. To move a cell: left click a bubble to select the bubble to move

left click and hold while dragging the mouse to move the bubble

release the click when the bubble is in a better relative location.

Note that the bubble connections track the new location of the bubbleautomatically.

You can also create groups of cells easily in the hierarchy planner.

2. On the Connectivity Viewmenu bar, select:

File//Create Groups

3. Now on the ChipBench main window, raise the cell action menu and select:

Grouping //Group Lists//Cell Groups

4. You will see groups in the list beginning with the string bv_. These groupscorrespond to the bubble structure that was in place when the Create Groupsaction was run. Rerunning the command will rebuild the groups from scratch.

5. Exit out of chipbench.

Note: You will not need to save your data. We will start with a fresh copy forour next experiment.




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Loading a Netlist Design




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Working with a Netlist based DesignIn this design phase, we will assume we have gotten a netlist from our customer and wewant to take the floorplan we have developed so far and use it with the new, moredetailed netlist. For this pass of design we will use the default abstract netlist (Dust

Logic Aware abstraction) generated by the floorplan_flow script

Loading a design netlistFirst we need to load the design netlist into a new ChipBench session

1. Close your previous ChipBench session if you have not already done so.

2. On theGuide menu bar, select:

Tools//ChipBench_Via_Socket//With Gui

3. On theGuide Gui panel for ChipBench, make sure the switch Load Design isoff.

4. Press OKto start a ChipBench session.

5. From the ChipBench main window menu bar:

File//Load//Specify Data...

6. Select Read Parms...

7. Select StartingData.parms in the rightmost list.

8. Press OK

The Netlist search path should now have a value. This time we are loading our

design and a netlist exists for it in VIM format.9. Make sure the Design Type is set to Chip.

10.Click on Initialize Image and select Options....

11.Make sure a PDL Package File and Vim Chip Image are specified.

12.Under Options make sure only the following options are selected:

Initialize Power (Post-Invocation)

Generic Image

13.Press OK on the Initialize Imagepanel.

14.Press OKon the Design Specificationwindow.

Our design will take a minute or so to load.

15.Now load the rules by doing:

File//Load Library...

16.Confirm the fields are filled in and press okay to load srules and ndrs.




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Selective Design Flatteningin ChipBench

ASIC design guidelines require that incoming designs are eitherflat (no hierarchy) or that the hierarchy is limited to 1 level ofmacros (no nested macros). The logic design (an early netlist)

you have received for this design example does not meet thatcriteria as shown in the hierarchy window below. In this sectionwe will flatten the design to 1 level of macros.




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Flattening CHIPTOP to 1 macro level of hierarchyCHIPTOPs hierarchy contains hierarchical structures that need to be flattened forvarious reasons. Note that we could choose for floorplanning purposes to leave thehierarchy deeper than 1 level, however a design that you are driving to completion must

have no more than 1 level of macros.

Our Flattening Strategy

The following is a list of cells and why they should be flattened. Please be sure youalso understand the reasons why these items are being flattened.

CLKS

The CLKS macro contains the clock distribution network for the design. Thisclock distribution network needs to be spatially distributed across the entire chipwhile one of the characteristics of a macro is that it constrains its contents to bein a sub-region of the design. We will have to flatten CLKS to get a proper clock

tree network spread over the design.

SM0, SM1

These two macros will remain macros on the design but currently they aremultiple levels of hierarchy deep. We will flatten the contents of SM0 and SM1so they only have leaf cells as children. Note that SM0 and SM1 are twoinstances of the same macro. We will only really have to flatten the contents ofone instance since that will flatten both instantiations.

RU1, RU2, RU3, RU4

The RU# macros are four instances of the same logic. The RU# macros eachcontain the logic driven by a single SCB in the original incoming logic. We aregoing to eventually flatten these four macros to allow swapping of clock treeconnections between the various children of the macro. Hierarchy wouldprevent this since cells on logically equivalent nets cannot be swapped across ahierarchical boundary. However at the beginning of the design process, we willflatten the internals of the RUs but keep the macro itself and treat it as a clockdomain to help us with our structured clock buffer placement and skew controlby limiting the size of the clock domain. Note that this is not a methodologyrequirement but a design strategy we are employing with this design.




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Flattening to one level of hierarchyCHIPTOP will be flattened to a single level hierarchy using the strategy as outlinedabove using the following TCL script. Please review the script and make sure youunderstand what is happening. The hierarchy editing features of ChipBench can

also be accessed interactively from the cell action menu (Mouse Button 3) and the

following actions are available: Hierarchy//Flatten

Hierarchy//Flatten Children...

Hierarchy//CreateThe copy of the class example flattening script in the student directory$HOME/tcl/AdjustHierarchy has more comments/output statements in it for yourreference.

chb::current_cell -rootputs "Flatten clock generator macro...."

chb::flatten_hierarchy -cell CLKS -no_create_move_boundschb::current_cell -rootputs "Flatten the contents of the RU's common DEF...."chb::flatten_hierarchy -cell RU1 -prefix_children_names -to_leaf -no_create_move_boundschb::current_cell -rootputs "Flatten the contents of the LB macro...."chb::flatten_hierarchy -cell LB -prefix_children_names -to_leaf -no_create_move_boundschb::current_cell -rootputs "Flatten the contents of SM0...."chb::flatten_hierarchy -cell SM0 -prefix_children_names -to_leaf -no_create_move_boundsputs " this also flattens SM1 since it is another instance of same cell!!!!"chb::current_cell -rootputs "Flatten contents of DO_MUX"

chb::flatten_hierarchy -cell DO_MUX -prefix_children_names -to_leaf-no_create_move_boundschb::current_cell -root

1. Open the Hierarchy Viewer window if one is not already open.

Windows//Hierarchy Viewer

2. On the Hierarchy Viewerwindow, click each box shape preceding a macro thathas a dot within it. Keeping doing this until all the filled box shapes have beenreplaced by empty boxes.




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For each macro expansion you will see a pop-up asking if you want to loadthe data (internal netlist) for the macro you are expanding. Affirm each one.You will not get a popup if the object has no internal netlist.

Note that you might see some delay while ChipBench processes this. Since wehad loaded the design in incremental mode as we expand the hierarchy tree,additional net lists and physical definitions will be loaded.

The hierarchy view of the design is now fully expanded, you are looking at thefull representation of the design structure prior to flattening. Note that youwould not need to do this to run the command, this is for visualization purposesonly.

Note: In ChipBench 11.1 you will just be able to set Full Import in Model ImportDefaults to get this to happen during design load automatically

3. From the Hierarchy Viewer select CHIPTOP.

4. On the ChipBench nutgui window command input field, type:

source AdjustHierarchy

When the script finishes running the CLKS macro has been completelyflattened out of the design. RU1 through RU4, LB, DO_MUX,SM0 and SM1 nolonger have any macro children, i.e., they are macros, not supermacros.

When you manipulate an object's hierarchy later in the design process(flattening or creating hierarchy), you should retrace clock and scan nets afterthe hierarchy change to be sure your clock and scannet group informationrecorded in the vim is correct. We will not need to do this since we have not yettraced our design.




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IO FloorPlan




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Preparing the DesignWe will need to setup our voltage regions for the design and bring our previous floorplanforward into the actual netlist. We also need to trace out the clock and scan structures

on the design so they can be ignored for early phases of floorplanning and placement.The following procedure runs a script for tracing both clock and scan on the design andalready has the required parameters set for you. For more information on clock design,see the EDA course ChipBench Clock and Tree Design.

Setting up our voltage regionsFor most designs, additional voltages will have to be supplied to portions of the chip.This is done via voltage regions. The following step from the IO and Block Planningflow will run this action.

1. Find theGuide window with the IO and Block Planning methodology in it.

2. Select Define Voltage levels with mouse button 13. Press mouse button 3 to raise the action menu and select:

Execute//With Gui

4. On theGuide Gui forDefine Voltage levelspress Launch.

Since we started our chipbench session with the ChipBench_Via_Socket option,theGuide will generate the script to set the Voltage Regions based on ourIOSpecList and send the script to the ChipBench tcl executor via the socket.You can view this script by using the location specified for the executed script inthe ChipBench console output from theGuide action.

There is also a hand written script in $(env)HOME/tcl/SetVoltageRegions.tclwhich does essentially the same thing.

Bring our floorplan data forwardNow we will bring the placement and size data forward from the DSL floorplan.

1. Now load the placement from the previous floorplan session

chb::read_pdef -file $env(HOME)/pdef_plan_01/CHIPTOP.pdef

You will get more warnings here about the dummy IO_BUS. Again this is okaybecause the netlist has real I/O in it and the remainder of the process will usethe real I/O rather than our IO_BUS models.

At this point, you can read in each of the macro pdefs to get the macro sizes orto shorten things for class, just run the following script to reload the sizes.

source SetDSLSizes

Tracing the design using a script

1. Make sure CHIPTOP is the currently selected cell




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2. On the ChipBench main windows command line, type:

source TraceDesign

3. Review the console output for any problems.

Note: You will see the following problems which for the purpose of our lab have

no effect. The cause of the problem is shown in bold, with a sample messagefollowing. Some of these messages will have multiple instances.

Normal operation in a hierarchical design[CD-463]: (W) Net CE1_C_RAM in cell LB is driven by a hierarchy port and has multiplesinks.Optimization may cause the net to be split into multiple nets, replicating port

CE1_C_RAM on cell LB.

Because we didnt initialize the integrated timer, not necessary for trace[ET-477]: (W) No calculator registered, NOPATH modeling applied for

PAD_ABIST_TST_CCLK.

We havent yet placed the contents of the RLMs.[CD-469]: (W) Placement view does not exist for instance RU1.




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Simple Model for a Black Box MacroFor this design, we will assume that we have a large macro in the design for which wehave not received the internal logic description. We have a CHIPTOP netlist which calls

out a black box macro and defines its inputs and outputs. Remember that ChipBench isa four dimensional planner. We will specify values for (x,y,z,t) for our black box. Forthis design we will assume that we have estimated the size of the object to be 1800tracks wide and 3600 tracks tall. In addition, we will need four metal wiring layers toroute the internal circuits and set our timing assertions.

Setting up a black box macro for floorplanning

1. On the nutgui window, from the tree select:

CHIPTOP

Note on the nutgui window, CHIPTOP gets a blue background and a fine red

outline around the border of the blue background. The fine red outline meansthe cells was selected by clicking on it in the nutgui windowtree.

2. Bring up a Hierarchy Viewerwindow.

Windows//Hierarchy Viewer

3. Select the macro instance "BLK_BOX" from the list of hierarchical cells on theHierarchy Viewerwindow.

Note that after the selection in the Hierarchy Viewer, that CHIPTOP now has theblue background in the nutgui windowbut no red outline is present. If no redoutline is present the tree in the nutgui windowis providing you NO informationon what cell is selected or current. Note that the Hierarchy Viewer window doesnot have this flaw. It will correctly track the selected cell(s) no matter themethod or how many cells. We highly recommend you use the Hierarchy Viewerwindow anytime you need to use the window for feedback on selection.

Remember that the current size is the standard initial guess provided by ChipInitialization.

4. Display the Exact Resizedialog so that you can manually set the size ofBLK_BOX:

Edit//Exact Resize...

Notice that there are two other resizing options on the menu. The Resize

function allows you to interactively drag the corners/sides of a macro to resizeit, the Resize by Factorfunction allows you to set multiplication factor for the areaof the macro. Using either of these will require us to legalize the macro sizeafterwards using (usually) the Area Planner. We will see this tool in a later lab.We will just Exact Resizethe macro to a legal size for the moment.

5. Set the "Width" field to 1800 wiring tracks.




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Macro widths should be set to multiples of the gate array channel step size.You can find keyword values for both the gate array (3) and standard cell (1)step size in the RULEDEF record of the PHYSICAL view of the macro.

6. Set the "Height" field to 3600 wiring tracks.

7. Click OKto run the Exact ReSizeaction and close the dialog.BLK_BOX will grow to the specified size. We now need to set the number ofwiring layers that ChipBench will assign to this macro for its internal wiring.

8. Display the Highest Reserved Layerdialog so that we can set the ceiling.

Planning//Reserved Areas//Set Highest Reserved Layer...

9. Select "M4" as the ceiling (top most metal layer usable by macro).

10.Click OK.

11.Change the display theme by:

Themes//Color Cells by Attribute

If you unselect BLK_BOX, its outline color is red.

To set the states of all macro location and shape constraints for laterprocessing, do the following.

12.Select all the macro children of the chip.

chb::select_cell -macro

13.Unfix the shape of the selected macros.

Constraints//Unfix Shape//Self

To prevent the next set of floorplanning actions from recalculating thenecessary size for our BLK_BOX macro based on no cells in the internal netlist(results in a size of 0 by 0),

14.First select BLK_BOX by:

chb::select_cell BLK_BOX

15.Now set the Shape constraint to fixed to prevent BLK_BOX from being resized.

Constraints//Fix Shape//Self

If the color by attribute feature is on, the outline of "BLK_BOX" will now beyellow when it is not the currently selected object. This indicates that"BLK_BOX" is fixed in shape.

Setting Up a Black Box for TimingIn addition to asserting the physical constraints on our BLK_BOX macro, we will alsowant to establish timing constraints at it's input and output ports. Remember that thetiming specs for an internally defined object are subject to the Columbus effect.Inputs on the macro are signals leaving the defined logic domain (outputs) andoutputs on the macro are signals entering the defined logic domain (inputs).




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For the inputs, we will set the required time of arrival to allow signals to meet theproposed internal macro timing requirements. This can be done with the TCLcommand

et::set_required

For the outputs of the macro we will need to specify the arrival times that signals willarrive at the macro outputs from the internal logic as well as the slew rates of thesesignals. This can be accomplished with the TCL commands

et::set_arrival et::set_slew

We will also set the failure calculator mode to NOPATH.

In our design the timing assertions for BLK_BOX were provided by the logicdesigner in the original timing assertions for CHIPTOP.

To see the timing assertions that were set in the assertion files:

1. Switch to the usercntl directory where we put the assertion files.

cd $HOME/usercntl

2. Search the assertion files for lines pertaining to BLK_BOX

grep BLK_BOX chiptop.*.cmd

Here is a sample of the output from this grep. We can see the assertions thatthe logic designer created for the BLK_BOX macro.

chiptop.eta.cmd:et::set_required -pins {{BLK_BOX/SIMILAR1_DATA(25)}} -phase "B0+R" -time 3.50chiptop.eta.cmd:et::set_required -pins {{BLK_BOX/SIMILAR1_DATA(26)}} -phase "B0+R" -time 3.50chiptop.eta.cmd:et::set_required -pins {{BLK_BOX/SIMILAR1_DATA(27)}} -phase "B0+R" -time 3.50chiptop.eta.cmd:et::set_required -pins {{BLK_BOX/SIMILAR1_DATA(28)}} -phase "B0+R" -time 3.50chiptop.eta.cmd:et::set_required -pins {{BLK_BOX/SIMILAR1_DATA(29)}} -phase "B0+R" -time 3.50chiptop.eta.cmd:et::set_required -pins {{BLK_BOX/SIMILAR1_DATA(30)}} -phase "B0+R" -time 3.50chiptop.eta.cmd:et::set_required -pins {{BLK_BOX/SIMILAR1_DATA(31)}} -phase "B0+R" -time 3.50chiptop.pis.cmd:et::set_arrival -pins {{BLK_BOX/OUT_NET}} -phase "B0+R" -time 0.50chiptop.pis.cmd:et::set_slew -pins {{BLK_BOX/OUT_NET}} -phase "B0+R" -time 0.50

If we were going to load timing assertions from a separate file we can justsource the assertions using source on the ChipBenchTcl command line.

Note that these assertions would be loaded in the current session but would notbe available in subsequent ChipBench sessions unless you once again sourcethe file with the new assertions. Merging the new assertions into the assertionsfor CHIPTOP avoids this inconvenience.




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Creating an Initial Area PlanWe will now calculate the area required by each macro/partition to successfully containits child objects. The Area Planner will perform the following functions:

Traverse the hierarchy both top down and bottom up resolving each cell. Estimate the placement and wiring area requirements for each macro/partition.

Assign shapes and aspect ratio limits to for reshaping macros and partitionsbased on shapes of their respective child cells and the relative wiring congestionin the X/Y directions.

The area planner will also calculate the ceiling (implicit reserved layer) for eachmacro and partition (the topmost wring layer the cell will be able to use)

Initializing Blockage EstimatesIn this procedure we will define wire track blockage estimation parameters for image

(power rails, etc.) and book blockage. At this point in our design, since we have noplacement data ChipBench cannot use actual values from placed books. Insteadestimates of wiring plane blockage will be calculated based on whether an area iswithin the active image and/or circuit row placement area. This will allow thedesigner to begin developing design information and proceed to an initial placementat which point the designer may refine area planning numbers using the AreaUpdate function.

1. From the ChipBenchnutgui window make sure CHIPTOP is the currentlyselected object.

2. On the ChipBench command line, type the following:

source SetDesignBlockageThis command causes the ChipBench TCL interpreter to search for and load afile called SetDesignBlockage. This file is found in your$HOME/tcl directoryon your student account. If you had wanted to explicitly define the directory inwhich to find the tcl, the following syntax would also work:

source $env(HOME)/tcl/SetDesignBlockage

The commands in this file set the image and leaf cell blockage estimates foreach wiring plane in our design (see the contents of this file in the next figure).The text output from the TCL script will appear in the consolewindow. We couldalso have set these values from the ChipBench graphics user interface. We

can go to the user interface now to view the values set by our TCL script.3. Raise the cell action menu using Mouse Button 3 and select

Planning//Set Blockages for Design...

On the resulting dialog window you should see all the values set by the scriptdisplayed. You could also create or edit these values via this window. For now,leave the values as set by the script.




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4. Press Cancel to leave the window without making any changes.

The contents of the SetDesignBlockage file is as follows:

echo " "echo "----------------------------------------- "echo "SA-27E TCL Design Blockage Example"echo "EDA Customer Education Team - Do Not Copy"echo "----------------------------------------- "echo "Design name: [ current_cell]"echo "Constraint file name: assert_design_blockage"echo " "echo "Setting PC image blockage...."chb::set_layer_blockage_averages -layer {PC} -image_blockage 50.0echo "Setting PC leaf blockage...."chb::set_layer_blockage_averages -layer {PC} -average_leaf_blockage 35.0echo "Setting M1 image blockage...."chb:: set_layer_blockage_averages -layer {M1} -image_blockage 25.0echo "Setting M1 leaf blockage...."chb:: set_layer_blockage_averages -layer {M1} -average_leaf_blockage 35.0echo "Setting M2 image blockage...."

chb:: set_layer_blockage_averages -layer {M2} -image_blockage 9.1echo "Setting M2 leaf blockage...."chb:: set_layer_blockage_averages -layer {M2} -average_leaf_blockage 0.0echo "Setting M3 image blockage...."chb:: set_layer_blockage_averages -layer {M3} -image_blockage 12.5echo "Setting M3 leaf blockage...."chb:: set_layer_blockage_averages -layer {M3} -average_leaf_blockage 0.0echo "Setting M4 image blockage...."chb:: set_layer_blockage_averages -layer {M4} -image_blockage 12.5echo "Setting M4 leaf blockage...."chb:: set_layer_blockage_averages -layer {M4} -average_leaf_blockage 0.0echo "Setting M5 image blockage...."chb:: set_layer_blockage_averages -layer {M5} -image_blockage 12.5echo "Setting M5 leaf blockage...."chb:: set_layer_blockage_averages -layer {M5} -average_leaf_blockage 0.0

echo "Setting M6 image blockage...."chb:: set_layer_blockage_averages -layer {M6} -image_blockage 95.0echo "Setting M6 leaf blockage...."chb:: set_layer_blockage_averages -layer {M6} -average_leaf_blockage 0.0echo "assert_design_blockage complete!"echo " "

Note that this is not an official set of numbers. You should obtain the correctvalues for your technology from your ASIC field engineer.

Running the Hierarchical Area Planner

We will now run the Hierarchical Area Plannerto create estimates for the area requiredfor each macro/partition in our design. On this first set of estimates, we will use acommon set of assumptions for the entire design and allow the hierarchical areaplanner to traverse the entire design hierarchy. These assumptions will be refinedlater in our floorplanning process as we develop more information about our design.

1. Be sure CHIPTOP is selected.




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2. Reset the color scheme and then apply Color by Attribute Theme.

Themes//Default Settings

Themes//Color Cells by Attribute

3. Confirm that the macro BlackBox is fixed in shape (yellow or blue)

You can also see the setting by selecting a macro and looking in the attributeinformation box at the bottom of the Graphic Window

4. Confirm the other macros in the design are not fixed in shape (yellow or blue)

5. Raise the Action Menu by pressing Mouse Button 3.

6. Select from the Cell Actionscascade menu select::

Planning//Hier. Area Planning...

7. On the resulting Area Planning Panel, set the following options on the ParametersPage ON:

Resize/Reshape Soft Blocks

This will allow area planning to alter the shapes of supermacros andmacros.

Descendants Only 9999

8. Make sure the following options are turned OFF

Create Circuit Rows

This action would copy circuit rows from the chip level image into themacros to allow legalized placement of the macros children. Since wehave not placed the RLMs yet, we will hold off on this action.




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Trim Soft Blocks to Circuit Rows

The macro boundaries would be trimmed back to an integer multiple of thecircuit row height and placement cell width. We will hold off on this actionalso.

Click on the Resize/Reshape Options... button.

Set the Density(%) to 67.00

This sets the maximum density that leave cells will be assumed at in the

design cell. As the density goes down, the size of the containing cell mustgrow to accomadate the child cells.




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Set Hard and Soft Macro Padding Factors to 1.10

Multiplies area of child macros by the specified factor when calculating therequired area requirements for placing and wiring the child macro withinthe parent macro. A soft macro is a child macro without a fixed shapeconstraint. A hard macro is a child macro with a fixed shape constraint.

The Library, Hard and Soft Macro areas calculated using the paddingfactors are added together and used as the minimum allowable spacerequired to house the macros child cells.

Set the Core to I/O Gap to zero

Specifes the distance between the core logic and the I/O ring. Set this tozero since we are doing an RLM

Encounter I/O File

Support for reading in an Encounter I/O File. We will not be using anEncounter IO file in class

Consider Wire DemandThe "Consider Wire Demand" button tells Area Planner to estimate howmuch space is required to wire the circuits once they are placed. If therequired space is larger than the wiring capacity of the calculatedplacement space, the X/Y size of the macro will be increased and theceiling of the macro adjusted if necessary (ceiling adjustment will occureven if the Create Reserved Areas for Signal Wiring is off.

Consider Placement Reserved Areas

The "Consider Placement Reserved Area" button tells the Area Planner toinclude the effects of placement reserved areas in the size estimation of

the macro. This was initially used only for clock books but other uses arenow practiced.

Create Reserved Areas for Signal Wiring

This option tells the area planner to do a statistical analysis of theconnections in the logic and adjust the ceiling of the macro as necessary.

9. Press OKto return to the Area Planner main dialog.

10.Press OKto run the Hierarchical Area Planner.




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IO Constraints for IO Assignment

Creating Fixed IO Assignments using a Tcl scriptIO locations can be manually pre-assigned prior to any automated I/O assignmentfunctions and fixed in location to prevent the automatic functions from modifyingthem. Assigned but unfixed I/O locations can be used to provide seed informationon I/O positions in a flow.

1. On the ChipBench Graphic Window menu bar, select:

Visuals//Port Visibility

2. Notice the stack of blue port indicators at the center of the chip.

If you had family highlighting on, the ports would have already been visible. Ifyou had highlighted the ports with chb::highlight_port, they would have alsobeen visible but you can switch that off with Visuals//Always Obey VisibilitySettings.

3. On the ChipBench main window command line, type:

source IOPreAssign

4. You will now see 10 ports turn orange and assume new positions on the designover the terminal they have been assigned to.




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5. Review the contents of the IOPreAssign script below:

# explain operationsecho "Processing system clocks by assigning ports to package_pins...."echo "Processing test io control lines by assigning ports to terminals...."

# echo all the commands to the consoleset incoming_observe_state [observe]observe -all

chb::assign_terminal -package_pin_name E08 \

-port TST_ACLK -fix_assignmentchb::assign_terminal -package_pin_name M03 \

-port TST_BCLK -fix_assignmentchb::assign_terminal -package_pin_name N03 \

-port TST_CCLK -fix_assignment

chb::assign_terminal -terminal NEKT70 -port DI1 -fix_assignment




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Note that we assigned ports using two conventions, one where we assign a logicalport to a package pin, the other where we assign a logical port to a chip terminal.Either method is acceptable. ChipBench uses the technology rules to map thepackage pin method to the correct chip terminal.

Interactively Assigning Ports to TerminalsYou can also use ChipBench to interactively assign IO to terminals. This is usefulfor doing a few pre-assignments or for editting the generated assignment to correctany issues.

1. Make sure ChipTop (the chip) is the currently selected cell from the GraphicWindow by:


2. Raise the cell action menu (Mouse Button 3) and select:

Windows//Lists//Ports

3. Raise the cell action window again and select: Windows//Lists/Terminals

4. Find and select the CHIPTOP/BS_SCAN_IN port in the port list window

5. Press Mouse Button 3 to raise the Port Action menu and select:

Edit//Assign to Terminal

6. In the Terminal list window, find the terminal which is attached to package pinK12 and select it.

Note: You can only do selection in the terminal column although you can seethe name of the associated package pin.

7. BS_SCAN_IN will appear as the assigned port on the terminal list windowsthird column.

Note: You may need to widen the Terminal List window to see all the fields fulllength.

We can also work the problem starting from the terminal side.

Note that the package pins are not in alphabetical order so this can be a chore

8. To resolve this problem, on the terminal list window menu bar select:

Options//Sort

9. Select Package Pin10.Press OK.

11.Now find and select the terminal associated with package pin E13 in theterminal list window

12.Raise the terminal action menu and select:

Edit//Assign to Port




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13.In the port window, select the port BS_SCAN_OUT.

BS_SCAN_OUT will appear as the assigned port in the terminal list window.

14.Scroll up and down the terminal list window.

You should be able to also see the assignments that we made in the previous

script, IOPreAssign.15.To identify the two ports we just assigned on the Graphic Window menu bar,

select:

Visuals//Text Visibility

16.On the port window, select BS_SCAN_IN.

17.On the port window, hold down the Ctrl key and select BS_SCAN_OUT.

Both cells are now selected and a text label appears next to them.

18.In the terminal window, select the Terminal attached to port BS_SCAN_OUT

19.Raise the action window using mouse button 3 and select:20.Windows//Attributes

21.A terminal attribture window appears with attribute information.

Creating Port Area Contraints for our design

Lets say that we have some groups of I/O that we want to contrain to particularregions of the chip. We may have developed this information by looking at an earlierfloor plan, by restrictions generated by the floorplan of our system board, etc. Wewill use the following set of port area restrictions for our design.


April 24, 2006 Page 67IBM EDA Education

floor planning lab

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