FIR FilterCMPE 222 – Project

Divya Misra

Gnanapriya Mohanavelu

FIR Filter

Aim of the project

• Study the effect of latency

• Study the effect of type of adders on area&timing

• Understanding the synopsys tool

• Effect of taps on filters

Terms used

• Coefficients

• Taps– Memory

– No. of calculations

– Filtering

– Advantages• Stop band attenuation

• Less ripple

• Narrower filter

3-tap filter

Actual timing diagram

3-tap filter Architecture

What we did

• Combinational circuit for addition– Synthesis (had problems)

• All multiplications in the same stage

• Feeding constants externally– Synthesis (had problems)

Timing diagram with latency 5

      

Timing Diagram after reducing the latency to 3

Timing Diagram after increasing the latency to 6

Latency

3 clock cycles

5 clock cycles

6 clock cycles

Area 79051.89 69508.45 79051.89

Timing 9.61 9.61 9.61

map_effort = medium + boundary optimization

Synthesis

• list command– Lists information about the

commands,variables and licenses in the design analyzer or standard dc_shell

– e.g.: list link_library

link_library = {"typical.db"}

Shell script used for synthesis

%dc_shell

free –design

alias veri “read –f verilog”

veri fir.v

veri fir_ctrl.v

veri fir_dp.v

link

compile –map_effort medium –boundary_optimization

Changing the type of adder

dc_shell>current_design fir_dp

dc_shell> report_resourcesImplementation Report

==========================================================================

| | | Current | Set |

| Cell | Module | Implementation | Implementation |

===========================================================================

| mult_30 | DW02_mult | csa | |

| mult_36 | DW02_mult | csa | |

| r124 | DW01_add | rpl | |

==========================================================================

dc_shell>set_implementation clf r124

dc_shell> report_resources

Changing the type of adder (contd.)

Implementation Report

==========================================================================

| | | Current | Set |

| Cell | Module | Implementation | Implementation |

===========================================================================

| mult_30 | DW02_mult | nbw | |

| mult_36 | DW02_mult | wall | |

| r124 | DW01_add | clf | clf |

==========================================================================

Area and Timing

Carry Look Forward

Ripple Carry Adder

Area 72023.21 69508.45

Timing 8.90 9.61

sample

c0

16-tap filter

D DD D

++ ++

c3c2c1 c15

result

Logic used

A = sum0+sum1

+sum2+sum3

D = sum12+sum13

+sum14+sum15

C = sum8+sum9

+sum10+sum11

B = sum4+sum5

+sum6+sum7

Result =A+B+C+D

Timing Diagram

Area & timing

• Area = 985775.25

• Timing = 9.77