cmpe-310 - swe.umbc.edu
TRANSCRIPT
CMPE-310Lecture-04: 8086 Chipset
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
Outline
8086 Device Specification
8086 Pinout
Clock Generator
Bus Timing (Read, Write)
MIN- MAX Mode
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
8086/88 Device Specifications
Both are packaged in DIP (Dual In-Line Packages)8086: 16-bit microprocessor with a 16-bit data bus8088: 16-bit microprocessor with an 8-bit data bus
Both are 5V parts (i.e. VDD is 5V)8086: Draws a maximum supply current of 360mA8088: Draws a maximum supply current of 340mA
80C86/80C88: CMOS version draws 10mA with temp spec -40 to 225oFInput/Output current levels:
Yields a 350mV noise immunity for logic 0 (Output max can be as high as 450mV while input max can be no higher than 800mV). This limits loading on the outputs.
Input Logic level Voltage Current Output Logic level Voltage Current
0 0.80V max +/- 10uA max 0 0.45V max +2mA max
1 2.0V min +/- 10uA max 1 2.4 V min -400uA max
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
8086 Pinout
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
8086 Pinout
AD15-AD0Multiplexed address(ALE=1)/data bus(ALE=0).
A19/S6-A16/S3 (multiplexed)High order 4 bits of the 20-bit address OR status bits S6-S3.
M/๐ฐ๐ฐ๐ถ๐ถ
Indicates if address is a Memory or IO address.๐น๐น๐น๐น
When 0, data bus is driven by memory or an I/O device.๐พ๐พ๐น๐น
Microprocessor is driving data bus to memory or an I/O device. When 0, data bus contains valid data.ALE (Address latch enable)
When 1, address data bus contains a memory or I/O address.DT/๏ฟฝ๐น๐น (Data Transmit/Receive)
Data bus is transmitting/receiving data.๐น๐น๐ซ๐ซ๐ซ๐ซ (Data bus Enable)
Activates external data bus buffers.
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
8086 Pinout
S7, S6, S5, S4, S3, ๐บ๐บ๐๐ , ๐บ๐บ๐๐, ๐บ๐บ๐๐S7: Logic 1, S6: Logic 0.S5: Indicates condition of IF flag bits.S4-S3: Indicates which segment is accessed during current bus cycle
๐บ๐บ๐๐ , ๐บ๐บ๐๐, ๐บ๐บ๐๐ : Indicate function of current bus cycle (decoded by 8288).
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
8086 Pinout
INTRWhen 1 and IF=1, microprocessor prepares to service interrupt. ๐๐๐๐๐๐๐๐ becomes active after current instruction completes.๐ฐ๐ฐ๐ซ๐ซ๐ต๐ต๐ต๐ตInterrupt Acknowledge generated by the microprocessor in response to INTR. Causes the interrupt vector to be put onto the address bus.NMINon-maskable interrupt. Similar to INTR except IF flag bit is not consulted and interrupt is vector 2.CLKClock input must have a duty cycle of 33% (high for 1/3 and low for 2/3s)VCC/GNDPower supply (5V) and GND (0V)MN/ ๐ด๐ด๐ด๐ดSelect minimum (5V) or maximum mode (0V) of operation.
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
8086 Pinout
๐ฉ๐ฉ๐ฏ๐ฏ๐ซ๐ซBus High Enable. Enables the most significant data bus bits (D15-D8) during a read or write operation.READYUsed to insert wait states (controlled by memory and IO for reads/writes) into the microprocessor.RESETMicroprocessor resets if this pin is held high for 4 clock periods. Instruction execution begins at FFFF0H and IF flag is cleared.๐ต๐ต๐ซ๐ซ๐บ๐บ๐ต๐ตAn input that is tested by the WAIT instruction. Commonly connected to the 8087 coprocessor.HOLDRequests a direct memory access (DMA). When 1, microprocessor stops and places address, data and control bus in high-impedance state.HLDA (Hold Acknowledge)Indicates that the microprocessor has entered the hold state.
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
8086 Pinout๐น๐น๐ถ๐ถ/ ๐ฎ๐ฎ๐ต๐ต๐๐ and ๐น๐น๐ถ๐ถ/ ๐ฎ๐ฎ๐ต๐ต๐๐ : Request/grant pins request/grant direct memory accesses (DMA) during maximum mode operation.๐ณ๐ณ๐ถ๐ถ๐ถ๐ถ๐ถ๐ถ : Lock output is used to lock peripherals off the system. Activated by using the LOCK: prefix on any instruction.QS1 and QS0 : The queue status bits show status of internal instruction queue. Provided for access by the numeric coprocessor (8087).
QS1 QS0 Status
0 0 No operation
0 1 First byte of op code from queue
1 0 Empty the queue
1 1 Subsequent byte from queue
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
8284A Clock Generator
โ Clock generationโ RESET synchronizationโ READY synchronizationโ Peripheral clock signal
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
8284A Clock Generator
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
8284A Clock Generator
Crystal is connected to X1 and X2.
XTAL OSC generates square wave signal at crystal's frequency which feeds:
An inverting buffer (output OSC) which is used to drive the EFI input of other 8284As.
2-to-1 MUX : F/C selects XTAL or EFI external input.
The MUX drives a divide-by-3 counter (15 MHz to 5 MHz).
This drives:โ The READY flip flop (READY synchronization).โ A second divide-by-2 counter (2.5MHz clk for peripheral components).โ The RESET flip flop.โ CLK which drives the 8086 CLK input.
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
8284A Clock Generator
RESETNegative edge-triggered flip flop applies the RESET signal to the 8086 on the falling edge.The 8086 samples the RESET pin on the rising edge.
Correct reset timing requires that the RESET input to the microprocessor becomes a logic 1NO LATER than 4 clocks after power up and stay high for at least 50ms.
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
Bus buffering and latching
Computer systems have three busesโข Addressโข Data
โข Control
The Address and Data bus are multiplexed (shared) due to pin limitations on the 8086.The ALE pin is used to control a set of latches.
All signals MUST be buffered Buffered Latches for A0-A15.Control and A16-A19 + ๐ฉ๐ฉ๐ฏ๐ฏ๐ซ๐ซ are buffered separately. Data bus buffers must be bidirectional buffers.
In a 8086 system, the memory is designed with two banksHigh bank contains the higher order 8-bits and low bank the lower order 8-bitsData can be transferred as 8 bits from either bank or 16-bits from both๐ฉ๐ฉ๐ฏ๐ฏ๐ซ๐ซ pin selects the high-order memory bank
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
Bus buffering and latching
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
Bus Timing
Writing:Dump address on address bus.Dump data on data bus.Issue a write (๐พ๐พ๐น๐น) - set M/๐๐๐๐ to 1.
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
Bus Timing
Reading:Dump address on address bus.Issue a read (๐น๐น๐น๐น) - set M/๐๐๐๐ to 1. Wait for memory access cycle.
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
Bus Timing
Read Bus Timing:
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
Bus Timing During T1:
The address is placed on the Address/Data bus.Control signals M/IO, ALE and DT/R specify memory or I/O, latch the address onto the address bus and set the direction of data transfer on data bus.
During T2:
8086 issues the RD or WR signal, DEN, and, for a write, the data.DEN enables the memory or I/O device to receive the data for writes and the 8086 to receive the data for reads.
During T3:
This cycle is provided to allow memory to access data.READY is sampled at the end of T2.
If low, T3 becomes a wait state.
Otherwise, the data bus is sampled at the end of T3.
During T4:
All bus signals are deactivated, in preparation for next bus cycle.Data is sampled for reads, writes occur for writes.
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
Bus Timing
Each BUS CYCLE on the 8086 equals four system clocking periods (T states). The clock rate is 5MHz, therefore one Bus Cycle is 800ns.The transfer rate is 1.25MHz.
Memory specifications (memory access time) must match constraints of system timing.
For example, bus timing for a read operation shows almost 600ns are needed to read data.However, memory must access faster due to setup times, e.g. Address setup and data setup.This subtracts off about 150ns.Therefore, memory must access in at least 450ns minus another 30-40ns guard band for buffers and decoders.
420ns DRAM required for the 8086.
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
Bus Timing
READYAn input to the 8086 that causes wait states for slower memory and I/O components. A wait state (TW) is an extra clock period inserted between T2 and T3 to lengthen the bus cycle.For example, this extends a 460ns bus cycle (at 5MHz clock) to 660ns.
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
MIN and MAX mode
Controlled through the MN/๐ด๐ด๐ด๐ด pin.Minimum mode is cheaper since all control signals for memory and I/O are generated by the microprocessor.Maximum mode is designed to be used when a coprocessor (8087) exists in the system.
Some of the control signals must be generated externally, due to redefinition of certain control pins on the 8086.
The following pins are lost when the 8086 operates in Maximum mode.ALEWRIO/๏ฟฝMDT/๏ฟฝRDENINTA
This requires an external bus controller: 8288 Bus Controller.
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
8288 Bus controller
Adapted from lecture notes by Dr Chintan Patel and Avani Dave
Max Mode 8086 system