cmpe 110 class notes
TRANSCRIPT
-
8/9/2019 Cmpe 110 Class Notes
1/69
1
CmpE 110
Digital Electronics
Class Notes
ByDr. Ahmet Bindal
Revised August 2008
-
8/9/2019 Cmpe 110 Class Notes
2/69
2
CHAPTER I. RLC NETWORKS
A. BASIC CONCEPTS ON PASSIVE ELEMENTS
Resistance:
R
vR(t)
iR(t)
vR(t) = RiR(t)
[vR(t)] = VR(s) = R [iR(t)] = R IR(s)
)(
)(
)( sI
sV
sZ R
R
R=
Capacitance:
vC(t)
iC(t)
C
iC(t) = C( )dvc t
dt
[iC(t)] = IC(s) = C [( )dvc t
dt]
Laplace transform:
=0
)()( dtetfsFst
Thus:
[( )dvc t
dt] =
0
( ) stdvc te dt
dt
=
0
( )ste dvc t
But,
0
( )ste dvc t
= 0( )ste vc t -
0
( )( ) stvc t s e dt
= [0- (0)vc ] + s 0( ) stvc t e dt
= sVC(s) - vC(0)
Then:
[ ( )] [ ( ) (0)] ( )c c cic t C sV s v sCV s= =
Thus, ZC(s) =1
sC
-
8/9/2019 Cmpe 110 Class Notes
3/69
3
Inductor:
vL(t)
iL(t)
L
vL(t) =Li (t)d
dt
[ vL(t)] = VL(s) = L [Li (t)d
dt] = L [sIL(s) iL(0)] = sL IL(s)
ZL(s) = sL
B. TIME-DOMAIN ANALYSIS OF PASSIVE NETWORKS
(i) RC Circuits
Integrator:
+
-
R
Ci
vout
vin
Vin = Ri + vout
i = Cvoutd
dt
Vind
dt= R
di i
dt C+
di i
dt RC + =
1 Vind
R dt
General Solution:1
0di
idt RC
+ =
-
8/9/2019 Cmpe 110 Class Notes
4/69
4
Characteristic equation:
1 10s s
RC RC + = =
t
st RCgi Ae Ae
= =
0pi =
RC
t
pg Aetititi
=+= )()()(
0 0
1 1t t t
inRC
outV
v idt e dt C C R
= =
( ) 10t
RC
tin tRC
in eV
e RC V RC
= =
1t
RCout inv V e
=
Vin
t
vout
0
Differentiator
R
C
i
vout
+
-
vin
0
in c out
c
V v v
dv diR
dt dt
= +
= +
-
8/9/2019 Cmpe 110 Class Notes
5/69
5
0
10
i diR
C dt
dii
dt RC
= +
+ =
But, the characteristic equation:1
0s RC+ =
0)()()( +=+= stpg Aetititi
( )t
st RCi t Ae Ae
= =
( )t
RCoutv Ri t ARe
= =
But, (0) 0 (0)c out inv v V= =
inV AR=
Thus,inV
A
R
=
Thus,t
RCout inv V e
=
Vin
t
vout
0
-
8/9/2019 Cmpe 110 Class Notes
6/69
-
8/9/2019 Cmpe 110 Class Notes
7/69
7
L
Vi
L
R
dt
dip
p =+ L
VK
L
R=+0
R
VK=
Now put the general and particular solutions together:
R
VAeti
tL
R
+=
)(
Now solve for A by using the initial condition 0)0( =i :
0)0( =+=R
VAi
R
VA
=
==
t
L
Rt
L
R
eR
Ve
R
V
R
Vti 1)(
Use Lorentz Law to solve for outv
tL
Rt
L
R
tL
R
out
out
VeL
Re
R
VL
dt
eR
Vd
Lv
dt
diLv
=
=
=
=
0
1
RESULTS:
tL
R
out
tLR
Vev
eR
Vti
=
= 1)(
-
8/9/2019 Cmpe 110 Class Notes
8/69
8
(iii) RLC Circuits
RL
i (t)
vout (t)
C
vL
(t)
+
-
vin
)()()( tvtvtRiV outLin ++=
dt
tdiLtvL
)()( = and
dt
tdvCti out
)()( =
)()( tvdtdiLtRiV outin ++=
Differentiating both sides yields:
C
i
dt
idL
dt
diR
dt
dv
dt
idL
dt
diR out ++=++=
2
2
2
2
0
Characteristic equation: 2R 1
s + s + = 0L LC
1,2
2
22
R R 4
R R 1L L LCs = =
2 2L 2L LC
LetL
R
2= and
LC
10 =
2
0
2
2,1 =s
1 2i (t) =A + Bs t s t e e find A & B
At t = 0-, iL(0
-) = i(0
-) = 0
Since the current through the inductor cannot change suddenly, iL(0
+
) = i(0
+
) = 0
Thus, i(0) = 0 = A + B
A = - B
We need another initial condition to find A and B explicitly.
-
8/9/2019 Cmpe 110 Class Notes
9/69
9
Evaluatedt
tdi )(:
1 2 1 21 2 1 2
( )= A s + A s = A ( s s )s t s t s t s t
di te e e e
dt
However, at t = 0 vout (0-) = 0 and vR (0-) = i (0-) R = 0
When the switch is closed the voltage across the capacitor and the current through theinductor cannot change instantaneously
Thus: vout (0+) = 0 and vR (0
+) = i (0+) R = 0
+in L
0
V = v ( 0 ) = Lt
di
dt +=
Then:
)( 21 ssALVin =
( )in
1 2
VA =
L s s
( )in
1 2
VB =
L s s
( )( )1 2
in
1 2
Vi(t) =
L s s
s t s t e e
out inv = V i R Ldi
dt
where,( )
1 2in1 2
1 2
V= ( s s )
L s s
s t s t di e edt
( )( )
( )1 2 1 2in in
out in 1 2
1 2 1 2
V R Vv = V ( s s )
L s s s s
s t s t s t s t e e e e
( ) ( )
1 2
out in 1 2
1 2 1 2
R Rv = V 1 ( s ) + ( s )
s s L s s L
s t s t e e
+ +
where,2
0
2
1 =s and2
0
2
2 +=s
2
0
2
21 2 = ss
-
8/9/2019 Cmpe 110 Class Notes
10/69
-
8/9/2019 Cmpe 110 Class Notes
11/69
11
Then, KVL dictates:
( )11( ) ( )
sRCVinI s R I s
s sC sC
+ = + =
1 1( ) ( )Vout s I s
sC sC= =
Vin sC
s ( )1sRC+
1( )
1
VinVout s
RCs s
RC
= +
But,1
1s s
RC
+
1
A B
ss
RC
++
1
1 A s BsRC
+ +
( ) 1A
s A BRC
+ +
Thus:A
0 and 1RC
A B+ = = yields
and A RC B RC = =
1 1( )
1 1
Vin RC RC Vout s Vin
RC s ss s
RC RC
= =
+ +
1 1( ) 11
t
RCvout t Vin Vin ess
RC
= = +
-1
Differentiator
R
C
Vout
(s)
I (s)+
-Vin/ s
( )11( ) ( )in
sRCV I s R I s
s sC sC
+ = + =
-
8/9/2019 Cmpe 110 Class Notes
12/69
12
( ) ( )out
RCV s I s R= =
RC 1 1in in
V V
s s RC RC
= + +
1( )
1
t
RCout in in
v t V V e
sRC
= = +
-1
Homework:
Find vout(t) by performing frequency-domain analysis
C
Vout
(s)
+
-
Vin
/ s
(ii) RLC Circuits
R L
I (s)
Vout
(s)
C
VL (s)
+
-
Vin/ s
Assuming that vout(0) = 0 V and i(0) = 0.
1( )in
out
V I R sLs sC
IV
sC
= + +
=
1( )in out
VsCV R sL
s sC= + +
-
8/9/2019 Cmpe 110 Class Notes
13/69
13
2( 1)in outV
V RCs s LC s
= + +
2
1
1
( )
out
in
V LCRV
s s s L LC
=+ +
Solving 21
( )R
s s L LC
+ + yields:
2
1,2
1
2 2
R Rs
L L LC
=
or 2 21,2 0s =
Where,2
R
L = and 0
1
LC =
1 2 1 2
1
( )( ) ( ) ( )out
in
V K M NLCV s s s s s s s s s s
= + +
( )1 2( ) s t s t out inv t K Me Ne V = + + for 0t .
Where, 1K= , 2
2 1
sM
s s=
and 1 2
2 1
2s sN
s s
=
-
8/9/2019 Cmpe 110 Class Notes
14/69
14
(iii) STABILITY
Transfer Function
H(s)Vin(s) Vout(s)
(s)V
(s)VH(s)
H(s)(s)V(s)V
in
out
inout
=
=
The transfer function, H(s), can be described as follows.
D(s)
N(s)H(s) =
When N(s) = 0, the solution gives us the zeros.
When D(s) = 0, the solution gives us the poles and also tells us the stability of the circuit.
Poles
When solving for D(s) = 0, the solution should result in the following form:
js += where is the real component and is the imaginary component. These solutions (there
could be more than one solution for s) can then be plotted real vs. imaginary.
-
8/9/2019 Cmpe 110 Class Notes
15/69
15
Poles to the right of the imaginary axis shown as (0) and (1) are unstable causing theresulting waveforms similar to the following:
Poles that lay on the imaginary axis shown as (2) are oscillatory causing waveformssimilar to the following:
-
8/9/2019 Cmpe 110 Class Notes
16/69
16
Poles to the left of the imaginary axis shown as (3) and (4) are stable causing theresulting waveforms similar to the following:
-
8/9/2019 Cmpe 110 Class Notes
17/69
17
Example 1
We first transform the circuit with Laplace.
+
=+
=+
==
RCsRC
sRC
sCR
sC1
1
1
1
1
1
(s)V
(s)VH(s)
in
out
Now, to find the pole(s).
RCs
RCsRCsN
1
01
)(
=
=
+=
Plot this pole.
-
8/9/2019 Cmpe 110 Class Notes
18/69
18
From the position of the pole, we know that the circuit is stable and the waveform would
look as follows:
0
vin
t
vout
Example 2
We first transform the circuit into s-domain with Laplace.
-
8/9/2019 Cmpe 110 Class Notes
19/69
19
1
1
1
1
(s)V
(s)VH(s)
2in
out
++=
++==
sRCCLs
sCsLR
sC
Now, to find the pole(s).
( )222
2,1
2
1
222
4
01)(
=
=
=++=
CLL
R
L
R
CL
CLRCRCs
sRCCLssN
2
0
2
002
2
0
2
001
=
+=
s
s
where
LC
L
R
1
2
0
0
=
=
Assuming that L, R, and C are not zero and not negative there are three possible
solutions.
00 < There is not imaginary part.Plot these poles.
From the position of the pole, we know that the circuit is stable and the waveform wouldlook as follows:
0
vin
t
vout
-
8/9/2019 Cmpe 110 Class Notes
20/69
20
00 = There is not imaginary part.Plot this pole.
From the position of the pole, we know that the circuit is stable and the waveform wouldlook as follows:
0
vin
t
vout
00
> There is an imaginary part.Plot these poles.
2
2
21
L
R
CL
2
2
21
L
R
CL
-
8/9/2019 Cmpe 110 Class Notes
21/69
21
From the position of the pole, we know that the circuit is stable and the waveform wouldlook as follows:
-
8/9/2019 Cmpe 110 Class Notes
22/69
22
CHAPTER II. FUNDAMENTALS OF CMOS CIRCUITS
A. BRIEF THEORY OF SEMICONDUCTORS
Si Si Si
Si Si Si
Si Si Si
electron
INTRINSIC SEMICONDUCTOR
-
8/9/2019 Cmpe 110 Class Notes
23/69
23
Si Si Si
Si As Si
Si Si Si
extraelectron
N-TYPE EXTRINSIC SEMICONDUCTOR
-
8/9/2019 Cmpe 110 Class Notes
24/69
24
Si Si Si
Si As Si
Si Si Si
freeelectronpositively charged
site (DONOR)
-
8/9/2019 Cmpe 110 Class Notes
25/69
25
Si Si Si
Si B Si
Si Si Si
hole
P-TYPE EXTRINSIC SEMICONDUCTOR
-
8/9/2019 Cmpe 110 Class Notes
26/69
26
Si Si Si
Si B Si
Si Si Si
negatively charged site
(ACCEPTOR)free electron
-
8/9/2019 Cmpe 110 Class Notes
27/69
27
electron path
N+ N+
P
VGS
VDS
N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET)
e
e
e
metal gate
gate oxidesourcedrain
bulk
-
8/9/2019 Cmpe 110 Class Notes
28/69
28
hole path
P+ P+
N
VSG
VSD
P-type Metal Oxide Semiconductor Field Effect Transistor (PMOSFET)
h
h
h
metal gate
gate oxidesource drain
VBS
bulk
-
8/9/2019 Cmpe 110 Class Notes
29/69
29
B. MOSFET CHARACTERISTICS
(i) NMOSFET
ID
D
S
G
ID
VGS
VDSVDsat=VGS-VT
Saturation
Quadratic
Linear
( )2
2
n ox n DS D GS Tn DS
C W V I V V V
L
=
( )n ox n
D GS Tn DSC W
I V V V L
linear region for small VDS
( )2
2
n ox n D GS Tn
C W I V V
L
= DS Dsat GS Tn DSfor V V = V - V saturation region for large V
(ii) PMOSFET
I D
D
S
G
I D
VSG
VSDVSDsat=VSG - VT
( )2
2 p ox p SD
D SG Tp SDC W V I V V V L
=
( ) p ox p
D SG Tp SDC W
I V V V L
linear region for small VSD
( )2
2
p ox p D SG Tp
C W I V V
L
= SD SDsat GS Tp SDfor V V = V -V saturation region for large V
-
8/9/2019 Cmpe 110 Class Notes
30/69
30
C. LARGE SIGNAL EQUIVALENT CIRCUIT OF MOSFETS
(i) NMOSFET LARGE SIGNAL EQUIVALENT CIRCUIT
For small DSV
Rn
VDS
ID
( )
DS
D
V 1
IGS Tn
nn ox n
RC W
V VL
= =
( )n
1where K
GS Tn
n ox nn
n
C WR
K V V L
=
For large DSV
( )2
2 Dsat GS Tn
nK I V V =
GS DD Tn DDIf V =V & V 0.2V then:
DSAT DD
2n
1& I = 0.32K V
0.8DD
n
n
RK V
=
(ii) PMOSFET LARGE SIGNAL EQUIVALENT CIRCUIT
For small SDV
Rp
VSD
ID
( )p
1where K =
SG Tp
p ox pp
p
C WR
LK V V
=
For large SDV
( )2
2 DSAT SG Tp
pK I V V =
-
8/9/2019 Cmpe 110 Class Notes
31/69
31
D. Complementary MOS (CMOS) Inverter Static Characteristics
VDDVDD - vin
G
S
D
D
Svin
+
-
vout
ID
G
0
vin(t)
t
VDD
(i) For Small values of vin (t)
ID
VGSn= vin
vout = VDSn
ID
VSGp= VDD-vin
VDD - vout= VSDn
Overlapping these two curves on top of each other yields:vout = VDSn = VDD when VSDp = 0
vout = 0 when VSDp = VDD
1
VGSn= vin
voutVDD0
ID
VGSp = VDD - vin
At 1 pfet is in linear regionnfet is in saturation region
-
8/9/2019 Cmpe 110 Class Notes
32/69
32
IDSAT
vout
Rp
( ) ( )out DD DSAT SGp Tp DD in Tpp p
p p
1v = V - R I where R =
K V -V V -v -V
1=
( ) ( )2 2
2 2 DSAT GSn Tn in Tn
n nK K I V V v V = =
( )( )
2
2
in Tn
out DD
DD in Tp
n
p
v VKv VK V v V
=
(ii) For some intermediate value of vin(t)
vout
ID
2VSGp= VDD - vin VGSn= vin
At2
both pfet & nfet are in saturation region
IDSSAT
voutISDSAT
-
8/9/2019 Cmpe 110 Class Notes
33/69
33
( )
( )
2
2
2
2
SDSAT SGp Tp
DSSAT GSn Tn
p
n
K I V V
K I V V
=
=
( )( )
2
p2
n
K, givesK
GSn Tn
SDSAT DSSAT
SGp Tp
V V But I I V V
= =
SubstitutingSGp DD in
and V = V - vGSn in
V v=
( )
( )p
n
K
K
in Tn
DD in Tp
v V
V v V
=
p nWe had K = and K = p ox p n ox nC W C W
L L
in Tn
DD in Tp
p p
n n
W v V
W V v V
=
Assume that 2n p &T Tn Tp
V V V= =
p
2
p
p
W
2
in T
DD in T
p
n n
v V WR
W V v V W
= = =
( ) ( ) ( )yields 1 1in T DD in T in T DDv V R V v V v R V R RV = + = +
( )1
DD T T
in
R V V V v
R
+=
+
if 2 R=12
DD
inp n
VW W v= =
if R=0.71 0.41in DD
p nW W v V =
(iii) For large values of vin(t)
vout0
ID
3 VSGp= VDD-vin
VGSn= vin
-
8/9/2019 Cmpe 110 Class Notes
34/69
34
At 3 nfet is in linear region
pfet is in saturation region
vout
Rn
ISDSAT
out SDSATnv =R I
Where,( ) ( )
n
n n
1 1R =
K KGSn Tn in T
V V v V =
( ) ( )2 2
2 2SDSAT SGp Tp DD in Tp
p pK K
I V V V v V = =
( )( )
out
2
n
v =2K
DD in Tp
in Tn
p V v VK
v V
Plotting vout in terms of vin yields:
vout
vinVDD/2 VDD
BELL CURVE
For vin < VDD/2
( )
( )out2
nKv =
2
in Tn
DD
DD in Tpp
v VV
K V v V
For vin > VDD/2
( )
( )out
2
nv = 2K
DD in Tp
in Tn
p V v VK
v V
-
8/9/2019 Cmpe 110 Class Notes
35/69
35
2
13
ID
VSGp
VSGp
VSGp
VGSn
VGSn
VGSn
VDD vout As vin approaches from 0 to VDD then the quiescent point (operating point) of the the
inverter transverses the DASHED ARC from 1 to 3 through 2 in ID vs. vout curve.As vin approaches from VDD to 0, the quiescent point of the inverter follows the
DASHED ARC from 3 to 1 .
Now, lets plot the BELL CURVE for different values ofp
n
W
W:
p
n
W
W
inv at 2
1 0.41 VDD
2 0.5 VDD
3 0.55 VDD
4 0.58 VDD
6 0.63 VDD
0.4
1V
DD
0.5V
DD
0.63
VDD
Observe the following:
Whenp
n
W
W= 1 (strong nfet weak pfet) small increases in v in quickly turns the nfet
on, and vout starts decreasing towards 0.
-
8/9/2019 Cmpe 110 Class Notes
36/69
36
Whenp
n
W
W= 6 (strong pfet weak nfet) large increases in v in cannot turn on the nfet,
vout delays to decrease towards 0.
E. NOISE MARGIN OF THE INVERTER
Noise margin of the inverter is defined as the value of the input voltage, v in, at
1outdv
dt= .
Thus, from the BELL curve:
Wp/Wn=2
vinVDDVIHVIL
NML NMH
1ou td v
d t=
1outdv
dt=
Wp/Wn=1
vou t
vinVDDVIHVIL
NML NMH
1ou td v
d t=
1
outdv
dt =
Positive glitch Negative glitch0V
VDD
t t
-
8/9/2019 Cmpe 110 Class Notes
37/69
37
When nfet is stronger with respect to pfet (Wp/Wn=1) in an inverter, then small input
voltages at vin can easily turn on the nfet. Therefore, the inverter with Wp/Wn=1 has low
noise margin or noise immunity for positive glitches at its input. But, the same inverterexhibits high noise immunity for negative glitches at its input.
Wp/Wn=6
vou t
vinVDDVIHVIL
NML NMH
1ou td v
d t=
1outdv
dt=
Positive glitch Negative glitch0V
VDD
t
For an inverter with Wp/Wn=6, the inverter exhibits high noise immunity for positive
glitches & low noise immunity for negative glitches.
F. CMOS Inverter Dynamic Characteristics
If vin is changed from 0 to VDD without any transition time (rise time = 0 sec), the pfet is
turned OFF, and nfet is put in the linear region and shows resistive characteristics.
vout
Rn
pfet is OFF
When vin = VDD( )
1
DD Tn
n
n
RK V V
-
8/9/2019 Cmpe 110 Class Notes
38/69
38
Assume 0.2Tn DD
V V 1
0.8DD
n
n
RK V
Now, if vin is switched back from VDD to 0 without any transition time, this time nfet is
turned off and pfet is put in the linear region and shows resistive characteristics.
vout
Rp
nfet is OFF
when vin=0 ( )1
DD Tp
p
pR K V V
Assume 0.2Tp DD
V V and1
0.8DD
p
p
RK V
This analysis aids to derive the propagation delay of the inverter with a load capacitor,
CL, at its output.
VDDVDD - vin
G
S
D
D
Svin
+
-
vout
ID
G
CL
When vin changes from 0 to VDD, then nfet turns ON and pfet turns OFF.
-
8/9/2019 Cmpe 110 Class Notes
39/69
39
Vout(0) = VDD
Rn CL
out DD
n L
t
R Cv V e
=
vin,vout
VDD
vin(t) is a step function
VDD/2 TpL
TpL
0
vout(t)
t
2
pL
DD L
out DD
n
TV R C
v V e
= =
ln2 =0.69 pL L L
n nT R C R C = (low-going propagation delay)
When vin goes from VDD to 0, then nfet is turned OFF and pfet is turned ON.
Rp
CL
Vout(0) = 0
(1 )Lout DD
t
RpCv V e
=
-
8/9/2019 Cmpe 110 Class Notes
40/69
40
vin,vout
VDD/2
TpH
0
vout(t)
t
vin(t)
0.69 pH L
pT R C= (high-going propagation delay)
Example: Compare TPL & TPH for 1, 2,4p
n
W
W
= (assume VT = VTn = VTp= 0.2VDD)
Solution:1 1
( ) 0.8 DD T DD
n
n n
RK V V V K
= =
1
0.8DD
p
p
RV K
=
Where,
ox
ox
n n
n
p p
p
C WK
L
C WK
L
=
=
0.86 0.860.69
2
0.86 0.86
L L
PL L
DD DD ox
L L
PH
DD DD ox
n
n p n
p p p
C CT R C L
V K V C W
C CT L
V K V C W
= = =
= =
Let;
0.86
2
L
PL
DD ox
PH
p n
p
C M M L T
V C W
M
T W
= =
=
For
1p
n
W
W= (strong nfet, weak pfet)
2PL
n
MT
W = ,
PH
n
MT
W=
PLT =
2
PHT
2p
n
W
W= (equal nfet and pfet)
2PL
n
MT
W = ,
2PH
n
MT
W=
PLT =
PHT
-
8/9/2019 Cmpe 110 Class Notes
41/69
41
4p
n
W
W= (weak nfet, strong pfet)
2PL
n
MT
W = ,
4PH
n
MT
W=
PLT = 2
PHT
FANOUT
N
Cin
Fanout of a gate (inverter in this case) is the number of identical gates at the output of this
gate.
Thus = CL
=N Cin
where N = fanout.
Therefore,
0.69 0.69
0.69 0.69
PL L
PH L
n n in
p p in
T R C N R C
T R C N R C
= =
= =
0.69PH p LT R C=
0.69PL n LT R C=
Tp
CL
IMPORTANT OBSERVATION
Tp changes linearly with CL. That means more output capacitance (fan-out) linearly
produces propagation delay.
Note that, Tp= 0 when CL =0 F. However, this is impossible because every inverter has anintrinsic load capacitor due to source/drain contact capacitance even though the externalload capacitor, CL, may not exist. Therefore, if one assumes CL as a physical capacitance
due to gate fanout or wiring, the practical Tp vs CL will be as follows.
-
8/9/2019 Cmpe 110 Class Notes
42/69
42
Tp
CL
TpL
TpH
TpL0
TpH0
G. Rise Time & Fall Time
vin,vout
0
vout
(t)=VDD
(1-e-t/RpCL)
t
vin(t)
VDD
0.9VDD
0.1VDD
t1 t2T
Rise
10.1
out DDt tv V
==
DDV=
1
1 Lpt
R Ce
1
0.1 1 Lpt
R Ce
=
1ln 0.9= 0.1
L Lp pt R C R C =
-
8/9/2019 Cmpe 110 Class Notes
43/69
43
20.9
out DDt tv V
==
DDV=
2
1 Lpt
R Ce
2
0.9 1 Lp
t
R Ce
=
2ln 0.1= 2.3
L Lp pt R C R C =
RISE2 1T = t - t = 2.2
LpR C
vin,v
out
VDD
v in(t)
0
vout(t)=VDD(e-t/RnCL)
t
0.9VDD
t1T
FALL
t2
0.1VDD
10.9
out DDt tv V
= = DDV=
1
Ln
t
R Ce
1ln 0.9= 0.1
L Ln nt R C R C =
20.1
out DDt tv V
==
DDV=
2
Ln
t
R Ce
2ln 0.1= 2.3
L Ln nt R C R C =
FALLT =2.2
LnR C
Example: Compare TRISE, TFALL for 1p
n
W
W= , 2 and 4. Assume 0.2T DDV V
-
8/9/2019 Cmpe 110 Class Notes
44/69
44
Solution:1 1
&0.8 0.8
DD DD
n p
n p
R RV K V K
= =
2ox ox
ox
n n p nn
p pp
C W C W K
L L
C WK
L
= =
=
1 1 1 1
0.8 2 0.8 DD ox DD ox
n p
n n p p
R RV C W V C W
= =
Let P0.8
DD oxp
L
V Cthen
P P&
2n p
n p
R RW W
= =
For 1p
n
W
W
= thenRISE L FALL L
1 1T =(2.2 C P) T =(2.2 C P)
2n nand
W W
therefore FALLRISE
TT =
2
For 2p
n
W
W= then
RISE L FALL L
1 1T =(2.2 C P) T =(2.2 C P)
2 2n nand
W W
thereforeRISE FALL
T = T
For 4p
n
W
W= then
RISE L FALL L
1 1T =(2.2 C P) T =(2.2 C P)
4 2n nand
W W
thereforeRISE FALL
2T = T
H. Power Consumption
vout
CLi (t )
0
1P= ( ) ( )
Tout
T
i t v t dt power spent to charge CL.
out
L
dvi C
dt=
Then,
-
8/9/2019 Cmpe 110 Class Notes
45/69
45
1P=
T
out
L
dvC
dt0
( )out
T
v t dt
2 2
DD
0
V
2 2
DD L out L
VC v C
T T
= =
Therefore,
Power changes LINEARLY with CL and QUADRATICALY with VDD.
If we have a periodic input waveform:
VDD
0 Tperiod
vin
t
1
Tperiod
2
period 0
1P =
T
2
L out out C v dv
2
Tperiod
period Tperiod
2
1P =
T2
L out out C v dv
2
2DD
DD1 2
period
V 1P = P + P = V
T 2 2
L
L
CC f=
Therefore power changes LINEARLY with frequency.
VDD
0 Tperiod/2
vout
tTperiod/2
P1 P2
-
8/9/2019 Cmpe 110 Class Notes
46/69
46
I. TECHNOLOGY SCALING
Example: Compare 0.5 technology with tox=100A , 3.3V @ 100 MHzwith 0.1 technology with tox=50A , 1V @ 5 GHz.
Keepp
n
WK
W= the same in both technologies.
Solution:
( ) ( 1)
( 1)
L ox ox
ox ox
ox
ox ox
n p n
L n
C C W W L C K W L
KC C W L
t t
= + = +
+= =
For 0.10.1 0
( 1)(0.1 )
50
oxnL u
KC W
A
=
+=
0.5 0.5 0( 1)
5 (0.5 )100
oxnL u
KC W
A
=
+=
2
L=0.1u 0.1 0.10.1
1P =
2DD L u L uL uC V f= ==
2
0
1 ( 1)(0.1 ) (1V) (5000 )
2 50
oxn
KW MHz
A
+=
L=0.5u
2
0
1 ( 1)P 5 (0.5 ) (3.3V) (100 )
2 100
oxn
KW MHz
A
+=
L=0.1u
L=0.5u
20
0
P 100 1 0.1 1 50000.368
P 50 5 0.5 3.3 100
A V MHz
A V MHz
= =
Therefore, there is room to increase VDD.
-
8/9/2019 Cmpe 110 Class Notes
47/69
47
CHAPTER III. CMOS LOGIC
A. CMOS GATE STRUCTURE
Complementary
pfet tree
nfet tree
in1
ink
out
The nfet tree is formed between the output & ground to produce a logic function at the
output. The pfet tree is formed between VDD & output to replicate the complementary
version of the nfet tree.In a pfet tree, parallel nfet interconnects are converted into serial pfet interconnects and
serial nfet interconnects are converted into parallel pfet interconnects.
(i) 2-Input NAND Gate
A B
A
B
outNAND
A B outNAND Comments
0 0 1 pfetA on, pfetB on
0 1 1 pfetA on only
1 0 1 pfetA on only
1 1 0 nfetA on, nfetB on
-
8/9/2019 Cmpe 110 Class Notes
48/69
48
(ii) 2-Input NOR Gate
A
B
A B
outNOR
A B outNOR Comments
0 0 1 pfetA on, pfetB on0 1 0 nfetA on only
1 0 0 nfetA on only
1 1 0 nfetA on, nfetB on
B. Building Complex Function Gates
Example: out= ( )D A B C + +
Form nfet tree first:
A D
B C
out
-
8/9/2019 Cmpe 110 Class Notes
49/69
49
Form pfet tree second:
B
C
A
D
out
Combine nfet & pfet Trees
B
C
A
D
A D
B C
out
Example:
0
1
out
EN
A
B
. .out A EN B EN= +
-
8/9/2019 Cmpe 110 Class Notes
50/69
50
First obtain . .out AEN B EN= +
A B
EN
out
EN
A
B EN
out
EN
nfet-tree pfet-tree
Now combine nfet tree, pfet tree &inverters to form out.
A
B EN
A B
EN
out
EN
EN
-
8/9/2019 Cmpe 110 Class Notes
51/69
51
C. Fundamentals of Transistor Sizing
Transistor sizing is achieved by determining the maximum charge & discharge paths.
(i) Inverter
in
charge path
discharge path
wp
wn CL
n p
n p
P PR = and R =
2W W
PH L
PL L
p
n
T =0.69 R C (rise delay)
T =0.69 R C (fall delay)
If we want TPH=TPL (relative)
Then,
L Lp n p n0.69 R C =0.69 R C R = R
Or p nW =2W
(ii) 2- Input NAND Gate
Wp
Wn
B
Wndischarge pat h
A
A
B
charge path
CL
outWp
-
8/9/2019 Cmpe 110 Class Notes
52/69
52
From critical charge path:
PH L
PL L
peq
neq
T = 0.69 C R (rise delay)
T = 0.69 C R (fall delay)
peq p
p
PR = R =
W
neq n n
n n
P PR = R + R = 2
2W W=
(i) If we wantPH PL
T = T peq neqR = R
p n
p n
P PW = W
W W=
Thus:
Wn
Wn
B
Wn
A
A
B
CL
outWn
(ii) If we wantPH PL
T =2T peq neqR =2R
np
p n
P P W2 W =
W W 2=
-
8/9/2019 Cmpe 110 Class Notes
53/69
53
(iii) 3-Input NAND Gate
Wp
CL
A B
A
B
out
charge path
discharge pat h
C
C
Wp Wp
Wn
Wn
Wn
PH L
PL L
peq
neq
T =0.69 C R (rise delay)
T =0.69 C R (fall delay)
peq p
p
PR = R =
W
neq n n n
n
PR = R + R + R = 3
2W
Therefore, if we wantPH PL
T = T peq neqR = Rp n
P 3 P
W 2 W =
p n2
W = W3
(iv) 2- Input NOR Gate
A
B
Wp
Wp
A B
Wn Wn
CL
out
charge path
discharge pat h
-
8/9/2019 Cmpe 110 Class Notes
54/69
54
PH L
PL L
peq
neq
T = 0.69 C R (rise delay)
T = 0.69 C R (fall delay)
peq p pp
2P
R = R + R = W
neq n
n
PR = R =
2W
PH PLT = T peq neqR = R
p n
2P P
W 2W=
p nW = 4W
(v) ( )out D A B C = + +
-
8/9/2019 Cmpe 110 Class Notes
55/69
55
PH L
PL L
peq
neq
T = 0.69 C R (rise delay)
T = 0.69 C R (fall delay)
peq p p p p
p
3PR = R + R + R = 3R =
W
neq n n nR = R + R = 2R = 2P
2 nn
P
WW=
If we wantPH PL
T = T peq neqR = R3 P
p
P
W=
n
W
p nW =3W
To find Wp2, Wn2 and Wn3 :
p2 p
p p2 p
P P 2PR = 2R = 2
W W W
=
pp2 n
W 3W W
2 2= =
n2 nR = R
n2 nW = W
n3 n nR = R + R = 2P
2 n n3 nn
P P P
W 2W WW= =
nn3
WW
2=
Therefore, all the other charge and discharge paths will be equal to the critical charge and
discharge paths, respectively.
-
8/9/2019 Cmpe 110 Class Notes
56/69
56
D. MORE ACCURATE DELAY CALCULATION, ELMORE DELAY
When we were calculating TpH & TpF earlier, we did not take the intrinsic source/draincapacitances in the delay calculation. Elmore delay calculation considers these intrinsic
capacitances in the following manner:
nfet tree:
M1
M2
M3
MN
C2
C3
CN
CL+C1
out
( )
( )
( )
2
3
1 2 31
2 3 4
3 4 5
0.69{( ) ..........
..........
.........
...........
}
pL
N
n n n nN L
n n n nN
n n n nN
nN
T C C R R R R
C R R R R
C R R R R
C R
= + + + +
+ + + +
+ + + +
+
+
-
8/9/2019 Cmpe 110 Class Notes
57/69
57
pfet tree:
N2C1
C2
C(K-1)
out
N1
N3
NK
CL+CK
C0
( )
( )
( )
0
1 1
1 2 2
1 2 3 3
1 2
0.69{0.
.........
....... ( )}
pH
p
p p
p p p
p p pk L K
T CR C
R R C
R R R C
R R R C C
=+
+ +
+ + +
+
+ + + + +
-
8/9/2019 Cmpe 110 Class Notes
58/69
58
Example: Determine Elmore delays for 2 NAND with intrinsic S/D capacitance, Ci.Let Ci be the capacitance per transistor width.
For practical purposes, each transistor has a separate Ci at its source and drain junctions.
B
discharge path
A
A
B
charge path
CL
out
+(2Wp+Wn)Ci
2WnCi
( )
0.69( (2 ))
0.69 ( (2 )) 2
pH L
pL L i
pi p n
n n ni p n n
T C C W W R
T C C W W R R CW R
= + +
= + + + +
-
8/9/2019 Cmpe 110 Class Notes
59/69
59
Example: Determine Elmore delays for 4 NAND with intrinsic S/D cap=Ci
(4Wp+W
n)Ci
A B
A
B
out
C
C D
CL
D
2WnCi
2WnCi
2WnCi
0.69( (4 ) )
pH Lp p n i
T C W W C R= + +
( )
( )
( )
0.69{( (4 ) )
2
2
2 }
pL L
i
i
i
n n n n p n i
n n nn
n nn
nn
T C W W C R R R R
W C R R R
W C R R
W C R
= + + + + +
+ + +
+ +
+
0.69 ( 16( ) ) pL L in p nT R C W W C = + +
If we want:
( (4 ) ) ( 16( ) ) pH pL L L i
p n p n i p nT T C W W C R C W W C R= + + = + +
p
p
PR
W= ,
2n
n
PR
W= and nW W=
(8 ) (8 )2 128 ( )
32
i L i L i L i
p
i
WC C WC C WC C WC W
C
+ + + + +=
If 0 as expected.2
ni p WC W =
-
8/9/2019 Cmpe 110 Class Notes
60/69
60
Example: Determine Elmore delays for 2 NOR with intrinsic S/D cap=Ci.
A
B
A B
Wn
CL+ (Wp+2Wn)Ci
out
charge path
discharge path
Wp
Wn
Wp
2WpCi
( )0.69 2 [ ( 2 ) ]
0.69[ ( 2 ) ]
pH i L
pL L
p p p p p n i
n p n i
T R W C R R C W W C
T C W W C R
= + + + + = + +
-
8/9/2019 Cmpe 110 Class Notes
61/69
61
Example: Determine Elmore delays for Out = ( )D A B C + +
B
C
A
D
A D
B C
out
CL+Ci(2W
n+W
p)
Wp
Wn
2WpCi
3WpCi
3WnCi
Wp
Wp
Wp
Wn
WnWn
( ) ( )
( )
0.69 2 3 ( (2 ))
0.69 ( (2 )) 3
pH i i
pL i
p p p p p p p p L i n p
n n n n L i n p
T R W C R R W C R R R C C W W
T R R C C W W R W C
= + + + + + + +
= + + + +
-
8/9/2019 Cmpe 110 Class Notes
62/69
62
E. INTERCONNECT DESIGN STRATEGIES TO REDUCE ELMOREDELAYS
Consider ( )out A B C D= + + . There are 2 ways to implement this:
CL+(2Wp+Wn)Ci
4WnCi
out
D
A B C
A
B
C
D
Implementation #1
CL+(2Wp+3Wn)Ci
4WnCi
out
D
A B C
A
B
C
D
Implementation #2
{ }1 0.69 [ (2 ) ]( ) 4n n nPL L p n i n iT C W W C R R W C R= + + + +
{ }2 0.69 [ (2 3 ) ]( ) 4n n nPL L p n i n iT C W W C R R W C R= + + + +
Therefore, TPL1 < TPL2. Therefore, choose the implementation #1
-
8/9/2019 Cmpe 110 Class Notes
63/69
63
CHAPTER IV. PASS-TRANSISTOR LOGIC
A. ISSUES WITH PASS TRANSISTOR LOGIC
(i) Problem with nfet
VDD
CL
VG = VDD
VGSv
out(0) = 0
I D
ID
VDSV
TV
DD/2 V
DD
VGS = VDD/2
VGS = VDD
VGS = VT
1
2
3
vout
= VDD
-VT
vout= VDD/2 vout= 0
When VG = VDD and VD = VDD are applied to the nfet in the above circuit, the initialvoltage across the load capacitor, CL, is zero. Therefore, initially VGS = VDD and VDS =
VDD. This condition induces a maximum current through the nfet (case 1). As this
current charges the output capacitor, CL, and the output voltage rises, the current through
the nfet declines steadily (case 2). When vout = VDD - VT, the current through the nfetreaches sub-threshold level, which is practically zero (case 3).
Therefore, a logic 1 is applied to the drain (input) of an nfet, one can never reach the full
VDD at the source (output); the maximum attainable value is always VDD - VT.
Final form:
VDD
CL
VG = VDD
VTvout = VDD - VT
I D = 0
-
8/9/2019 Cmpe 110 Class Notes
64/69
64
Any problem if we apply ground instead of VDD?
CL
VG = VDDVGS
vout
= VDD
I D
I D
VDSV
TV
DD/2 V
DD
VGS = VDD
12
3
vout
= 0 vout= VDD/2 vout= VDD
With the above bias across the nfet, output capacitor is discharged completely, and voutreaches 0 since VGS = VDD at all times. Therefore, if a logic 0 is applied to the source
(input) of an nfet, a logic zero is obtained at the drain (output).
(B) Problem with pfet
CL
VG = 0
VSGvout(0) = VDD
I D
ID
VSD
VT VDD/2 VDD
VSG
= VDD
/2
VSG = VDD
VSG = VT
1
2
3
vout= VT vout= VDD/2 vout= VDD
When VG = 0 and vout(0) = VDD are applied to the pfet in the above circuit, the initial VSG
= VDD and VSD = VDD. This condition induces a maximum current through the pfet (case1). As this current discharges the output capacitor, CL, and the output voltage decreases,
the current through the nfet declines steadily (case 2). When vout = VT, the currentthrough the pfet reaches sub-threshold level, which is practically zero (case 3).Therefore, a logic 0 is applied to the drain (input) of a pfet, one can never reach 0 at the
source (output); the minimum attainable value is always VT.
-
8/9/2019 Cmpe 110 Class Notes
65/69
65
Any problem if we apply VDD instead of 0 ?
CL
VG = 0VSG
vout (0) = 0
I D
I D
VSD
0 VDD/2 VDD
VSG = VDD
1
2 3
vout
= 0vout
= VDD
/2vout= VDD
With the above bias across the pfet, output capacitor gets charged completely, and voutreaches VDD since VSG = VDD at all times. Therefore, if a logic 1 is applied to the source(input) of a pfet, a logic 1 is obtained at the drain (output).
CONCLUSIONS:
(1)
VDD
CL
VDD
VDD - VT
ON
CL
VDD
ON
0
result: nfet transmits logic 0 OK when it is ON.
(2)
CL
VDD
ON
0
CL
VDD
ON
0
result: pfet transmits logic 1 OK when it is ON.
Because of the level shifting problem in nfet and pfet for VDD and 0, respectively,transmission gate is developed.
-
8/9/2019 Cmpe 110 Class Notes
66/69
66
B. TRANSMISSION GATES
The transmission gate is the parallel combination of nfet and pfet with an inverter.
A
B
out =AB
A
B
out =AB
Example: out A B AB AB= = +
A
B
A B
B
A
A B
out = A B + A B
A
B
A
B
out = A B + A B
What about out ABC= ?
-
8/9/2019 Cmpe 110 Class Notes
67/69
67
A
B
A B
C
out = A B C
Even though one gets a functionally correct output, one of the biggest drawbacks of serialtransmission gate is that it generates a slow node at the output due to high series
resistance. The charge path:
The change path:
Wpeq
Rp
Rp
Rn
Rn
CL
vout
Where,
p
p
PR
W=
2n
n
PR
W=
2
n p
n p p n
R R P
R R W W =
+ +
1 22.2 ( 2 ) 2.2 ( )
2
p n
RISEslow L peq L
p n peq p n
R RT C R C P
R R W W W = + = +
+ +
The discharge path:
Wneq
Rp Rp
Rn
Rn
CL
vout
1 2
2.2 ( )2 2
FALLslow L
neq p n
T C PW W W
= ++
-
8/9/2019 Cmpe 110 Class Notes
68/69
68
Therefore, more serial transmission gate induces more1
2p n
W W+- term, which results in
generating slower output node at vout.
To prevent the slow node formation signals need to be buffered by going to the gate of
the next transistor rather than its drain (or source):
B
A BA
Cout = A B C
Wpeq
Rp
Rn
Cinv+
Cnox
vab
Wpeq
Rp
Rn
CL
vout
1 1
2.2 ( )( )2
RISEab inv nox RISEslow
peq p n
T P C C T W W W
= + +