final fpga

8/15/2019 Final FPGA

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FPGA(Field Programmable Gate

Array)

Presenter

Abu Shohel Ahmed

Md. Kamrul Abedin TarafderDebashis roy


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HistoryProgrammable Read Only Memory (PROM)

address line as input

data line as output

Problem:

dont require all the logic combination in input.

Programmable Logic Array (PLA)- Programmable AND plane followed by

programmable or wired OR plane.- Sum of product form- Two level programming adds delay (problem)


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Next -PAL ( Programmable array logic)

- Programmable AND plane and fixed OR

plane.- All these PLA and PAL are Simple

programmable logic devices.

- Logic plane structure grows rapidly withnumber of inputs( problem)


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NextTo mitigate the problem

Complex programmable logic devices

(CPLD)-programmably interconnect multiple

SPLDs.

- Extending to higher density difficult(problem)

- Less flexibility (problem)


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Comparison


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What is FPGA?

A field programmable gate array

(FPGA) is a semiconductor device

containing programmable logiccomponents and programmable

interconnects and programmable I/O

blocks.


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FPGA


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Logic BlocksPurpose: implement combinational and

sequential logic functions.

Logic blocks consists of

- Transistor pairs Basic small gates such as two-input NANDs or

exclusive-OR s.

Multiplexers Look up tables( LUT) Wide fanin AND-OR structure.


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Logic Block ArchitectureGranularity:

The number of boolean function a logic block can

implement, the number of gates, transistors,total normalized area, number of inputs and

outputs.

According to granularity Two types of Blocks

d. Fine Grain Logic Blocks

e. Coarse Grain Logic Blocks


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Fine Grain The Cross Point

FPGA

1. Transistors are

interconnected.

2. Logic block is

implemented

using transistor

pair tiles.


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Fine GrainAdvantage:

1. Blocks are fully utilized.

Disadvantage:

Require large numbers of wire segments

and programmable switches. So it is

costly in delay and area size.


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Coarse Grain Logic BlocksMany types exists according to

implementations

-Multiplexer Based and Look-up-TableBased are most common

The Xilinx Logic Block:

A SRAM function as a LUT.

Address line of SRAM as input

Output of SRAM gives the logic output


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Xilinx Logic BlockAdvantage: High

functionality

any function of kinputs

Dis Adv: unacceptably

large


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Switch Box Whenever a vertical and

a horizontal channelintersect there is aswitch box.

In this architecture,when a wire enters aswitch box, there arethree programmable

switches that allow it toconnect to three otherwires in adjacentchannel segments.


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Programming technologies

Used in switchesb. SRAM programming

technology

Use Static RAM cells tocontrol pass gates or

multiplexers.1= closed switch

connection

0= open

For mux, SRAMdetermines the muxinput selectionprocess.


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Programming Tech Antifuse

2 terminal device with an un programmed

state present very high resistance.By applying high voltage create a low

resistance link.

Adv

5. Small size

6. Low series resistance.


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Programming Tech

Floating gateprogramming Tech

Same as electrically

erasable process in

EPROMSwitch is disable by

injecting charge on the

gate 2 using high

voltage between gate1

and drain.

The charge is removed by

UV light


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summary


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Effects of Granularity on FPGA

Density and Performance

Tradeoff

Granularity increase -> Blocks less

More Functional Blocks-> more area

Area is normally measured by total number

of bits needed to implement the design.So look the example


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Example


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Experimental Results

A 4-input 1-output lookup table yields the

minimum total area

Best k is determined by ratio of memorybit area to the fixed overhead area.


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Routing Architectures

The wayprogrammableswitches andwiring segmentsare positioned for

interconnections.

Core Elements:

c. Wire segment

d. Track

e. Routing Channel

f. Connection Blockg. Switch Block


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Why better ?

-FPGA programmed using electricallyprogrammable switches

-Routing architectures are complex.-Logic is implemented using multiple levels

of lower fanin gates.

-Shorter time to market

-Ability to re-program in the field to fix bugs

-Lower non-recurring engineering costs


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FPGA Disadvantage

FPGAs are generally slower than their

application-specific integrated circuit

(ASIC) Can't handle as complex a design, and

draw more power.


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FPGA Design and Programming

To define the behavior of the FPGA the user provides ahardware description language (HDL) or a schematicdesign.

Then, using an electronic design automation tool, atechnology-mapped net list is generated.

The netlist can then be fitted to the actual FPGA architectureusing a process called place-and-route.

The user will validate the map, place and route results via

timing analysis, simulation, and other verificationmethodologies.

Once the design and validation process is complete, thebinary file generated used to configure the FPGA.


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Application

1. Reconfigurable computing.

2. Applications of FPGAs include DSP,

software-defined radio.3. The inherent parallelism of the logic

resources on the FPGA allows for

considerable compute throughput.


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FPGA Optimization

DAG map: Graph based FPGA mapping for delay optimization DAG-Map reduces both the network depth and the number of

lookup-tables.

Problem Formulation: A Boolean network can be represented as a directed acyclic

graph (DAG) where each node represents a logic gate andthere is a directed edge (i,j) if the output of gate iis an input ofgatej.

A primary input (PI) node has no incoming edge and a primary

output (PO) node has no outgoing edge. We use input(v) to denote the set of nodes which supply

inputs to gate


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rs ep: rans or m ngArbitr ary Netw orks into T wo-Input Ne twor ks algorithm decompose-multi-input-gate (DMIG)

let V= input(v) = {u1 , u2 , ..., um};

while |V|> 2 dolet uiand ujbe the two nodes ofV with smallest levels;

introduce a new nodex;input(x) = {ui, uj};

level(x) = max(level(ui), level(uj)) + 1;

V= (V- {ui, uj}) {x}

end-while;

Connect the only two nodes left in Vto vas its inputs;Return the binary tree T(v) rooted at v;

end-algorithm.


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Transformin g Ar bitr aryNe twor ks in to T wo-Inp utNe twor ks


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2nd S tep: T echno logy Mappingfor Dela y Min imiz ation

Our algorithm consists of two steps.

- We first label the network to

determine the level of each node in thefinal mapping solution.

- We then generate the logically

equivalent network of K-LUTs.


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Continue

The first step assigns a label h (v) to eachnode vof the two-input network, with h (v)equal to the level of the K-LUT containing vin

the final mapping solution. Clearly, we want h (v) to be as small as

possible in order to achieve delayminimization.

We label the nodes in a topological orderstarting from the PI nodes.

The label of each PI node is zero.


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Continue..

If node vis not a PI node, letp be themaximum label of the nodes in input(v).

We use Np(v) to denote the set ofpredecessors ofvwith labelp.Then,

ifinput(Np(v) {v}) K,

we assign h (v) =p;

otherwise, we assign h (v) =p + 1.


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Continue

The second step generates K-LUTs in the mappingsolution.

Let L represent the set of outputs which are to beimplemented using K-LUTs.

Initially, L contains all the PO nodes. We process thenodes in L one by one.

For each node vin L, we remove vfrom L andgenerate a K-LUT v to implement the function ofgate vsuch thatinput(v) = input(Nh(v) (v)).


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Continue

Then, we update the set L to be

L input(v). The second step ends when L consists of

only PI nodes in the original network.

Clearly, we obtain a network of K-LUTs that

is logically equivalent to the original network.


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DAG-Map Algorithm


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Applying DAG-Map Algorithm


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Mapping by DAG-Map (3 levels)


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Gate Decomposition

If node vis a simple gate of multipleinputs in the mapping solution, for anytwo of its inputs uiand uj, ifuiand ujaresingle fanout nodes, we can decomposevinto two nodes Vijand vsuch that vis

of the same type as vand vijis of the

same type as vin non-negated form, andinput(vij) = {ui, uj} and input(v) = input(v) U {vij} - {ui, uj}


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Example of Gate decomposition


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Predecessor Packing

For each node v, we examine all of its input

nodes.

If | input(v) U input(ui) | Kfor some input

node ui, and uihas only a single fanout, then

vand uiare merged into a single K-LUT. In

this case we also say that node uiand vare

mergeable, and call vthe base of the merge.This operation reduces the number of K-LUTs

by one.


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Example of Predecessor

Packing


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THANKS

final fpga

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