Fast Dead-Time Locked Loops for a High-Efficiency Microprocessor-Load ZVS-QSW DC/DC Converter

Shuo Chen*, Olivier Trescases and Wai Tung Ng**

Abstract - This paper presents the design of integrated Dead-Time-Locked Loops (DTLL) for a fixed-frequency Zero-Voltage-Switching Quasi-Square-Wave (ZVS-QSW) buck converter. This is developed to address the challenges of DC/DC conversion for next-generation high-performance microprocessors. The DTLLs provide real-time accurate dead-time control with fast error rejection to realize ZVS, which minimizes switching loss, thus allows high switching frequency operation.

I. INTRODUCTION The next-generation microprocessors will require

point-of-load DC/DC switch-mode converter modules capable of providing tightly regulated sub-1V supply voltages, high currents up to several hundred Amps under extremely large load transients (di/dt of thousands of A/µs). The most popular solution for such applications is the multi-phase interleaved buck converter [1].

Stringent future demands on transient response and power density will push the switching frequency, fs, beyond several MHz. A higher fs allows wider control bandwidth, shorter modulation delay and reduced output inductance L, yielding higher current slew rate during load transients.

Research shows that interconnect parasitics between the Voltage Regulation Module (VRM) and microprocessor package are significant contributors to supply voltage fluctuations [1]. It will eventually be necessary to integrate power management chips, inductors and capacitors within the processor package. Such hybrid packaging required fs to be pushed to the multi-MHz range to allow passive component miniaturization.

However, increasing fs will incur higher losses, such as the gate-drive loss and, in particular, the switching losses in conventional hard-switched Buck converters:

Psw(conv)= Pturn-on+Pturn-off ∝ (CpVin2 + VinIout tr) fs (1)

where Pturn-on is due to charging the parasitic capacitances Cp at the junction of the power switches during their turn-on, and Pturn-off is due to the V-I overlapping during their turning-off. This is becoming more serious at higher fs, as bus voltages are migrating from 5V toward 12V to mitigate the losses on power delivery paths to the VRM.

Maintaining high efficiency at such a high fs will become a major challenge. The vicinity of processors is extremely noise-sensitive. Soft switching techniques can

minimize both switching losses and noise. Zero-voltage switching (ZVS) is ideal for low-voltage converters using power MOSFET devices, since capacitive loss can be eliminated through ZVS.

Section II introduces the ZVS Quasi-Square-Wave (ZVS-QSW) buck converter as a candidate for future VRM applications. A real-time analog dead-time control scheme is presented to realize ZVS under dynamic conditions. Finally, a silicon implementation is outlined in section III.

II. DESIGN OF THE ZVS-QSW CONVERTER

A. Zero-Voltage-Switching Quasi-Square-Wave Topology Reducing the output inductance L of a synchronous

buck converter beyond a critical value will result in discontinuous operation. However, continuous inductor current is achieved using bi-directional power switches [1], resulting in QSW operation [1] shown in Fig.1. The reversed inductor current prior to high-side turn-on can charge up the parasitic capacitance at node X to Vin in lossless resonance, thus Pturn-on is eliminated.

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Fig. 1. (a) A QSW buck converter and (b) its waveforms After the resonant transition, the inductor current is

carried by the body diode until the MOSFET turns on. The associated body-diode loss:

Pdiode ≈ (VD1iL(valley)Terr1+VD2iL(peak)Terr2) fs (2)

significantly reduces the converter efficiency at low output voltages, as verified through simulations, even with a Terr as low as 10ns per switching transition. Moreover, the QSW converter still suffers from turn-off switching loss Pturn-off on both switches. The body-diode

** The authors are with the Edward S. Rogers Sr. Dept. of Electrical and Computer Engineering, University of Toronto, ON M5S 3G4, Canada. {trescas, ngwt}@vrg.utoronto.ca.

* Shuo Chen is currently with Texas Instruments, Dallas, TX.

and turn-off losses are even higher than in the traditional buck converter due to the increased iL ripple (>2Io). These losses increase with fs, which is therefore limited to the hundred-kHz range in today’s QSW VRM modules. The high iL ripple increases the conduction losses in the power devices and non-ideal output filter. Fortunately, conductions losses generally do not scale with fs. In addition, the QSW topology has the lowest voltage stress among resonant-mode converters and therefore power devices having very low Rds(on) can be employed. Given that the body-diode and turn-off switching losses can be eliminated through ZVS, the QSW converter is a viable solution for high fs operation, despite the conduction-loss penalty.

A true ZVS-QSW buck converter (Fig. 2a) is formed by simply adding a small capacitor Cx at the junction of power switches (node X). Thus, the resonant transitions T1 and T2 in Fig. 2b can be lengthened, and the dead-time delays must be controlled in real time to realize the ideal resonant transitions. A true ZVS-QSW converter minimizes switching and body-diode losses and lowers the EMI due to reduced dvx/dt without increasing the power stage complexity.

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waveforms (Shaded areas indicate currents through switches)

B. Delay-Locked Loops for Real-Time Dead-Time Control The ideal dead time delays T1 and T2 in Fig. 2b are

determined by the resonant switching durations due to the charging and discharging of the Cr by the valley and peak inductor currents respectively. In turn, T1 and T2 are directly affected by the RMS output current. The ideal dead-times alternate between their respective maximum and minimum durations over the full load range.

A converter designed with fixed delays invariably suffers from body-diode conduction losses when the delay is longer than ideal (eq. 2) and capacitive switching losses through power switches when the delay is shorter

than ideal (eq. 3). These losses, which occur every switching cycle, are inevitable since fixed dead-times cannot be optimized for all load conditions.

∑Ediode ≈ VD1iL(valley)Terr1+VD2iL(peak)Terr2 (2)

Ecap=1/2Cr(∆vx)2 ≈1/2(iL(peak/valley)Terr)2/Cr ≤ 1/2CrVin2 (3)

The most obvious solution is an “adaptive” scheme in which the gate-drive is asserted after detecting the zero-voltage crossing [2]. This is unsuitable in high-frequency applications where comparator and gate-drive delays (>10ns) lead to severe positive dead-time errors.

An alternate approach proposed by [3] uses an opamp assisted V/I converter for the adaptive delay generator. The design assumes that the vx transition is linear and therefore the Vin/2 crossing occurs at the middle of the ideal dead-time. This is used to adjust the dead-time before the actual zero-voltage crossing. The main drawback is that the transition is not exactly linear and therefore external trimming is required to eliminate timing errors. The idea was further developed for an integrated synchronous rectifier [4] and again in a variable-frequency voltage-mode controller IC [5].

A “predictive gate drive” scheme based on a digital Delay-Locked Loop (DLL) was proposed using a D-flip-flop phase detector and a digital delay line to track the ideal dead-time [6]. This scheme has relatively poor transient performance, requiring numerous switching cycles to reach steady state. Moreover, even at “steady state”, the dead time swings sub-harmonically around the ideal dead time due to the nature of its nonlinear (“bang-bang”) phase detector and the fixed digital delay step. There is an inherent tradeoff between the steady state dead-time accuracy and the settling speed of the DLL since the delay can only be incremented by one step each cycle. Therefore the incremental digital delay cannot be reduced arbitrarily since the losses incurred while a slow DLL settles can be prohibitive. This drawback renders this scheme unsuitable for applications with frequent load variations such as microprocessors.

The current design employs analog Delay-Time Locked Loops (DTLL, Fig. 3) to allow quick and accurate adjustments of the dead-times. Comparators that sense the power MOSFETs’ vds zero-voltage crossing (CompVDS) and vgs threshold-voltage crossing (CompVGS) are followed by a phase detector, which provides up and down pulses for the charge pump by detecting the timing difference between the rising edges of the comparator outputs. The charge pump outputs the delay control voltage vctrl that linearly determines the dead time delay, which completes the negative feedback loop.

To maintain high-efficiency during load variations, it is desirable for the DTLLs to reach steady-state within at most several switching cycles. The gain of the DTLL can be expressed as:

G =ICP

IDL

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CCP

≈1, but ≤1 (4)

|G| must be chosen sufficiently large to obtain fast tracking without leading to instability (|G|>2) in this discrete-time DTLL system with a fixed one-cycle delay.

Non-linear delay-generators such as the resistor V-I converters used by [3-5] were avoided to maintain linearity. In the linear delay stage of Fig. 3, the PWM signal rapidly discharges Cdl, which is then linearly charged by Idl until it reaches the buffered Vctrl. The PWM signal is therefore delayed by td =Vctrl ⋅Cdl Idl .

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Locked Loops (DTLL); (b) circuits inside a DTLL block

For negative dead-time errors (Fig.4) the resonant transition is not completed and Cr is charged/discharged almost instantaneously, resulting in an UP pulse out of the phase detector (approximately T(dis-)charge) which is much shorter than the actual error |Terr2|. This leads to poor tracking since the short UP pulse does not sufficiently correct the dead-time. The problem is solved by inserting a One-Shot block, which linearly extends UP pulses exceeding a minimum threshold length (Fig. 5). Pulses narrower than the threshold travel to the charge pump, unaffected by the one-shot block. The threshold can be digitally adjusted.

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Fig. 4. Load transient leads to dead-time errors. (Shaded areas signify intensity of losses of respective currents.)

The references for the CompVGS in high- and low-side DTLLs are P and N threshold voltages respectively, which are internally generated using dedicated circuits. The CompVDS are connected across the power transistors. Therefore both CompVDS should be connected to VX and a

power rail. To account for the low power devices’ conduction voltage drop vds(on), a digitally trimmed offset is introduced at each comparator reference (see Fig.3a).

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Fig. 5. Up One-Shot Block The offset introduced into CompVDS causes the phase

detector DN pulse to be slightly extended by toffset beyond the ideal dead-time error (Terr1 in Fig.6, with respect to the ideal dead time T1). If such DN pulses were fed directly into the charge pump, the DTLL’s loop gain would be increased for small dead-time errors, possibly resulting in instability and excess delay time oscillations. To avoid this scenario, a Down Pulse One-Shot block similar to the UP Pulse One-Shot block is inserted to shorten the DN pulses beyond toffset, effectively creating a desirable control dead-zone. This dead-zone ensures that the DTLL loop gain is effectively reduced for small dead-time errors, yet largely unaffected for large errors. This permits the use of a higher loop gain, which helps fast rejection (of larger dead-time errors esp.) and prevents instability while approaching steady state.

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Fig. 6. Transient waveforms of ZVS-QSW buck converter with DTLLs under a dynamic switching (1.5A/10A) load

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Fig. 7. The ZVS-QSW system at 10A-load steady state

Fig.6 shows transient simulation results of the Current-Mode-controlled ZVS-QSW buck converter system under a dynamic load with large transient variations, similar to a modern high-speed microprocessor. The adjustment of

vctrl in both DTLLs rapidly follows the inductor current and dead-time errors are essentially eliminated in two cycles, as seen from the vctrl waveforms. After several cycles, the dead time delays reach steady state and the vx waveform in Fig. 7 exhibits ideal ZVS resonant transitions similar to Fig. 2. Fig. 8 shows the simulated loss distribution for several topologies. Fig. 8 shows the simulated loss distribution for the DTLL design and with fixed 10ns dead-times. Results are presented for rated (10A) and low loads (1.5A). The DTLL circuitry clearly eliminates switching losses under constant and dynamic loads, maintaining high efficiency. The DTLL advantage is even more promising as fs scales to 4MHz, where a high on-chip dynamic efficiency of 93% is achieved.

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fs=1MHz fs=4MHz

Fig. 8. On-chip losses with DTLL/fixed dead time (DT) (VO=1.3V, devices optimized @10A, for 1 and 4MHz)

III. CMOS IMPLEMENTATION A chip was designed in TSMC’s 0.18µm CMOS

process (Fig. 10) to demonstrate the DTLL concept. Fig. 9 shows the block diagram. In addition to the blocks of Fig. 3a, the chip includes an 8-bit digital delay line for comparison purpose, and a digital RAM file that stores calibration data. Various DTLL parameters such as the COMPVDS offsets and the one-shot thresholds can be digitally trimmed. The final setup will include an external PWM regulator. Both DTLL blocks can generate delays up to 50ns. The scaled-down power stage has a nominal output of 0.2A with VO=1V and Vin=2V.

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IV. CONCLUSION Conventional DC/DC topologies used for

microprocessor loads cannot satisfy future demands for shrinking voltages, rising switching-frequencies, tighter

regulation and high efficiency. Zero-Voltage-Switching can be applied to the Quasi-Square-Wave converter to eliminate switching losses, as long as the dead-times are adjusted in real-time to track load changes. Analog Dead-Time-Locked-Loops are shown to achieve fast error-rejection with low steady-state losses.

HSPICE simulations have demonstrated that the optimized design can achieve 93% on-chip efficiency at 4MHz under a 1.5A-10A dynamic load. A scaled down design is currently being fabricated in 0.18µm CMOS to demonstrate the DTLL concept, which has great potential for low cost, low profile, maximum integration and minimal external components.

Fig. 10. Layout for DTLL 0.18µm CMOS chip

ACKNOWLEDGEMENT The authors would like to thank NSERC, CITO, EST

Ontario, U of T open fellowship and Agile Systems, Inc., Ontario, Canada, for their support during this research.

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