faculty of computer science © 2006 cmput 229 input and output devices pooling and interrupts
TRANSCRIPT
Faculty of Computer Science
CMPUT 229 © 2006
Input and Output Devices
Pooling and Interrupts
© 2006
Department of Computing Science
CMPUT 229
I/O Fundamentals
Programmed data transfer
– An instruction for each data transfer
Direct Memory Access (DMA) transfer
– Processor requests transfer
– DMA controller moves the data between I/O and memory
Clements, pp. 412
© 2006
Department of Computing Science
CMPUT 229
I/O Fundamentals
Clements, pp. 412
Twisted pair
Start bitStop bit
© 2006
Department of Computing Science
CMPUT 229
I/O Fundamentals
Clements, pp. 413
Looks like a
Memory location
© 2006
Department of Computing Science
CMPUT 229
Memory-mapped I/O
Clements, pp. 414
© 2006
Department of Computing Science
CMPUT 229
Memory-mapped I/O
Each memory-mapped I/O device occupies at least two memory locations:
– A location for the data input or data output
– A location for the status byte associated with the port
Example
– Assume the following semantics for bit 0 of the status byte:
• 1: port is ready for data
• 0: port is busy
© 2006
Department of Computing Science
CMPUT 229
Pooling
FOR I = 1 TO 128
REPEAT
Read Port_status_byte
UNTIL Port_not_busy
Move data from Tablei to output_port
ENDFOR
Clements, pp. 415
© 2006
Department of Computing Science
CMPUT 229
Pooling PORTDATA EQU $0008000 Port address
PORTSTAT EQU $0008002 Port status byte
COUNT EQU 128 Size of block to output
*
ORG $002000 Start of data area
TABLE DS.B 128
*
ORG $000400
MOVE #COUNT, D1 Set count in D1
LEA TABLE, A0 A0 points to table in memory
LEA PORTDATA, A1 A1 points to data port
LEA PORTSTAT, A2 A2 points to port status byte
LOOP MOVE.B (A0)+, D0 Get byte from table
WAIT MOVE.B (A2), D2 REPEAT Read port status
AND.B #1, D2 Mask to extract lsb
BEQ WAIT Until port is ready
MOVE.B D0, (A1) Store data in peripheral
SUB #1, D1 Decrement loop counter
BNE LOOP Repeat until COUNT = 0
Clements, pp. 415
Pooling Loop
© 2006
Department of Computing Science
CMPUT 229
Interrupt Organization
Clements, pp. 416
© 2006
Department of Computing Science
CMPUT 229
Interrupt Sequence
Clements, pp. 417
© 2006
Department of Computing Science
CMPUT 229
Interrupt Sequence
Clements, pp. 417
© 2006
Department of Computing Science
CMPUT 229
Interrupt Sequence
Clements, pp. 417
© 2006
Department of Computing Science
CMPUT 229
Interrupt Sequence
Clements, pp. 417
© 2006
Department of Computing Science
CMPUT 229
Interrupt Sequence
Clements, pp. 417
© 2006
Department of Computing Science
CMPUT 229
Prioritized Interrupts
The 68K supports seven interrupt request inputs:
– IRQ7 is the most important
• also called a non-maskable interrupt request
– IRQ1 is the least important
The seven interrupt requests are encoded in three
interrupt request inputs:
– IPL0, IPL1, and IPL2
© 2006
Department of Computing Science
CMPUT 229
Masking Interrupts
The 68K has an interrupt mask that determines
which interrupt requests are enabled
– This mask is formed three bits (I2, I1, I0) of the processor
status register
– When the 68K services an interrupt, the mask is changed
to match the level of the interrupt being serviced
• Thus lower level interrupts are disabled until the current one is
serviced
© 2006
Department of Computing Science
CMPUT 229
68K Interrupt Structure
Clements, pp. 418
0
10
111
0
10
0
0
© 2006
Department of Computing Science
CMPUT 229
68K Status Word
Clements, pp. 419
© 2006
Department of Computing Science
CMPUT 229
Vectored Interrupts
How the processor finds out which device
requested an interruption:
– Polling: test sequentially each possible interruptor
– Vectorized: The interruptor identifies its own interrupt
handling routine
© 2006
Department of Computing Science
CMPUT 229
Interface polling: Memory-mapped data and status port
Clements, pp. 419
© 2006
Department of Computing Science
CMPUT 229
Responding to VectoredInterrupt
Clements, pp. 420
© 2006
Department of Computing Science
CMPUT 229
Daisy-chaining
There 256 interrupt vector numbers
– But the 68K supports only seven levels of interrupt
Daisy-chain links several peripherals together in a
line.
Devices closer to the CPU have more chances of
having their interrupts acknowledged.
© 2006
Department of Computing Science
CMPUT 229
Daisy-Chain of I/O Devices
Clements, pp. 421
© 2006
Department of Computing Science
CMPUT 229
Direct Memory Access
Transfer data from a peripheral and memory
DMA grabs the data and address bus
Releases the processor from executing many
instructions to transfer the data.
© 2006
Department of Computing Science
CMPUT 229
DMA Protocol
Clements, pp. 423
© 2006
Department of Computing Science
CMPUT 229
DMA Protocol
Clements, pp. 423
© 2006
Department of Computing Science
CMPUT 229
DMA Protocol
Clements, pp. 423
© 2006
Department of Computing Science
CMPUT 229
DMA Protocol
Clements, pp. 423
© 2006
Department of Computing Science
CMPUT 229
DMA Protocol
Clements, pp. 423
© 2006
Department of Computing Science
CMPUT 229
Direct Memory Access
Clements, pp. 422
© 2006
Department of Computing Science
CMPUT 229
Direct Memory Access
Clements, pp. 422
© 2006
Department of Computing Science
CMPUT 229
DMA Operating Modes
Burst Mode
– DMA seizes the bus and keep it until the data transfer is
completed
Cycle Stealing Mode
– DMA operations are interleaved with normal memory
accesses.
– Called transparent DMA
© 2006
Department of Computing Science
CMPUT 229
DMA by Cycle Stealing