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Syllabus• Interrupt Application 8254 Timer; 8259 Controller• Digital Interfacing 8255 PPI; Handshaked I/O; Interfacing keybds,

displays, Encoders• Analog Interfacing Sensors, Transducers; D/A & A/D interfacing• Robotics and Embedded control• System peripherals Keybd, mouse, Storage devices, Printer• Data Comn & Networks Asynch & Synch Serial data comn & Protocols; LAN,

GPIB, HPIB, IEEE-488 BUS

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InterruptsRequirement ?• For “Synchronization” i.e. for coordinating the

activities of the processor with that of the I/O devices.

• Processors allow normal program execution to be interrupted by some external signal {called the INTERRUPT REQUEST}.

• In response to the interrupt the µP stops executing its current program and calls for a procedure to service the interrupt

• An INTERRUPT RETURN (IRET) instruction at the end of the Interrupt service routine returns execution back to the interrupted program.

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3 SOURCES• HARDWARE INTERRUPTS• SOFTWARE INTERRUPTS• EXCEPTION

SOURCES OF INTERRUPTSSOURCES OF INTERRUPTS

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Execution of an Instruction

Put the next memory location on the address bus (2001 h)

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Execution of an InstructionExecution of an Instruction

Get the data byte from the memory

Put into accumulator

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Execution of an InstructionExecution of an Instruction How long does it take to execute this two-byte instruction (op-code) ?

It is quite possible to accurately predict the time that is required to run each instruction, and to run the entire program !

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8085 Instruction Set8085 Instruction Set The 8085 instructions can be classified as follows:

Data transfer operations

Arithmetic operations (ADD, SUB, INR, DCR)

Logic operations

Branching operations (JMP, CALL, RET)

• Between registers• Between memory location and a register• Direct write to a register / memory• Between I/O device and accumulator

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8085 Instruction Types8085 Instruction Types

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8085 Instruction Types8085 Instruction Types

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8085 Instruction Types8085 Instruction Types

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Instruction set of 8085The 8085 is designed to execute 74 different instruction types

1.    Data Transfer Group:    The data transfer instructions move data between registers or between memory and registers.

MOV           Move MVI           Move ImmediateLDA           Load Accumulator Directly from MemorySTA           Store Accumulator Directly in MemoryLHLD          Load H & L Registers Directly from MemorySHLD          Store H & L Registers Directly in Memory 

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LXI           Load Register Pair with Immediate data LDAX          Load Accumulator from Address in Register PairSTAX          Store Accumulator in Address in Register PairXCHG          Exchange H & L with D & EXTHL          Exchange Top of Stack with H & L

Instruction set of 8085An 'X' in the name of a data transfer instruction implies that it deals with a register pair (16-bits);

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2.    Arithmetic Group:       The arithmetic instructions add, subtract, increment, or decrement data in registers or memory.

ADD    Add to Accumulator ADI      Add Immediate Data to Accumulator

ADC   Add to Accumulator Using Carry Flag ACI    Add Immediate data to Accumulator Using carry SUB   Subtract from AccumulatorSUI     Subtract Immediate Data from AccumulatorSBB   Subtract from Accumulator Using Borrow (Carry) Flag

SBI     Subtract Immediate from Accumulator Using Borrow (Carry) Flag

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INR      Increment Specified Byte by OneDCR    Decrement Specified Byte by OneINX      Increment Register Pair by OneDCX     Decrement Register Pair by OneDAD     Double Register Add; Add Content of register  Pair to H & L Register Pair

Arithmetic Group:

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3.Logical Group: This group performs logical (Boolean) operations on data in registers and memory and on condition flags.     The logical AND, OR, and Exclusive OR instructions enable you to set specific bits in the accumulator ON or OFF.

 ANA         Logical AND with Accumulator

ANI           Logical AND with Accumulator Using Immediate Data ORA         Logical OR with AccumulatorOR            Logical OR with Accumulator Using Immediate DataXRA         Exclusive Logical OR with AccumulatorXRI           Exclusive OR Using Immediate Data       

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CMP           Compare CPI           Compare Using Immediate DataThe rotate instructions shift the contents of the accumulator one bit position to the left or right: RLC           Rotate Accumulator LeftRRC           Rotate Accumulator RightRAL           Rotate Left Through CarryRAR           Rotate Right Through Carry Complement and carry flag instructions:

CMA           Complement Accumulator CMC           Complement Carry FlagSTC           Set Carry Flag

The Compare instructions compare the content of an 8-bit value with the contents of the accumulator

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4.     Branch Group:    The branching instructions alter normal sequential program flow, either unconditionally or conditionally. The unconditional branching instructions are as follows:JMP   JumpCALL          CallRET          Return

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  Conditional branching instructions examine the status of one of four condition flags to determine whether the specified branch is to be executed. The conditions that may be specified are as follows:NZ           Not Zero (Z = 0) Z             Zero (Z = 1)NC          No Carry (C = 0)C             Carry (C = 1)PO           Parity Odd (P = 0)PE           Parity Even (P        = 1)P             Plus (S = 0)M            Minus (S = 1)

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Thus, the conditional branching instructions are specified as follows: Jumps         Calls        Returns C                   CC           RC      (Carry)INC               CNC         RNC     (No JZ                 CZ            RZ  (zero)JNZ               CNZ         RNZ     (Not Zero) JP                 CP            RP      (Plus)JM                CM            RM      (Minus)JPE              CPE          RPE     (Parity Even) JP0                CPO        RPO     (Parity Odd)Two other instructions can affect a branch by replacing the contents or the program counter: PCHL          Move H & L to Program Counter RST           Special Restart Instruction Used   with Interrupts

carry)

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5.    Stack I/O, and Machine Control Instructions: The following instructions affect the Stack and/or Stack Pointer:PUSH         Push Two bytes of Data onto the Stack POP           Pop Two Bytes of Data off the stack XTHL         Exchange Top of Stack with H &L SPHL        Move content of H & L to Stack PointerThe I/O instructions are as follows: IN            Initiate Input Operation OUT           Initiate Output Operation

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The Machine Control instructions are as follows: EI            Enable Interrupt FLAGDI            Disable Interrupt FLAGHLT         HaltNOP        No Operation

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A VERY Simple ProgramA VERY Simple Program

Add two hexadecimal numbers:

Load register A (accumulator) with 32 (hex)

Load register B with 48 (hex)

Add the two numbers and save the sum in A

Display accumulator (A) contents at port (01)

End

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A VERY Simple ProgramA VERY Simple Program

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InterruptInterrupt• The microprocessor can be interrupted from its normal operations to execute instructions from another memory location.

• There are several interrupt inputs, with each having a priority setting and a restart address.

• The interrupt requests are classified in two categories : maskable interrupt and nonmaskable interrupt. 8085 has four maskable interrupts and one nonmaskable interrupt. Among the four maskable interrupts one is non vectored, which requires external hardware to supply the address to restart the execution. The other three are vectored to specific locations

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RAWrite about RST AND STEPS TAKEN DURING INTERRUPT

EI:Enable Interrupt FLAG. It enables the interrupt processDI:Disable Interrupt FLAG. It disables the interrupt process.

SIM This instruction implement the 8085 interrupts and serial data output

This instruction interprets the accumulator contents as follows

D7 D6 D5 D4 D3 D2 D1 D0

SOD SDE XXX R7.5 MSE M7.5 M6.5 M5.5

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D0 =0, RST 5.5 is enabledD1 =0, RST 6.5 is enabledD2 =0, RST 7.5 is enabledD3(Mask set enable) If thes bit is high, it enabkes the functions of bits D2,D1,D0. This is a master control Over all the interrupt masking bit. If this bit is low, bits D2,D1,D0 do not have any effect on the masks.D4 If this bit is 1 , RST 7.5 Flip flop is reset. This is an Additional control to reset RST 7.5D5 Don’t care

ExampleMVI A,0EH Bits D3=1 and D0=0SIM Enable RST 5.5

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RST: RestartThese instruction are used conjunction with interrupts andInserted using external hardware. However these can Be used as software instructions in a program to transferProgram execution to one of the eight locationsOpcodeRST 0RST 1RST 2RST 3RST 4RST 5RST 6RST 7

Hex CodeC7CFD7DFE7EFF7FF

Restart Address00000008001000180020002800300038

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EXPLAIN THE INTERRUPT PROCESSAS IN PAGE 359

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Interrupt PriorityInterrupt PriorityThe table on the following page describes the priority of the interrupts and restarts.

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Interrupt (INTR)Interrupt (INTR)• The interrupt input creates a pause for

the program execution.

• This pause allows the microprocessor to run a sub-routine, or a different set of instruction.

• When the sub-routine is done, the program continues from where it left off (from the PC).

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TRAPTRAP• The TRAP command is the highest level

interrupt.

• TRAP causes the CPU to execute the command located at memory location 24H.

• Typically, TRAP is used for urgent request. For instance, a shut-down routine.

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I/O ADDRESSINGThere are two different methods by which I/O devices Be identified: one uses 8-bit address and the other uses a 16-bit address. I/O with 8- bit addresses (peripheral- Mapped I/O)

8085 uses eight address lines to identify an input or an output device. It is used in conjunction with input and output instructions. The 8 address lines can have 256addresses; thus 8085 can identify 256 input devicesand 256 output devices with addresses ranging from 00H to FFH. The input and output devices are differentiatedby the control signals;8085 use the I/O read control signal for input devices and the I/O write control signal for output devices. The entire range of I/O addresses from 00 to FFis known as an I/O map, and individual addresses are referred to as I/O device addresses or I/O port numbers.

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I/O with 16-bit addresses (memory mapped I/O)

In this 8085 uses 16 address lines to identify an I/O device: an I/O is connected as if it is a memory register. This is known as memory mapped I/O. 8085 uses the same control signal (memory read or memory write) andinstructions as those of memory.

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RST 7.5

RST 6.5

RST 5.5

TRAP

INTR

QD Q CLR

PRIORITY INPUT PIN MASK VECTOR LOCATIONS