evla corr codr panel report v6 - national radio astronomy ......adder 4-s ta ion compl exmi r +...

Architecture Walk-through

National Research CouncilCanada

Conseil national de recherchesCanada EVLA Correlator Conceptual Design Review

B. Carlson, 2001-Nov-02EVLA Correlator Conceptual Design Review

2

Outline

• Overview.

• Board descriptions.

• System design issues.


3

OVERVIEW


4

Antennas:Receivers,Samplers,Fibre WDM

FOTS


5

Fibre WDMDemodulators


FOTS

-48 VDC to1.8V, 2.5VPOWERSUPPLY

MCBInterfaceModuleEt

hern

et

Fibre-OpticReceiverModule

DELAY

DELAY

FIRFilterBank

FIRFilterBank

Sw

itch

Sw

itch

Timing

Station Board

WidebandAutocorrelator


6

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0


Sub-band Distributor Backplane


FOTS

TIMECODEGeneratorBox (TGB)

Reference Clock

Reference Time Tick

TIMECODE(s) + CLOCK(s)



hern

et


DELAY

DELAY

FIRFilterBank

FIRFilterBank

Sw

itch

Sw

itch

Timing

Station Board Master Slave 1 Slave 2 Slave 3



7

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MDR-80

MDR-80

MDR-80

MDR-80

MDR-80

MDR-80



StationDataFanoutBoard


FOTS


Reference Clock

Reference Time Tick




hern

et


DELAY

DELAY

FIRFilterBank

FIRFilterBank

Sw

itch

Sw

itch

Timing

Station Board

Retiming/Drivers

Master Slave 1 Slave 2 Slave 3



8

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MDR-80

MDR-80

MDR-80

MDR-80

MDR-80

MDR-80

MDR

-80

MDR

-80

MDR

-80

MDR

-80

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0



BaselineEntryBackplane



FOTS


Reference Clock

Reference Time Tick


Baseline Board



hern

et


DELAY

DELAY

FIRFilterBank

FIRFilterBank

Sw

itch

Sw

itch

Timing

Station Board

Retiming/Drivers

8 'X

' Rec

ircu

latio

n C

ontr

olle

rs

8 'Y' Recirculation Controllers

8 x 8Correlator Chip

and LTA ControllerMatrix


hern

et

-48 VDC to1.8V , 2.5VPOWERSUPPLY

FPDPI/F(s)




9

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MDR-80

MDR-80

MDR-80

MDR-80

MDR-80

MDR-80

MDR

-80

MDR

-80

MDR

-80

MDR

-80

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

4-StationComplex Mixer

+ 1st Stage

Adder

48-S

tatio

n D

ata

Ent

ry C

onne

ctor

s


Pow

erC

onne

ctor

MCBInterfaceModule





PhasingBoardEntryBackplane


FOTS


Reference Clock

Reference Time Tick


Baseline Board



hern

et


DELAY

DELAY

FIRFilterBank

FIRFilterBank

Sw

itch

Sw

itch

Timing

Station Board

Retiming/Drivers

8 'X

' Rec

ircu

latio

n C

ontr

olle

rs





hern

et


FPDPI/F(s)


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder

(5)Sub-array2nd-Stage

Adders

FIRFilterBank

Sw

itch

Phasing Board



200

pin

type

E20

0 pi

n ty

pe E

200

pin

type

E20

0 pi

n ty

pe E

200

pin

type

E20

0 pi

n ty

pe E


+ 1st Stage

Adder


+ 1st Stage

Adder


10

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MDR-80

MDR-80

MDR-80

MDR-80

MDR-80

MDR-80

MDR

-80

MDR

-80

MDR

-80

MDR

-80

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0


+ 1st Stage

Adder

48-S

tatio

n D

ata

Ent

ry C

onne

ctor

s


Pow

erC

onne

ctor

MCBInterfaceModule







FOTS


Reference Clock

Reference Time Tick


Finalsynchronization

and VLBI recorderinterface

VLBIRecorder(s)

Phased outputfeedback

synchronization

To phased-VLAStation Board

input(s)

Baseline Board



hern

et


DELAY

DELAY

FIRFilterBank

FIRFilterBank

Sw

itch

Sw

itch

Timing

Station Board

Retiming/Drivers

8 'X

' Rec

ircu

latio

n C

ontr

olle

rs





hern

et


FPDPI/F(s)


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder


Adders

FIRFilterBank

Sw

itch

Phasing Board



200

pin

type

E20

0 pi

n ty

pe E

200

pin

type

E20

0 pi

n ty

pe E

200

pin

type

E20

0 pi

n ty

pe E


+ 1st Stage

Adder


+ 1st Stage

Adder


11

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MDR-80

MDR-80

MDR-80

MDR-80

MDR-80

MDR-80

MDR

-80

MDR

-80

MDR

-80

MDR

-80

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0


+ 1st Stage

Adder

48-S

tatio

n D

ata

Ent

ry C

onne

ctor

s


Pow

erC

onne

ctor

MCBInterfaceModule






Network Switches

Host/Control

Computers;Archiving


FOTS

PC/CPCI

FPDP I/Fs


Reference Clock

Reference Time Tick


Finalsynchronization

and VLBI recorderinterface

VLBIRecorder(s)

Phased outputfeedback

synchronization

To phased-VLAStation Board

input(s)

Baseline Board

PC/CPCI

PC/CPCI



hern

et


DELAY

DELAY

FIRFilterBank

FIRFilterBank

Sw

itch

Sw

itch

Timing

Station Board

Retiming/Drivers

8 'X

' Rec

ircu

latio

n C

ontr

olle

rs





hern

et


FPDPI/F(s)


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder


+ 1st Stage

Adder


Adders

FIRFilterBank

Sw

itch

Phasing Board



200

pin

type

E20

0 pi

n ty

pe E

200

pin

type

E20

0 pi

n ty

pe E

200

pin

type

E20

0 pi

n ty

pe E


+ 1st Stage

Adder


+ 1st Stage

Adder


12

STATION BOARD


13

F ib erD em o d u lat o r


Def

orm

attin

g,S

ynch

roni

zatio

n,B

ER

T R

x/Tx

Co

nn

ect

or

A1HzAC LK

Data(64)

FOTS Rx Module - R

DVALID

TIM

EC

OD

ER

CLK

D at a P at hS wit ch

+L ev el C o n t ro l

+B ER T R X/T X

A1HzAC LK

DVALID

AC LK

D V A LI D

A1Hz



Def

orm

attin

g,S

ynch

roni

zatio

n,B

ER

T R

x/Tx

Co

nn

ect

or

A1HzAC LK

Data(64)

FOTS Rx Module - L

DVALID

TIM

EC

OD

ER

CLK

Fine DelayController

+STATE Cnts

+BERT Rx

Con

nect

or

SDRAM64M x 72

Con

nect

or

Delay/Memory

Controller

A1Hz

DVALIDDVALID

RC LK

Coarse Delay Module - L

ACLKTIMECODE

Connector

D at a P at hS wit ch

+L ev el C o n t ro l

+B ER T R X/T X

A1HzAC LK

DVALID

AC LK

D V A LI D

A1Hz

Fine DelayController

+STATE Cnts

+BERT Rx

DVALID

DVALID

8sb0

8sb1

8sb2

8sb3

8sb4 sb5 sb6 sb7

8sb8

8sb9

8sb10

8sb11

8sb12 sb13 sb14 sb15

8 8 8

8 8 8

Gat

ing,

STA

TE C

nts,

pC

al +

For

mat

ting

Cross-barSwitch

4

F.P

. Rad

arO

UTP

UT-

L

Fo

rma

t,S

am

ple

clo

ckg

en

.

Data

CLK

TickR C LK

TIM EC OD E

F IRF P G A

4

D VALID

D VALID

Lsb0-7

Lsb8-15Lsb-radar

R ef /C al F ilt er

L-Su

b-ba

nd C

onne

ctor

LsbO-0LsbO-1LsbO-2LsbO-3LsbO-4LsbO-5LsbO-6LsbO-7LsbO-8LsbO-9

LsbO-10LsbO-11LsbO-12LsbO-13LsbO-14LsbO-15LsbO-16LsbO-17Pu lsar T im er

+16 G at e G en .

8 X DelayGenerator

D U M P T R IG G en .+

PH ASEM O D G en .+

F o rm at t in g /T im in g

1

Tim

ing/

Con

trol

Con

nect

or

CLOC KD UM PTR IGD ELAYM ODPH ASEM ODTIM EC ODE

CLOCK-INTIM EC ODE-IN

R C LKT IM EC OD E

D ELAYM OD

D ELAY-RD ELAY-L

RC LKT IM EC OD E

R C LKTIM EC ODE

R C LKTIM EC OD E

DELAY-L


Pow

erC

onne

ctor

LCP FIR Filter Bank

NarrowbandRadar Filter

R-F

iber

Con

nect

ors

L-Fi

ber C

onne

ctor

s

Config/Status

Config/Status

Config/Status

Config/Status

Burs tI/F

Blank ing


FPGA

MCBInterfaceModule

LocalAddress /Data Bus

Eth

erne

t

Con

nect

or

SDRAM64M x 72

Con

nect

or

Delay/Memory

Controller

A1Hz

DVALIDDVALID

RC LK

Coarse Delay Module - R

ACLKTIMECODE

Connector

F IRF PG A

F IRF PG A

F IRF PG A

F IRF PG A

F IRF PG A

F IRF PG A

F IRF P G A

F IRF P G A

F IRF PG A

F IRF PG A

F IRF PG A

F IRF PG A

F IRF PG A

F IRF PG A

F IRF P G A

F IRF PG A

FIRFPGA

8sb0

8sb1

8sb2

8sb3

8sb4 sb5 sb6 sb7

8sb8

8sb9

8sb10

8sb11

8sb12 sb13 sb14 sb15

8 8 8

8 8 8

Gat

ing,

STA

TE C

nts,

pC

al +

For

mat

ting

Cross-barSwitch

4

F.P

. Rad

arO

UTP

UT-

R

Fo

rma

t,S

am

ple

clo

ckg

en

.

Data

CLK

TickR C LK

TIM EC OD E

F IRF P G A

4

R sb0-7

R sb8-15R sb-radar

R ef /C al F ilt er

R-S

ub-b

and

Con

nect

or

R sbO-0R sbO-1R sbO-2R sbO-3R sbO-4R sbO-5R sbO-6R sbO-7R sbO-8R sbO-9R sbO-10RsbO-11RsbO-12RsbO-13RsbO-14RsbO-15RsbO-16RsbO-17Pu lsar T im er

+16 G at e G en .

RC LKT IM EC OD E

R C LKTIM EC OD E

D ELAY-R

RCP FIR Filter Bank

NarrowbandRadar Filter

Burs tI/F

Blank ing

F IRF PG A

F IRF PG A

F IRF PG A

F IRF PG A

F IRF PG A

F IRF PG A

F IRF P G A

F IRF P G A

F IRF PG A

F IRF PG A

F IRF PG A

F IRF PG A

F IRF PG A

F IRF PG A

F IRF P G A

F IRF PG A

FIRFPGA

Ext

erna

lB

lank

ing

• Each Station Board handlesone baseband pair (2 x 2 GHz= 4 GHz), 4 bits/sample.

• 8 bits/sample possible with1/2 bandwidth.

• Two banks of 18 poly-phaseFIR filters: each oneindependent in width andplacement in the baseband.

• Input 64-bit, 256 Ms/s “datahighway” could be reassignedto multiple basebands.

• Generates all timing, dumpcontrol, delay, and phase fordownstream processing.

• Use SDRAM for >10k kmbaselines.

• Output switch for flexibility.


14

SUB-BAND DISTRIBUTORBACKPLANE


15

200

pin

type

E

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

200

pin

type

E20

0 pi

n ty

pe E

200

pin

type

E20

0 pi

n ty

pe E

200

pin

type

E

200

pin

type

E20

0 pi

n ty

pe E

200

pin

type

E

200

pin

type

E20

0 pi

n ty

pe E

200

pin

type

E

200-pin type Emale headers(opposite side)

80-pin MDR headers(sub-band data out x 18)

-48VDC main powerconnectors

48VDC blind-mateheaders (opposite side)

TIMECODE+ CLOCK entryheader

~9.75" (6U)

~9.75"


16

200

pin

type

E

MD

R-8

0

200

pin

type

E20

0 pi

n ty

pe E

200

pin

type

E20

0 pi

n ty

pe E

200

pin

type

E

200

pin

type

E20

0 pi

n ty

pe E

200

pin

type

E

200

pin

type

E20

0 pi

n ty

pe E

200

pin

type

E

#1 (Master) #2 #3 #4

Each MDR-80 connectorcontains one sub-band from all8 basebands (8 x 4-bits).

(+ TIMECODE + DUMPTRIG,+ PHASEMOD, +DELAYMOD + CLOCK)


17

STATION DATA FANOUTBOARD


18

Station Data Fanout Board• Fans data out to

Baseline Boardswithin a BaselineRack.

• For 32 stations, afanout of 4 isrequired, 40 stationsrequires a fanout of5, 48 stations afanout of 6.

• Also fans data out toPhasing Boards, andexpansion boards.

8 16 24 32 40 48

8

16

24

32

40

48

8 x 8 correlatorparallelogram(Baseline Board)

1

2

3 4 5 6

17

Station #17distribution


19

XCV50E-FG256C

DA

TEL

UN

R-3

.3/8

-D5

(3.3

V @

8 A

)

DATELUNR-1.8/2-D5SM(1.8V @ 2A)

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

1.8V and 3.3VDC-DC powersupplies

Input MDR-80Header (oppositeside)

LVDSReceivers

RetimingFPGA

LVDSDrivers Output MDR-80

Headers

Opposite sideholes forexpansionoutput

Sub-band breakoutheaders for PhasingBoards

8"

3.5"


20

Inside backpanel ofbaseline rack

Guide posts

Fastening posts

Cableportal

MDR-80entryconnector

SDFBattachmentplate

SDFB PCB(opposite side)

• Straw-man concept for hot-swapping the SDFB.

• Mount SDFB to plate, thatcan be unfastened from theback panel of the BaselineRack.

• Guide posts allowextraction of SDFB platewithout short circuit worry.

• Remove cables, install newplate assembly...

• Alternative is to use a set ofblind-mate MDR-80 socketson PCB that mountspermanently to back panel.Higher cost...


21

BASELINE ENTRYBACKPLANE


22

200

pin

type

E20

0 pi

n ty

pe E

200

pin

type

E20

0 pi

n ty

pe E

200

pin

type

E20

0 pi

n ty

pe E

200

pin

type

E

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

MD

R-8

0

12U(~19.5")

2.5"

MDR-80 station dataentry headers


48VDC blind-mateheaders


• Feeds sub-band (MDR-80) datathrough to the Baseline Board.

• Blind-mate with Baseline Board.

• Single board design permits flexibilityin mixing Baseline Boards and PhasingBoards in the same sub-rack.

• Many pins using 200-pin (hm 2.0, 8row) connectors, yields high insertionforce (~100 lbs).

• hm 2.0 connectors should be ok for256 Mbits/sec.


23

BASELINE BOARD


24

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

RecirculationController

512kDPSRAM


512kDPSRAM


512kDPSRAM


512kDPSRAM


512kDPSRAM


512kDPSRAM


512kDPSRAM


512kDPSRAM


512kDPSRAM


512kDPSRAM


512kDPSRAM


512kDPSRAM


512kDPSRAM


512kDPSRAM


512kDPSRAM


512kDPSRAM

FPDP Connector

FPDP Connector

FPDP Connector

FPDP Connector

FPDPScheduler

FPGA

X-S

tatio

n In

pu

ts

Y-Station Inputs

MCBInterfaceModule MCBAddress

DecoderFPGA

DATA

ADDRESS

CONTROL

Chipselects

PowerSupplies

&Temperature/

VoltageMonitoring


25

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M

2048C-lag

CorrelatorChip

LTAContrlr

SD

RA

M


512kDPSRAM


512kDPSRAM


512kDPSRAM


512kDPSRAM

FPDP Connector

FPDPScheduler

FPGA

X-S

tati

on

Inp

uts

Y-Station Inputs

Local FPDP Bus

ExternalworldFPDP

Column (Y)transmissionlines

Row (X)transmissionlines

LTA Controller status/control • FPDP is asimple protocolto handle withan FPGA, withno CPUinteraction.

• Alternatesolutions(Firewire)possible…aslong ascontrolled byFPGA.


26

Vicor PSV8B2C100A(1.8V, 90W)



Vicor PSV8C3V3C75A(2.5V, 56W)


MCB interfaceconnector

MCBinterfacemodule

8x8 correlatorchip array

FPDPdrivers

FPDPSchedulerFPGA

RecirculationControllerFPGAs

FPDPconnector(primary)

FPDPconnector(secondary)



Input connectorsmating with theBaseline EntryBackplane

X inputs

Y inp

uts

MCB addressdecoderFPGA

Baseline Board Layout - Front View Baseline Board Layout - Rear View

LTA ControllerFPGAs

256 MbitLTA SDRAMs

256k x 18RecirculationcontrollerDPSRAMs


27






X inputs

Y inp

uts

Baseline Board Layout - Front View - High Speed Data Routing Baseline Board Layout - Rear View - FPDP Bus Routing - Multiple Output

LTA ControllerFPGAs

256 MbitLTA SDRAMs

256k x 18RecirculationcontrollerDPSRAMs

=

LocalFPDPbusses

MultipleTM FPDPinterfaces


28

PHASING BOARDENTRY BACKPLANE


29

2.5"

12U(~19.5")


48 x single station,sub-band pairinput connectors(12 diff. signals)

200

pin

type

E20

0 pi

n ty

pe E

200

pin

type

E20

0 pi

n ty

pe E

200

pin

type

E20

0 pi

n ty

pe E


48VDC blind-mateheaders

• Feeds up to 48 stations, 1 sub-band pairinto a Phasing Board.

• Each connector contains two, 4-bit datapaths, timing, delay, and phase.

• Use GORE “quietzone” cables /connectors (12 pairs).


30

PHASING BOARD


31

cosLUT

sinLUT p

hase

gen

de lay -to -phase

LU T

cosLUT

sinLUT p

hase

gen

SDATA(0)

PHASEMOD

DELAYMOD

PHASEMOD

SDATA(1)

SDATA(2)SDATA(3)

9

9

I

Q

4-Station Mixer + 1s t Stage Adder

cosLUT

sinLUT p

hase

gen

de lay -to -phase

LU T

cosLUT

sinLUT p

hase

gen

SDATA(0)

PHASEMOD

DELAYMOD

PHASEMOD

SDATA(1)

SDATA(2)SDATA(3)

9

9

I

Q


cosLUT

sinLUT p

hase

gen

de lay -to -phase

LU T

cosLUT

sinLUT p

hase

gen

SDATA(0)

PHASEMOD

DELAYMOD

PHASEMOD

SDATA(1)

SDATA(2)SDATA(3)

9

9

I

Q


cosLUT

sinLUT p

hase

gen

de lay -to -phase

LU T

cosLUT

sinLUT p

hase

gen

SDATA(0)

PHASEMOD

DELAYMOD

PHASEMOD

SDATA(1)

SDATA(2)SDATA(3)

9

9

I

Q


cosLUT

sinLUT p

hase

gen

de lay -to -phas e

LUT

cosLUT

sinLUT p

hase

gen

SDATA(0)

PHASEMOD

DELAYMOD

PHASEMOD

SDATA(1)

SDATA(2)SDATA(3)

9

9

I

Q

4-Station Mixe r + 1st Stage Adde r

cosLUT

sinLUT p

hase

gen

de lay -to -phas e

LUT

cosLUT

sinLUT p

hase

gen

SDATA(0)

PHASEMOD

DELAYMOD

PHASEMOD

SDATA(1)

SDATA(2)SDATA(3)

9

9

I

Q


cosLUT

sinLUT p

hase

gen

de lay -to -phas e

LUT

cosLUT

sinLUT p

hase

gen

SDATA(0)

PHASEMOD

DELAYMOD

PHASEMOD

SDATA(1)

SDATA(2)SDATA(3)

9

9

I

Q


cosLUT

sinLUT p

hase

gen

de lay -to -phas e

LUT

cosLUT

sinLUT p

hase

gen

SDATA(0)

PHASEMOD

DELAYMOD

PHASEMOD

SDATA(1)

SDATA(2)SDATA(3)

9

9

I

Q


cosLUT

sinLUT p

hase

gen

de lay -to -phas e

LUT

cosLUT

sinLUT p

hase

gen

SDATA(0)

PHASEMOD

DELAYMOD

PHASEMOD

SDATA(1)

SDATA(2)SDATA(3)

9

9

I

Q


48-S

tatio

n D

ata

En

try

Co

nn

ecto

rs

4X:SDATA,CLOCK,

TIMECODE,DELAYMOD,PHASEMOD

4X:SDATA,CLOCK,


4X:SDATA,CLOCK,


4X:SDATA,CLOCK,


4X:SDATA,CLOCK,


4X:SDATA,CLOCK,


4X:SDATA,CLOCK,


4X:SDATA,CLOCK,


4X:SDATA,CLOCK,


4X:SDATA,CLOCK,


95-tap Hilbert FIR,Final Adder, ReQuant.

H(n)

Delay

4/8-bit

2-bit12 Element

ComplexSub-array

Adder

12 Elem entComplex

Sub-arrayAdder

12 ElementComplex

Sub-arrayAdder

12 ElementComplex

Sub-arrayAdder

12 ElementComplex

Sub-arrayAdder

Out

put C

onne

ctor

(s)

Sub-Sub-band FIR Filter Bank

FIR:FPGA

(512 tap)-48 VDC to1.8V, 2.5VPOWERSUPPLY

Pow

erC

onne

ctor

ComplexSub-Array

Adders

Hilbert FIRs,Final Adders,Requantizers

Quad ComplexMixers and

1st Stage Adders


H(n)

Delay

4/8-bit

2-bit


H(n)

Delay

4/8-bit

2-bit


H(n)

Delay

4/8-bit

2-bit


H(n)

Delay

4/8-bit

2-bit

FIR:FPGA

(512 tap)

FIR:FPGA

(512 tap)

FIR:FPGA

(512 tap)

FIR:FPGA

(512 tap)

FIR:FPGA

(512 tap)

FIR:FPGA

(512 tap)

FIR:FPGA

(512 tap)

Out

put F

orm

attin

g

TIMECODECLOCK

Pha

sing

Exp

ansi

onC

onne

ctor SYNC_PULSE

CLOCK

OutputSelection and

Formatting

MCBInterfaceModule

LocalAddress/Data Bus

Eth

erne

t

cosLUT

sinLUT p

hase

gen

de lay -to-phase

LU T

cosLUT

sinLUT p

hase

gen

SDATA(0)

PHASEMOD

DELAYMOD

PHASEMOD

SDATA(1)

SDATA(2)SDATA(3)

9

9

I

Q


cosLUT

sinLUT p

hase

gen

de lay -to -phase

LU T

cosLUT

sinLUT p

hase

gen

SDATA(0)

PHASEMOD

DELAYMOD

PHASEMOD

SDATA(1)

SDATA(2)SDATA(3)

9

9

I

Q


4X:SDATA,CLOCK,


4X:SDATA,CLOCK,


cosLUT

sinLUT p

hase

gen

de lay -to -phase

LU T

cosLUT

sinLUT p

hase

gen

SDATA(0)

PHASEMOD

DELAYMOD

PHASEMOD

SDATA(1)

SDATA(2)SDATA(3)

9

9

I

Q


• Phases 1 sub-bandpair, from up to 48stations.

• “Phasinggranularity” of 4stations to preventexcessive connectionproblems.

• 5 sub-arrays.

• Sub-sub-bandfiltering for moreefficient narrowbanddata recording.

• All digital.

• 8-bit output forexpansion >48 stations


32

TIMECODEGENERATOR BOX


33

• Generates “TIMECODE” for use by correlator.• 4 TIMECODES generated. Each Station Board “quad” can

select any of the 4. This permits mixed real-time and tape-based VLBI operation.

• 48 outputs to go to up to 48 Sub-band Distributor Backplanes.• Requires input clock and reference time tick.


34

SYSTEM DESIGN ISSUES


35

Sub-rack Design

~19" (12U)

~6"

12U x 400 mm (15.7") x 23"board installation volume

15.7"

Fan tray

Freshairintake

FRONTREAR

Backplanefasteningbars

TOP (exhaust)

BOTTOM

• 24” wide to allow 8boards, with 2.5” width perboard (3 full VME slots perboard).

• Fresh (cool) air supply foreach sub-rack (crate) ofboards.

• Requires hot-swappablefan (tray).

• Requires more verticalrack space...


36

Station Rack Design

6.5-7'

FRONT

• Cool air entry from bottom.

• Each sub-rack has own cool air.

• Probably only fit two sub-racks perrack (7’).

• Estimated power dissipation:200W/board ~= 2kW/sub-rack ~=4kW/rack.


37

Baseline Rack Design

Floor level

Front

Rear

6 ft

6.5-7 ft

BaselineSub-racks(12U x 400 mm)

Air entry

20 row x 2 colStationDataFanoutBoards

Horizontalcable routingsection

Verticalcable routingsection

Sub-rack entrycable routingsection

40 sub-bandcables fromstation racks

1 2 3

1

2

3

• Must hold up to256, ~3 m 80-wireGORE cables.

• Extra 3’ depth,with rear and side-panel access.

• “Grid routing” toorganize cabling.

• Will build fullmock-up to testfeasibility.


38

Remote Power M&C

SBDB SBDB

SBDB SBDB

BE

BB

EB

BE

B

BE

BB

EB

BE

B

BE

BP

BE

B

Station Rack Baseline Rack

To monitorand controlcomputer

(PC)

To monitorand controlcomputer

(PC)

• DC-DC convertershave power monitorand control line.

• Route via terminalblock and DB25-pinconnector to externalcontrol computer.

• Individual power-cycle and monitorcapability for eachboard in the system.


39

Correlator (48-station) Floor Plan50 ft

45 ftStation Racks (12)

Air Conditioner

Air Conditioner

Air

Con

ditio

ner

Air

Con

ditio

ner

Air

Con

ditio

ner

Air

Con

ditio

ner

26 ft+14ft = 40 ft = 12.2 m

7 ft

7 ft

3 racks =2 sub-bandcorrelators

Baseline Racks (24)

48 VDCRectifier

Plant(100-150 kW)

48 VDCBatteryPlant

(6.5 ft x26.4 in;767.3

lbs/ft^2)

Fibe

r-op

tics

rack

san

d ot

her

equi

pmen

t

2.5 ft 3 ft

2.5 ft3 ft

2.5 ft

2.5 ft

Possible under-the-floorground plane

• 45 x 50 ft.

• Center Station Racksbecause of cabling.

• 360o access to baselineracks (intra-rack cabling).

• 48 VDC mains supplySingle-point failure, hot-swappable boards andmodules.

• 48 VDC plant. Telephonycentral-office grade. N+nredundant, hot-swappablemodules.


40


41

(One idea of the) Computing EnvironmentStation Board

Baseline Board

FPDP

PC

Phasing BoardStation Board

Station Board Baseline Board

FPDP

PC

PC

Baseline Board

FPDP

PC

Baseline Board

FPDP

Phasing BoardBaseline Board

FPDP

PC

PC

Baseline Board

FPDP

PC

Diskserver

Diskserver

BeowulfCluster

External worldmonitor and control

connection

External worlddata output

connection(s)

PC PC

MASTERSLAVE

SLAVE

MASTER

SLAVE

SLAVE

• Use NRAO “MIB”.VxWorks? Home-brew OS? 100 MbpsEthernet.

• Use Linux PCs fornon-real-time“sophisticated” M&Ccomputing (e.g. modelgeneration)

• Use Linux PCBeowulf clusters forback-end dataprocessing.

• Other solutionsbeing proposed...


42

Summary• 32 delivered stations expandable to 48+ stations.• A few modules need to be developed.• Baseline Board and correlator chip conceptual design is quite

advanced.• Station Board design straightforward, but not as advanced as

the Baseline Board.• System design (racks etc.) fairly conservative. High cabling

density in Baseline Rack requires mock testing.• Full remote control capability, can hot-swap all modules with

semiconductors.• Ideas for computing environment, but not decided...

evla corr codr panel report v6 - national radio astronomy ......adder 4-s ta ion compl exmi r +...

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