epc2218 – enhancement mode power transistor · 2020. 12. 23. · epc2218 – enhancement mode...
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eGaN® FET DATASHEET EPC2218
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 1
EPC2218 eGaN® FETs are supplied only in passivated die form with solder bars. Die Size: 3.5 mm x 1.95 mm
Applications• DC-DC Converters• BLDC Motor Drives• Sync Rectification for
AC/DC and DC-DC• Point of Load Converters
• USB-C• Lidar• Class D Audio• LED Lighting• E-Mobility
Benefits• Ultra High Efficiency• No Reverse Recovery• Ultra Low QG
• Small Footprint
EFFICIENT POWER CONVERSIONG
D
S
HAL
EPC2218 – Enhancement Mode Power Transistor
VDS , 100 VRDS(on) , 3.2 mΩID , 60 A
Maximum Ratings
PARAMETER VALUE UNIT
VDS
Drain-to-Source Voltage (Continuous) 100V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150 °C) 120
ID
Continuous (TA = 25°C) 60A
Pulsed (25°C, TPULSE = 300 µs) 231
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage -4
TJ Operating Temperature -40 to 150°C
TSTG Storage Temperature -40 to 150
Thermal Characteristics
PARAMETER TYP UNIT
RθJC Thermal Resistance, Junction-to-Case 0.5
°C/W RθJB Thermal Resistance, Junction-to-Board 1.4
RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 53Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
# Defined by design. Not subject to production test.
Static Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITBVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.4 mA 100 V
IDSS Drain-Source Leakage VGS = 0 V, VDS = 80 V 0.08 0.35
mAIGSS
Gate-to-Source Forward Leakage VGS = 5 V 0.02 0.5
Gate-to-Source Forward Leakage# VGS = 5 V, TJ = 125°C 0.6 9
Gate-to-Source Reverse Leakage VGS = -4 V 0.06 0.4
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 7 mA 0.8 1.1 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 25 A 2.4 3.2 mΩ
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.5 V
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate.
eGaN® FET DATASHEET EPC2218
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 2
200
150
100
50
00 0.5 1.0 1.5 2.0 2.5 3.0
I D –
Drai
n Cu
rrent
(A)
Figure 1: Typical Output Characteristics at 25°C
VDS – Drain-to-Source Voltage (V)
VGS = 5 VVGS = 4 VVGS = 3 VVGS = 2 V
I D –
Drai
n Cu
rrent
(A)
VGS – Gate-to-Source Voltage (V) 1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 2: Transfer Characteristics
25˚C125˚C
VDS = 3 V
25˚C125˚C
VDS = 3 V
200
150
100
50
0
8
6
4
2
02.5 3.02.0 3.5 4.0 4.5 5.0
R DS(o
n) –
Dra
in-to
-Sou
rce R
esist
ance
(mΩ)
VGS – Gate-to-Source Voltage (V)
Figure 3: RDS(on) vs. VGS for Various Drain Currents
ID = 12 AID = 25 AID = 37 AID = 50 A
2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 4: RDS(on) vs. VGS for Various Temperatures
R DS(o
n) –
Dra
in-to
-Sou
rce R
esist
ance
(mΩ
)
VGS – Gate-to-Source Voltage (V)
25˚C125˚C
VDS = 3 V
25˚C125˚C
ID = 25 A
8
6
4
2
0
Dynamic Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITCISS Input Capacitance#
VDS = 50 V, VGS = 0 V
1189 1570
pF
CRSS Reverse Transfer Capacitance 4.3
COSS Output Capacitance# 562 843
COSS(ER) Effective Output Capacitance, Energy Related (Note 2)VDS = 0 to 50 V, VGS = 0 V
740
COSS(TR) Effective Output Capacitance, Time Related (Note 3) 925
RG Gate Resistance 0.4 Ω
QG Total Gate Charge# VDS = 50 V, VGS = 5 V, ID = 25 A 10.5 13.6
nC
QGS Gate-to-Source Charge
VDS = 50 V, ID = 25 A
3.2
QGD Gate-to-Drain Charge 1.5
QG(TH) Gate Charge at Threshold 1.9
QOSS Output Charge# VDS = 50 V, VGS = 0 V 46 69
QRR Source-Drain Recovery Charge 0# Defined by design. Not subject to production test.Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
eGaN® FET DATASHEET EPC2218
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Capa
citan
ce (p
F)
0 25 50 75 100
Figure 5a: Capacitance (Linear Scale)
VDS – Drain-to-Source Voltage (V)
1600
1400
1200
1000
800
600
400
200
0
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Capa
citan
ce (p
F)
10000
1000
100
10
10 25 50 75 100
Figure 5b: Capacitance (Log Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Figure 6: Output Charge and COSS Stored Energy
Q OSS
– O
utpu
t Cha
rge (
nC)
E OSS
– C O
SS St
ored
Ener
gy (µ
J)80
64
48
32
16
00 20 40 60 80 100
VDS – Drain-to-Source Voltage (V)
3.0
2.4
1.8
1.2
0.6
0.0
Figure 7: Gate Charge
V GS –
Gate
-to-S
ourc
e Vol
tage
(V)
5
4
3
2
1
00 108642
QG – Gate Charge (nC)
ID = 25 AVDS = 50 V
0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
I SD –
Sour
ce-to
-Dra
in Cu
rrent
(A)
VSD – Source-to-Drain Voltage (V)
Figure 8: Reverse Drain-Source Characteristics
200
150
100
50
0
25˚C
VGS = 0 V
125˚C
Figure 9: Normalized On-State Resistance vs. Temperature
Norm
alize
d On
-Sta
te R
esist
ance
RDS
(on)
2.0
1.8
1.6
1.4
1.2
1.0
0.80 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 25 AVGS = 5 V
eGaN® FET DATASHEET EPC2218
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 4
Figure 12: Transient Thermal Response Curves
Figure 10: Normalized Threshold Voltage vs. Temperature
Norm
alize
d Th
resh
old
Volta
ge
1.4
1.3
1.2
1.1
1.
0.9
0.8
0.7
0.6 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 7 mA
1000
100
10
1
0.10.1 1 10 100 1000
I D –
Drai
n Cu
rrent
(A)
VDS – Drain-Source Voltage (V)
Limited by RDS(on)
Pulse Width 1 ms 100 µs
10 µs
Figure 11: Safe Operating Area
tp, Rectangular Pulse Duration, seconds
Z θJB
, Nor
mal
ized T
herm
al Im
peda
nce
0.50.2
0.050.02
Single Pulse
0.01
0.1
Duty Cycle:
Junction-to-Board
Notes:Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
10-5 10-4 10-3 10-2 10-1 1 10+1
1
0.1
0.01
0.001
tp, Rectangular Pulse Duration, seconds
Z θJC
, Nor
mal
ized T
herm
al Im
peda
nce 0.5
Junction-to-Case
Notes:Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
10-6 10-5 10-4 10-3 10-2 10-1 1
1
0.1
0.01
0.001
0.0001
0.2
0.050.02
Single Pulse
0.01
0.1
Duty Cycle:
TJ = Max Rated, TC = +25°C, Single Pulse
eGaN® FET DATASHEET EPC2218
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 5
DIE MARKINGS
DIE OUTLINESolder Bump View
Pad 1 is Gate;Pads 2 ,4, 6, 8 are Source;Pads 3, 5, 7 are Drain;
DIM
Micrometers
MIN Nominal MAX
A 3470 3500 3530B 1920 1950 1980
c 1625
d 1800
e 775
f 250
g 500
h 1025
Side View
DIM Dimension (mm)EPC2218 (Note 1) Target MIN MAX
a 12.00 11.90 12.30b 1.75 1.65 1.85c (Note 2) 5.50 5.45 5.55d 4.00 3.90 4.10e 8.00 7.90 8.10f (Note 2) 2.00 1.95 2.05g 1.50 1.50 1.60
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole.
Part Number
Laser Markings
Part #Marking Line 1
Lot_Date CodeMarking Line 2
Lot_Date CodeMarking Line 3
EPC2218 2218 YYYY ZZZZ
2218YYYY ZZZZ Die orientation dot
Gate Pad bump isunder this corner
518 ±
-25
Seating plane
638
120 ±
12
A
dh
e
B
g
c
f
e2
3 4 5 6 7 8
1
YYYY2218
ZZZZ
TAPE AND REEL CONFIGURATION
Dieorientationdot
Gatesolder bump isunder thiscorner
Die is placed into pocketsolder bump side down(face side down)
Loaded Tape Feed Direction
a
d e
f g
c b
8 mm pitch, 12 mm wide tape on 7” reel
7” inch reel
eGaN® FET DATASHEET EPC2218
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 6
RECOMMENDEDLAND PATTERN (units in µm)
RECOMMENDEDSTENCIL DRAWING (units in µm)
Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing.
Intended for use with SAC305 Type 3 solder, reference 88.5% metals content.
The corner has a radius of R60.
Split stencil design can be provided upon request, but EPC has tested this stencil design and not found any scooping issues.
Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
A
d1h B
g
R60
c1
f1
e1e1
f1 f2 f2
A
d1h B
g
c1
f
e1e12
3 4 5 6 7 8
1
Information subject to change without notice.
Revised June, 2021
Land pattern is solder mask definedSolder mask opening is 180 µmIt is recommended to have on-Cu trace PCB vias
Pad 1 is Gate;Pads 2 ,4, 6, 8 are Source;Pads 3, 5, 7 are Drain;
DIM Nominal
A 3500B 1950c1 1605d1 1780e1 755f 230g 500h 1025
DIM Nominal
A 3500B 1950c1 1605d1 1780e1 755f1 230f2 210g 500h 1025