epc2034c – enhancement mode power transistor...oss(er) is a fixed capacitance that gives the same...

eGaN® FET DATASHEET

EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 1

EPC2034C

EPC2034C – Enhancement Mode Power Transistor

VDS , 200 VRDS(on) , 8 mΩID , 48 A

EPC2034C eGaN® FETs are supplied only inpassivated die form with solder bumps. Die Size: 4.6 mm x 2.6 mm

• High Frequency DC/DC Conversion• Multi-level AC/DC Power Supplies• Wireless Power• Solar Micro Inverters• Robotics• Class-D Audio• Low Inductance Motor Drives

EFFICIENT POWER CONVERSION

HAL

G

D

S

Maximum Ratings

PARAMETER VALUE UNITVDS Drain-to-Source Voltage (Continuous) 200 V

ID

Continuous (TA = 25°C) 48A

Pulsed (25°C, TPULSE = 300 µs) 213

VGS

Gate-to-Source Voltage 6V

Gate-to-Source Voltage -4

TJ Operating Temperature –40 to 150°C

TSTG Storage Temperature –40 to 150

Static Characteristics (TJ= 25°C unless otherwise stated)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.6 mA 200 V

IDSS Drain-Source Leakage VDS = 160 V, VGS = 0 V, TJ = 25°C 0.03 0.4 mA

IGSS

Gate-to-Source Forward Leakage VGS = 5 V, TJ = 25°C 0.002 4 mA

Gate-to-Source Forward Leakage# VGS = 5 V, TJ = 125°C 0.03 9 mA

Gate-to-Source Reverse Leakage VGS = -4 V, TJ = 25°C 0.03 0.4 mA

VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 7 mA 0.8 1.1 2.5 V

RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 20 A 6 8 mΩ

VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.7 V# Defined by design. Not subject to production test.

Thermal Characteristics

PARAMETER TYP UNIT

RθJC Thermal Resistance, Junction-to-Case 0.3

°C/WRθJB Thermal Resistance, Junction-to-Board 4

RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 45

Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details

Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate.

https://www.epc-co.com/epc/Products/eGaNFETsandICs /EPC2034.aspx

https://www.epc-co.com

https://www.epc-co.com/epc/Products/eGaNFETsandICs /EPC2034C.aspx

https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf

eGaN® FET DATASHEET EPC2034C


200

150

100

50

00 1 2 3 4 5 6

I D –

Drai

n Cu

rrent

(A)

Figure 1: Typical Output Characteristics at 25°C

VDS – Drain-to-Source Voltage (V)

VGS = 5 VVGS = 4 VVGS = 3 VVGS = 2 V

20

15

10

5

02.52.0 3.0 3.5 4.0 4.5 5.0

R DS(o

n) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ

)

VGS – Gate-to-Source Voltage (V)

ID = 10 AID = 20 AID = 30 AID = 40 A

Figure 3: RDS(on) vs. VGS for Various Drain Currents

I D –

Drai

n Cu

rrent

(A)

VGS – Gate-to-Source Voltage (V) 1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Figure 2: Transfer Characteristics

200

150

100

50

0

25˚C125˚C

VDS = 3 V

25°C125°C

VDS = 6 V

2.5 2.0 3.0 3.5 4.0 4.5 5.0

Figure 4: RDS(on) vs. VGS for Various Temperatures

R DS(o

n) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ

)

VGS – Gate-to-Source Voltage (V)

25˚C125˚C

VDS = 3 V

25°C125°C

ID = 20 A

20

15

10

5

0

Dynamic Characteristics (TJ= 25˚C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CISS Input Capacitance#

VDS = 100 V, VGS = 0 V

1155 1386

pF

CRSS Reverse Transfer Capacitance 3.1

COSS Output Capacitance# 641 962

COSS(ER) Effective Output Capacitance, Energy Related (Note 2)VDS = 0 to 100 V, VGS = 0 V

755

COSS(TR) Effective Output Capacitance, Time Related (Note 3) 969

RG Gate Resistance 0.5 Ω

QG Total Gate Charge# VDS = 100 V, VGS = 5 V, ID = 20 A 11.1 13.8

nC

QGS Gate to Source Charge

VDS = 100 V, ID = 20 A

3.8

QGD Gate to Drain Charge 2.0

QG(TH) Gate Charge at Threshold 2.1

QOSS Output Charge# VDS = 100 V, VGS = 0 V 96 144

QRR Source-Drain Recovery Charge 0

# Defined by design. Not subject to production test. Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.



All measurements were done with substrate shortened to source. TJ = 25°C unless otherwise stated.

0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

I SD –

Sour

ce-to

-Dra

in Cu

rrent

(A)

VSD – Source-to-Drain Voltage (V)

Figure 8: Reverse Drain-Source Characteristics

200

150

100

50

0

25˚C125˚C

VDS = 3 V

25°C125°C

VGS = 0 V

Figure 7: Gate Charge

V GS –

Gat

e-to

-Sou

rce V

olta

ge (V

)

5

4

3

2

1

00 10 128642

QG – Gate Charge (nC)

ID = 20 A

VDS = 100 V

Figure 9: Normalized On-State Resistance vs. Temperature

Norm

alize

d On

-Sta

te R

esist

ance

RDS

(on)

2.0

1.8

1.6

1.4

1.2

1.0

0.80 25 50 75 100 125 150

TJ – Junction Temperature (°C)

ID = 20 A

VGS = 5 V

Capa

citan

ce (p

F)

0 50 100 150 200

Figure 5a: Capacitance (Linear Scale)


2500

2000

1500

1000

500

0

COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

Capa

citan

ce (p

F)

10000

1000

100

10

10 50 100 150 200

Figure 5b: Capacitance (Log Scale)


COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

Figure 6a: Output Charge and COSS Stored Energy

Q OSS

– Ou

tput

Char

ge (n

C)

E OSS

– C OS

S Sto

red

Ener

gy (μ

J)160

128

96

64

32

0

12.0

9.6

7.2

4.8

2.4

0.050 100 150 200


Figure 6: Output Charge and COSS Stored Energy

0



Figure 12: Transient Thermal Response Curves

tp, Rectangular Pulse Duration, seconds

Z θJB, N

orm

alize

d The

rmal

Impe

danc

e

0.5

0.05

0.02

Single Pulse

0.01

0.10.2

Duty Cycle:

Junction-to-Board

Notes:Duty Factor: D = t1/t2

Peak TJ = PDM x ZθJB x RθJB + TB

PDM

t1

t2

10-5 10-4 10-3 10-2 10-1 1 10+1

1

0.1

0.01

0.001

Z θJC, N

orm

alize

d The

rmal

Impe

danc

e

0.5

0.1

0.02

0.05

Single Pulse

0.01

0.2

Duty Cycle:

Junction-to-Case

Notes:Duty Factor: D = t1/t2

Peak TJ = PDM x ZθJC x RθJC + TC

PDM

t1

t2

10-6 10-5 10-4 10-3 10-2 10-1 1

1

0.1

0.01

0.001

tp, Rectangular Pulse Duration, seconds

Figure 10: Normalized Threshold Voltage vs. Temperature

Norm

alize

d Th

resh

old

Volta

ge

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.60 25 50 75 100 125 150

TJ – Junction Temperature (°C)

ID = 11 mAID = 7 mA

0.1

1

10

100

1000

0.1 1 10 100 1000

I D – D

rain

Curre

nt (A

)

Limited by RDS(on)

Pulse Width

10 µs 1 ms

100 µs

Figure 11: Safe Operating Area

VDS – Drain-Source Voltage (V)TJ = Max Rated, TC = +25°C, Single Pulse



2034YYYYZZZZ

Die orientation dot

Gate Pad bump isunder this corner

Part Number

Laser Marking

Part #Marking Line 1

Lot_Date CodeMarking Line 2

Lot_Date CodeMarking Line 3

EPC2034C 2034 YYYY ZZZZ

DIE MARKINGS

DIE OUTLINESolder Bump View

Side View

DIMMicrometers

MIN Nominal MAX

A 4570 4600 4630B 2570 2600 2630c 1000 1000 1000d 500 500 500e 285 300 315f 332 369 406

510 t

yp

Seating plane

79

0 typ

280+

/−28

B

A

cX4

e

e

155 10 20

d X4

f

1

166 11 212

177 12 22

188 13 233

199 14 244

2034YYYYZZZZ

TAPE AND REEL CONFIGURATION4 mm pitch, 12 mm wide tape on 7” reel

7” reel

a

d e f g

c

b

Note 1: MSL 1 (moisture sensitivity level 1) classi�ed according to IPC/JEDEC industry standard.Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole.

Dieorientationdot

Gatesolder bump isunder thiscorner

Die is placed into pocketsolder bump side down(face side down)

Loaded Tape Feed Direction

Dimension (mm) target EPC2034C (note 1)

min max a 12.00 11.70 12.30 b 1.75 1.65 1.85

c (note 2) 5.50 5.45 5.55 d 4.00 3.90 4.10 e 4.00 3.90 4.10

f (note 2) 2.00 1.95 2.05 g 1.5 1.5 1.6

Pads 1 and 2 are Gate;

Pads 5, 6, 7, 8, 9, 15, 16, 17, 18, 19 are Drain;

Pads 3, 4, 10, 11, 13, 14, 20, 21, 22, 23, 24 are Source;

Pad 12 is Substrate*

*Substrate pin should be connected to Source



Information subject to change without notice.

Revised August, 2019

RECOMMENDEDLAND PATTERN (units in µm)

Land pattern is solder mask definedSolder mask opening is 330 µmIt is recommended to have on-Cu trace PCB vias

2600

4600

1000X4

300

300

500

X4330

155 10 201

166 11 212

177 12 22

188 13 233

199 14 244

RECOMMENDEDSTENCIL DRAWING (units in µm)

RECOMMENDEDSTENCIL DRAWING (units in µm)

Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing.

Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx

Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing.

Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx

2600

4600

1000X4

300

300

500

X4

330

2600

4600

1000300

300

500

300

350

Option 1 : Intended for use with SAC305 Type 4 solder.

Option 2 : Intended for use with SAC305 Type 3 solder.

Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

eGaN® is a registered trademark of Efficient Power Conversion Corporation.EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx

Pads 1 and 2 are Gate;

Pads 5, 6, 7, 8, 9, 15, 16, 17, 18, 19 are Drain;

Pads 3, 4, 10, 11, 13, 14, 20, 21, 22, 23, 24 are Source;

Pad 12 is Substrate*

*Substrate pin should be connected to Source

https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx

https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx

https://www.epc-co.com/epc/AboutEPC/Patents.aspx

epc2034c – enhancement mode power transistor...oss(er) is a fixed capacitance that gives the same...

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