Enhanced SAR ADC Energy Efficiency from the Early Reset

Merged Capacitor Switching Algorithm

Jon Guerber, Hariprasath Venkatram, Taehwan Oh, Un-Ku Moon

Oregon State University, Corvallis OR, USA

EMCS SAR Outline

• MCS SAR Background

• EMCS SAR Switching Power

• EMCS Linearity

• Implementation Techniques

• Conclusions

2

SAR Motivation

• SAR Contributions– Low Power– Scalable– Low FOM even at

small process nodes– Primarily dynamic

power

• Current SAR Design Issues– DAC takes a large portion of the SAR power budget– Without calibration DAC size (and power) is often

based on mismatch concerns

SAR

DAC Driver

DAC Driver

Cap DAC

Cap DAC

VIN

DOUT

3

Merged Capacitor Switching SAR

• Merged Capacitor Switching (MCS) – Sampling reference

is initially Vcm

– Minimizes switching power by switching only once per phase

– Maintains virtual node common mode

[1] [Hariprasath 2010][2] [Zhu 2010]

C2^(N-3)C2^(N-2)C

VINP

SAR

DACP

VT

DACN

VINN

C2^(N-3)C2^(N-2)C

VCM

VCMVDD

VDD

4

MCS SAR Switching

• MCS Switching– Differential– Each phase, current

cap charges to VDD or GND

– In the end, all caps have either VDD or GND on bottom plate

– Switching energy based on code

5

VIN+-

VCM VCM VCM

VCM VCM VCM

VDD VCM VCM

GND VCM VCM

GND VCM VCM

VDD VCM VCM

VDD VDD VCM

GND GND VCM

VDD GND VCM

GND VDD VCM

GND VDD VCM

VDD GND VCM

GND GND VCM

VDD VDD VCM

EVDD = (½)CVDD²

2C

2C C C

C C

2C

2C C C

C C

2C

2C C C

C C

2C

2C C C

C C

2C

2C C C

C C

2C

2C C C

C C

2C

2C C C

C CEVDD = (1/8)CVDD²

EVDD = (5/8)CVDD²

EVDD = (½)CVDD²

EVDD = (5/8)CVDD²

EVDD = (1/8)CVDD²

Φ1 Φ2

MCS SAR Switching

6

VIN+-

VCM VCM VCM

VCM VCM VCM

VDD VCM VCM

GND VCM VCM

GND VCM VCM

VDD VCM VCM

VDD VDD VCM

GND GND VCM

VDD GND VCM

GND VDD VCM

GND VDD VCM

VDD GND VCM

GND GND VCM

VDD VDD VCM

EVDD = (½)CVDD²

2C

2C C C

C C

2C

2C C C

C C

2C

2C C C

C C

2C

2C C C

C C

2C

2C C C

C C

2C

2C C C

C C

2C

2C C C

C CEVDD = (1/8)CVDD²

EVDD = (5/8)CVDD²

EVDD = (½)CVDD²

EVDD = (5/8)CVDD²

EVDD = (1/8)CVDD²

Φ1 Φ2

MSBVDD DD MSB DD

T

2Unit DD

MSB-1VDD DD MSB-1 DD

T

2MSB-1VDD DD

T

2Unit DD

C1E = - V C V

2 2C

C V=

2

C1E = - V C V

2 2C

C+C V

2C

5C V=

8

1

2

For :

For 10 :

EMCS SAR Switching

• EMCS Switching– Differential– Any {10} transition

is replaced by {VCM,1}

– Alternating code transitions have significantly lower energy

– No extra switching events happen since all caps are reset eventually

7

VIN+-

VCM VCM VCM

VCM VCM VCM

VDD VCM VCM

GND VCM VCM

GND VCM VCM

VDD VCM VCM

VDD VDD VCM

GND GND VCM

VCM VDD VCM

VCM GND VCM

VCM GND VCM

VCM VDD VCM

GND GND VCM

VDD VDD VCM

EVDD = (½)CVDD²

2C

2C C C

C C

2C

2C C C

C C

2C

2C C C

C C

2C

2C C C

C C

2C

2C C C

C C

2C

2C C C

C C

2C

2C C C

C CEVDD = (1/8)CVDD²

EVDD = (3/8)CVDD²

EVDD = (½)CVDD²

EVDD = (3/8)CVDD²

EVDD = (1/8)CVDD²

Φ1 Φ2

EMCS SAR Switching

8

VIN+-

VCM VCM VCM

VCM VCM VCM

VDD VCM VCM

GND VCM VCM

GND VCM VCM

VDD VCM VCM

VDD VDD VCM

GND GND VCM

VCM VDD VCM

VCM GND VCM

VCM GND VCM

VCM VDD VCM

GND GND VCM

VDD VDD VCM

EVDD = (½)CVDD²

2C

2C C C

C C

2C

2C C C

C C

2C

2C C C

C C

2C

2C C C

C C

2C

2C C C

C C

2C

2C C C

C C

2C

2C C C

C CEVDD = (1/8)CVDD²

EVDD = (3/8)CVDD²

EVDD = (½)CVDD²

EVDD = (3/8)CVDD²

EVDD = (1/8)CVDD²

Φ1 Φ2

MSBVDD DD MSB DD

T

2Unit DD

MSB-1VDD DD MSB-1 DD

T

2Unit DD

C1E = - V C V

2 2C

C V=

2

C1E = - V C V

2 2C

3C V=

8

1

2

For :

For 10 :

Switching Energy Comparison

9

• EMCS Energy Savings– 12.5% Lower energy

over MCS– 18.4% Lower energy

over MCS when MCS is Gaussian distributed

– 41.5% Lower energy then set-and-down approach [3]

– Even more energy savings is input PDF is concentrated in center

EMCS Static Linearity

• MCS worst case DNL transition: {1,0,0,0 …} to {0,1,1,1 …}

• EMCS worst case DNL transition: {1,VCM, VCM, VCM …} to {VCM,1,1,1 …} and {0,VCM, VCM, VCM …} to {VCM,0,0,0 …}

• Variance of virtual ground node charge due to worst case code cap matching is ½

• DNL reduced by factor of 2 10

EMCS Integral Non-Linearity

11

• EMCS INL– INL reduced by

factor of 2– Middle code is when

all bits are VCM,

hence INL = 0 there– INL Simulation

performed with unit cap sigma of 0.02 LSB and 10,000 runs

– Reduces size of a matching limited DAC, saves power

EMCS Switching AlgorithmFor (Stage = 1) if Comp = 1 b1 = 1 else b1 = 0 endend

For (Stage = 2:End) if CompN = b1

b(n) = b1

else b(n-1) = VCM

b(n) = b1

endend 12

• EMCS Switching Algorithm– All final bits end up as either

VCM or {b1}– In every phase, b(n) = b1– In each phase, comparator only

dictates whether to reset capacitor b(n-1) or not

EMCS Logic Implementation

13

• EMCS Implementation– Efficient AOI gate resets data latches

VGP

VGN

A

B

MU

X

LATD Q

Rb

AOI

LATQ D

RbΦ1

LATD Q

Rb

LATQ D

Rb Φ1

B1

B1b

LATD Q

Rb

AOI

LATD Q

Rb

B1

B1b

Φ2

Φ2

b1

b1b

Φ2

RST

b2

b2b

LATD Q

Rb

AOI

LATD Q

Rb

B1

Φ3

Φ3

Φ3

RST

b3

b3bB1b

Φ4

RST

EMCS SAR Summary

• Power Reduction–Switching energy reduction without additional driver energy and minimal logic

• Accuracy Improvements–Static linearity improvement, relaxed matching

• Implementation Method–Low overhead implementation utilizing latch resetting

14

Questions

15

References

[1] V. Hariprasath, J. Guerber, S.-H. Lee, U. Moon, “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” Electron. Lett., vol. 46, pp. 620-621, Apr. 2010.

[2] Y. Zhu, C.-H. Chan, U. Cho, S.-W. Sin, S.-P. U, R. Martins, F. Maloberti, “A 10-bit 100-MS/s reference-free SAR ADC in 90nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111-1120, Jun. 2010.

[3] B. Ginsburg and A. Chandrakasen, “An energy efficient charge recycling approach for a SAR converter with capacitive DAC,” Proc. of IEEE Int. Sym. On Circuits and Systems, ISCAS, pp. 184-187, 2005.

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