emerging memory device technologies -...

Emerging Memory Device Technologies

The 49th Annual IEEE/ACM Intl. Symp. on Microarchitecture, 2016

Tutorial on Existing and Emerging Memory Technologies and Circuits

Darsen D. Lu, Assistant ProfessorNCKU, Tainan, Taiwan

[email protected]

2016/10/16

mailto:[email protected]

Outline

• Introduction

• Phase Change Memory Devices

• Spin-torque Transfer Memory Devices

• Resistive Memory Devices

• 3D Integration

• SummaryMicro-49 Tutorial on Emerging Memory

Devices (Darsen Lu) 2

Data Explosion and Storage Requirements

• High density, high performance memory technology required to store even-increasing amount of data.

http://electronicdesign.com/power/software-and-system-solutions-drive-datacenter-energy-efficiencyCisco Systems forecasts that annual datacenter traffic will reach 6.6 zettabytes (1021 bytes) by the end of 2016 with a CAGR of 31% from 2011 to 2016. The chart uses exabytes (1 exabyte = 1018 bytes) on its Y axis (Cisco Systems Global Cloud Index).

Micro-49 Tutorial on Emerging Memory Devices (Darsen Lu) 3

http://electronicdesign.com/power/software-and-system-solutions-drive-datacenter-energy-efficiency

Emerging Memory Device Technologies

Conductor

Conductor

ConductiveFilament

Conductor

Conductor

AmorphousGeSbTe

CrystallineGeSbTe

SiO2SiO2

Free Layer

Pinned Layer

Magnetic Tunnel Jct.

Phase Change Memory(PCM)

Spin-torque Transfer(STT-MRAM)

Resistive Memory(RRAM)

OxRAM, CBRAMMicro-49 Tutorial on Emerging Memory


Focus of Tutorial

• Device Operation and Physical Mechanism• Figure of Merits of each memory type• Key technological challenges• Bridge to circuit/architecture level


http://myweb.ncku.edu.tw/~darsenlu/papers/micro16_emerging_mem_tutorial_darsen.pdf

Slides currently available at:

http://myweb.ncku.edu.tw/%7Edarsenlu/papers/micro16_emerging_mem_tutorial_darsen.pdf

PCM STT-MRAM

RRAM NANDFlash

DRAM

Power Ewrite/ BitIwrite

18pJ [15]1

100µA [15]1.0pJ [20]50µA [33]

1.0pJ [20] 1.0µA [18]

100pJ [31] <1.0 pJ [9]

Perform-ance2

Write Lat. 150ns [15] 5ns [6] 50ns [20] >100µs 5ns [27]

Read Lat. 80ns [28] 10ns [5] <10ns [30] 15-50µs [35] 20–80ns [35]

Reliabi-lity

Program Window

3 bit/cell [12]

Good [3] Variable [23]

4 bit/cell [32]

Good

Endurance 108-109

[4,9]Unlimited[1]

105-1010

[1]105-106 [8] Unlimited

Retention R-drift[12] Good [6] RTN [24] Good 64msDensity Cell size 4 F2 [15] 12 F2 [33] 4-6F2 [21] <4 F2 [15] 7 F2 [15]

1. Estimated using I_reset * Vdd * t_write2. Required programming pulse duration

Emerging Memory Technologies(Speed of DRAM; Non-volatility of NAND)

Emerging Memory Technology Metrics


Storage Capacity

H.-S. P. Wong, C. Ahn, J. Cao, H.-Y. Chen, S. W. Fong, Z. Jiang, C. Neumann, S. Qin, J. Sohn, Y. Wu, S. Yu, X. Zheng, H. Li, J. A. Incorvia, S. B. Eryilmaz, K. Okabe, “Stanford Memory Trends,” https://nano.stanford.edu/stanford-memory-trends, accessed October 12, 2016.


https://nano.stanford.edu/stanford-memory-trends/

Outline

• Introduction




• 3D Integration



Phase Change Material

• GeSbTe (GST)• Phase Change Material

• Often used in rewritable DVDs

• High R in amorphous state• Low R in crystalline state

Conductor

Conductor

AmorphousGeSbTe

CrystallineGeSbTe

SiO2SiO2

http://www.pcmag.com/encyclopedia/term/58619/phase-change-discMicro-49 Tutorial on Emerging Memory


http://www.pcmag.com/encyclopedia/term/58619/phase-change-disc

Phase Change Memory Operation

“SET” State “RESET” State

Heater

Amorphous GST

• Short RESET current pulse melts GST (~600C) and amorphous-ize it

• Longer SET current pulse crystallize GST (~300C)

G. W. Burr, et al., J. Vac. Sci.Technol. B 28, 223 (2010) (IBM) /Breitwisch, Phase Change Materials: Science and Applications. © 2009 by Springer.


PCM Reset Current Challenge & Solution• Reset operation requires melting of GST

• Power / write bandwidth limitation (on par with NAND)• Transistor select device current requirement (~ 100µA !)

• 1.6mA/µm current drive @ 20nm ?

• Reset current scales with contact dimension[11] F. Xiong et al., Science 2011

CNT Contact Diameter ~ 3nm

[14] P. Wong et al., IEEE Proc. 2010

[11]

Ireset ~ 5µA


PCM: Resistance Drift Issue• PCM resistance drifts with time

• Challenging to separate multiple programmed states.• Reading/writing “eM-metric” makes PCM states less

susceptible to R-drift.D. Ielmini, et al., IEDM 2007 (Politech. de Milano) M. Stanisavljevic et al., IMW 2016 (IBM)


PCM: Multiple Bits Per Cell• 3-4 bits per cell successfully implemented in PCM

technologies despite R-drift phenomenonT. Nirschl, et al., IEDM 2007(IBM/MXIC/Quimonda)M. Stanisavljevic et al., IMW 2016 (IBM)


PCM: Endurance• In general, PCM endurance is said to be around

108 – 109 switching cycles. However, numerous reports exist with endurance around 1010 - 1011.

• Its ability to replace DRAM still questionable.M. Brightsky et al., IEDM 2015 (IBM) D. H. Im et al., IEDM 2008 (Samsung)


PCM Chip Demonstrations• 8Gb demonstration is the largest so far, with cell

size of 4F2 or 41nm x 41nm.• 40MB/s program bandwidth• DRAM Interface• Diode selector• No MLC

Youngdon Choi et al., ISSCC 2012(Samsung)

Micro-49 Tutorial on Emerging Memory Devices (Darsen Lu) 15Ireset ~ 100uA

PCM STT-MRAM

RRAM NANDFlash

DRAM


18pJ [15]1

100µA [15]1.0pJ [20]50µA [33]

1.0pJ [20] 1.0µA [18]

100pJ [31] <1.0 pJ [9]

Perform-ance2



Reliabi-lity

Program Window

3 bit/cell [12]


4 bit/cell [32]

Good

Endurance 108-109

[4,9]Unlimited[1]

105-1010

[1]105-106 [8] Unlimited



PCM Metrics


PCM Scalability and Summary

• PCM device is a very well studied.• Key challenge is to reduce reset(write) current,

contact dimension scaling will help.• DRAM / SRAM replacement may be challenging

due to fundamental endurance limitation.• With the low latency, can we use PCM as

embedded NVM for SoC , or replace NOR flash ?• Does speed advantage over NAND justify PCM as

candidate for the new “storage class memory” ?Micro-49 Tutorial on Emerging Memory


Storage Class Memory


PCM For Neuromorphic Applications• Non-volatile memory like PCM can be used in

neuromorphic computing at very low power compared to von-Neumann implementations.

G. Burr et al., IEDM 2015 (IBM)Micro-49 Tutorial on Emerging Memory


Outline

• Introduction




• 3D Integration



Tunneling Magnetic Resistance• Electrons tunnel quantum

mechanically across barrier• Larger current when two layers

polarized in same direction

Free Layer

Pinned Layer


J. Zhu et al., Materials Today 2006 (CMU)


Magnetic Storage: Historic Perspective

Magnetic Core Memory (1953) Magnetic Tape (1928-)

FlyingHeight 1-3nm

Hard Disk (1956 – )


“Conventional” MRAM: Field Induced Switching• Principle: pass current along wire

above free layer to induce magneticfield switching

• Issue:• Large current required• Neighbor cell Interference low density

• In fact, at state-of-the-artdimensions the required current already exceedselectromigration limit 100 mA/µm2

I

T. Devolder et al., IEDM Short Course 2015


Spin-torque Transfer (STT) MRAM

Micro-49 Tutorial on Emerging Memory Devices (Darsen Lu)

24

Free Layer

Pinned Layer


• Writing “0”• The pinned layer has fixed magnetic field direction

• Electrons flowing through pinned layer becomespin polarized

• Spin polarized electrons thatflows into the free layeralter its magnetization (viaangular momentum transfer)

Spin-polarized current

• Writing “1”• Quantum mechanical tunneling of electrons that has

angular momentum same asthat in the pinned layer isgoes across the MTJ

• Electrons with the oppositespin accumulate in the freelayer and changes itsmagnetization to becomeopposite to the pinned layer

Spin-torque Transfer (STT) MRAM

Micro-49 Tutorial on Emerging Memory Devices (Darsen Lu)

25

Free Layer

Pinned Layer


Ref: “Spin Torque for Dummies”, Presented at Intermag 2007, Tom Silva

NIST, Boulder

STT-MRAM: Sub-10ns Read/write Latency & Infinite endurance• Read/write latency < 5-10ns typical for STT-MRAM• Only electron flow & magnetization change DRAM/SRAM like ~infinite endurance


10ns write pulse

50ns write pulse

Vc: write voltage

J. J. Nowak et al., IEEE Mag. Lett., vol. 2, 2011

D. C. Worledge et al., IEDM 2010

MRAM Scaling

• Magnetic-Field-Based MRAM occupies 20-30F2

• STT-MRAM occupies as small as 6-8F2

• Multiple-level cell (MLC) difficult due to relatively small R-window & binary switching



Jan et al., 2014 VLSI Symp. (TDK)

MRAM Process Complexity

• 47 Layers !!• Thick, stable

reference(fixed)layer

• Buffer layersto ensure stoichiometry

• Magnetic hardlayers

• Etching of theselayers are difficult



PCM STT-MRAM

RRAM NANDFlash

DRAM


18pJ [15]1

100µA [15]1.0pJ [20]50µA [33]

1.0pJ [20] 1.0µA [18]

100pJ [31] <1.0 pJ [9]

Perform-ance2



Reliabi-lity

Program Window

3 bit/cell [12]

1 bit [3] Variable [23]

4 bit/cell [32]

Good

Endurance 108-109

[4,9]Unlimited[1]

105-1010

[1]105-106 [8] Unlimited



STT-MRAM Metrics


STT-MRAM Scalability and Summary• STT-MRAM has most properties of an ideal

memory, including non-volatility and speed.

• Density may not be competitive as others.

• STT-MRAM endurance similar to DRAM/SRAM. Can it replace eDRAM or SRAM in SoC ?

• MLC is difficult. Process complexity may lead to higher cost. Can it still replace NAND?


Outline

• Introduction




• 3D Integration



Resistive Memory Devices

• Specific oxides can form conductive filaments, which reduces its resistance

• Reversible operation

Conductor

Conductor

ConductiveFilament

D. Ielmini et al., IEDM Short Course 2015Micro-49 Tutorial on Emerging Memory


RRAM Operation

Conductor

Conductor

Conductor

Conductor

Conductor

Conductor

ConductiveFilament (CF)

FORMINGRESETSET


RRAM Operation : Bipolar Switching• For bipolar switching RRAM devices, a positive

voltage sets it to low resistance state; a negative voltage resets the device.

D. Ielmini et al., IEDM Short Course 2015Lin et al., APL 2016


RRAM: Power Consumption• Programming current

<1µA possible• Write energy < 0.1pJ

• Cf: NAND ~ 100pJ

Wu et al., EDL 2010

100 101 102 103 104 105 106 107 108 109 1010 101110-15

10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

Baek '04 Chen '05 Lee '06 Tsunoda '07 Wei '08 Lee '08 Lee '09 Chen '09 Tseng '09 Sakotsubo '10 Ho '10 Chien '10l Lee '10 Yi '11 Kim '11 Govoreanu '11 Chen '12 Wang '12 Shen '12 Lee '12 Chien '12 Goux '12 Kim '12 Chen '12 Hsu '13 Govereanu '13 Hsu '13 Wu '13 Li '14 Sekar '14 Pan '15 Jo '14 Zhao '14 Govoreanu '15 Li '16 Govoreanu '16

Writ

e E

nerg

y (J

)

Cell Area (nm2)

1.1 11.3 112.8 1.1k 11.3k 112.8k

Equivalent Contact Diameter (nm)

0.1 pJ

1 µA


RRAM: Variability Issue• CF formation is of random nature. Therefore,

RRAM typically has broad resistance distribution• Increase write current Large CF less variation

A. Fantini et al., IMW 2013 (IMEC)

Cell-to-cell variation Single-cell variation


RRAM: Random Telegraphic Noise• Resistance distribution affected by

discrete events at atomic level

D. Ielmini et al., IEDM Short Course 2015

S. Balatti et al., IRPS 2014


CBRAM: Improved Resistance Window and Retention• CBRAM, or metal-ion

based RRAM• Larger R-window

(Variability-resistant)• Improved retention

Alessandro Calderoni et al., IMW 2014 (Micron)

CBRAM

CBRAM

CBRAMOXRAM

OXRAMOXRAM


PCM STT-MRAM

RRAM NANDFlash

DRAM


18pJ [15]1

100µA [15]1.0pJ [20]50µA [33]

1.0pJ [20]1.0µA [18]

100pJ [31] <1.0 pJ [9]

Perform-ance2



Reliabi-lity

Program Window

3 bit/cell [12]


4 bit/cell [32]

Good

Endurance 108-109

[4,9]Unlimited[1]

105-1010

[1]105-106 [8] Unlimited



RRAM (CBRAM) Metrics


RRAM Scalability and Summary

• RRAM is highly scalable and requires low write current. 32Gb demonstration with 4F2 cells

• Cell-to-cell, cycle-to-cycle variability, and RTN noise are the main challenge. Variability gets worse with scaling.

• Conductive bridge RAM (CBRAM) with large R-window mitigates variability impact.

• MLC difficult due to variability. Extensive material investigation on-going.


RRAM Application: Neuromorphic • Trained RRAM devices used for

recognizing hand-written digits• Resistance represents matrix

coefficientS. Yu et al., IEDM 2015


RRAM Application: Security• Physically Unclonable Function (PUF) implemented

with RRAM by taking advantage of its randomnature

R. Liu et al., EDL 2015


Outline

• Introduction




• 3D Integration



• Vertical NAND string available as real products.

3D NAND for High-Density Storage


K. Parat et al., IEDM 2015(Intel / Micron)

256Gb MLCVertical NAND32 layers

K. T. Park et al., JSSC 2015(Samsung)

128Gb MLCVertical NAND24 layers

3D Emerging Memory • To scale emerging memory technology to 3D,

several prototypes are demonstrated


M.-C. Hsieh et al., IEDM 2013(TSMC)

3D RRAM 3D PCM

M. Kinoshita et al, VLSI Tech., 2012(Toshiba)

Selection Diode Requirements

• Diodes or transistors prevent sneak path in crossbar architecture


ITRS Emerging Research Device ReportEmerging Memory Select Device WorkshopApril 22, 2012,

Selection Diode for 3D Integration


M. Kinoshita et al, VLSI Tech., 2012

Poly-Si Diode MEIC Diode

K. Gopalakrishnanet al., VLSI 2010

MIM Diode (Bidirectional)

I-Hsuan ChenM.S. Thesis

MIM Diode (Unidirectional)

J. J. HuangAPL 2010

Ti/TiO2/Ni

3D Integration Summary

• 3D Integration is required to continue scaling NVM

• 3D NAND has been demonstrated in product

• 3D emerging memory requires selection diode with excellent on-off current ratio and sufficiently low processing temperature. Candidates include

• MEIC diode• MIM diode


Summary of Applications and ChallengesTechnology Key Challenges Possible ApplicationsPCM Large reset current

Selector for 3D PCMNAND replacementStorage class memoryEmbedded NVMNeuromorphic

RRAM VariabilitySelector for 3D RRAM

Embedded NVMPUFNeuromorphic

STT-MRAM Cell sizeProcess Complexity

SRAMEmbedded DRAMOff-chip DRAM


References

[1] Yuan Xie, “Emerging Memory Technologies Design, Architecture and Applications,” Chapter 1, Springer, 2014

[2] J. J. Nowak et al., IEEE Magnetics Letters, 2011[3] D. Worledge et al., IEDM 2010[4] P. Zhou et al., Proc. ISCA, 2009[5] Tsuchida et al., ISSCC 2010[6] G. Jan et al., Symp. VLSI Tech., 2014[7] Xu et al., HPCA 2015[8] Yuan Xie, “Emerging Memory Technologies Design, Architecture and

Applications,” Chapter 2, Springer, 2014[9] B. C. Lee, Proc. ISCA, 2009


References

[10] J. Wu et al., IEDM 2011[11] F. Xiong, Science, Vol. 332, Apr. 2011[12] M. Stanisavljevic, IMW 2016

[13] D. H. Im, IEDM 2008[14] H. S. P. Wong, Proc. IEEE, 2010[15] Choi et al., ISSCC 2012[16] Yuan Xie, “Emerging Memory Technologies Design, Architecture and

Applications,” Chapter 6, Springer, 2014[17] S. Venugopalan et al., VLSI-TSA, 2011[18] Y. Wu et al., EDL 2010[19] Rizzo et al., IEEE Tran. On Magnetics, 2013


References

[20] H.-S. P. Wong, C. Ahn, J. Cao, H.-Y. Chen, S. W. Fong, Z. Jiang, C. Neumann, S. Qin, J. Sohn, Y. Wu, S. Yu, X. Zheng, H. Li, J. A. Incorvia, S. B. Eryilmaz, K. Okabe, “Stanford Memory Trends,” https://nano.stanford.edu/stanford-memory-trends, accessed October 12, 2016.

[21] Tz-Yi Liu et al., JSCC 2014[22] J. Y. Scharlotta et al., IIRW 2014[23] A. Fantini et al., IMW 2013[24] S. Ambrogio, IEDM 2014[25] A. Calderoni, INFOS 2015[26] D. Ielmini et al., Materials Today 2011[27] D. Ielmini et al., IEDM Short Course 2015


References

[28] K. J. Lee et al., JSSC 2008[29] L. M. Grupp et al., ISM 2009[30] S. S. Sheu et al., ISSCC 2011[31] R. Atiken et al., IEDM Short Course 2015[32] Cuong et al., NVMW 2010[33] Ikegami et al, IEDM 2014[34] Ahn, S. J. et al., IEDM 2004[35] C. Y. Lee et al., IEDM Short Course 2015[36] G. Burr et al., J. Vac. SC. 2010


Supplementary Materials


PCM: Crystallization Temperature

Cheng et al., IEDM 2011 (IBM / Macronix)


Chip-Level Power/Performance for Emerging NVM

MemoryTechnology

ChipSize

Read Latency

WriteLatency

Write Energy

50nm NAND Flash [29] 2 Gb 25.2 µs 200.1 µs 4.24 µJ

90 nm Phase Change (PCM) [28]

512 Mb 59.76 ns 438.55 ns 47.22 nJ

65nm Spin-torqueTransfer (STT-MRAM) [5]

64 Mb 11.47 ns 27.50 ns 0.26 nJ

Resistive (RRAM) [30] 4 Mb 7.72 ns 6.56 ns 0.46 nJ

Xiangyu Dong, Cong Xu, Norm Jouppi and Yuan Xie, “NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Non-volatile Memory,” a chapter in Emerging Memory Technologies Design, Architecture, and Applications, Springer, 2014


Memory Comparison

• J. J. Yang, Nature Nano 2013


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