eet 252 unit 4 programmable logic: splds & cplds read floyd, sections 11-1 to 11-4. study unit...

EET 252 Unit 4Programmable Logic: SPLDs & CPLDs

Read Floyd, Sections 11-1 to 11-4. Study Unit 4 e-Lesson. Do Lab #4.

Homework #4 and Lab #4 due next week.

Quiz next week.

© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th ed

Programmable Logic

SPLD (Simple PLD): the earliest type of array logic used for fixed functions and smaller circuits with a limited number of gates. (The PAL and GAL are both SPLDs).

CPLD (Complex PLD): contain multiple SPLD arrays and inter-connection arrays on a single chip.

FPGA (Field Programmable Gate Array): a more flexible arrangement than CPLDs, with much larger capacity.

Programmable Logic Devices (PLDs) are chips with a large number of gates and flip flops that can be configured with software to perform a specific logic function or perform the logic for a complex circuit. Major types of PLDs are:


Programmable Logic

Advantages of PLDs over fixed-function chips include

Reduced complexity of circuit boards• Lower power requirements• Less board space• Simpler testing procedures

Higher reliability Design flexibility

Approximate Equivalent Densities

The Lattice GAL22V10 (a popular SPLD) is equivalent to about 500 logic gates.

A typical Altera MAX7000 CPLD is equivalent to about 2500 logic gates.

A typical Altera Cyclone FPGA is equivalent to about 50,000 gates.

Major PLD Manufacturers

Three big names in this field are Xylinx, with 51% of market shareAltera, with 34%Lattice, with less than 10%

Market share numbers retrieved from Wikipedia on 10/26/2011.

http://en.wikipedia.org/wiki/Xilinx

Some Product Lines from Altera and Xylinx

AlteraCPLDs: MAXFPGAs: Cyclone, Arria, StratixProgramming software: Quartus II

Xylinx:CPLDs: CoolRunner, XC9500FPGAs: Vertix, Spartan, Kintex, ArtixProgramming software: ISE


PALs and GALs

PALs have a one-time programmable (OTP) array, in which fuses are permanently blown, creating the product terms in an AND array.

All PLDs contain arrays. Two important kinds of SPLD are PALs (Programmable Array Logic) and GALs (Generic Array Logic). A typical array consists of a matrix of conductors connected in rows and columns to AND gates.

Simplified AND-OR array

X

A A B B


X

A A B B

What function is represented by the array?

The function represents an XOR gate.

X = AB + AB

PALs are programmed with a specialized programmer that blows selected internal fuse links. After blowing the fuses, the array represents the Boolean logic expression for the desired circuit.

PALs


The GAL (Generic Array Logic) is similar to a PAL but can be reprogrammed. For this reason, they are useful for new product development (prototyping) and for training purposes.

A A B B

X

GALs were developed by Lattice Semiconductor.

GALs


PALs and GALs are often represented by simplified diagrams in which a single line represents multiple gate inputs. The logic shown is for the XOR gate, given previously.

X

X

X

X

2

2

Input buffer A A B BSingle line with slash indicating multiple AND gate inputs

Fuse blown

Fuse intact

AB

AB

AB + AB

PALs and GALs


The AND-gate arrays in PALs and GALs connected to macrocells. A macrocell is an OR gate together with associated output logic. Two types of PAL/GAL macrocells are shown. For these particular macrocells, the I/O pin can serve as an input or an output.

Tristate control

From AND array

From AND array

I/O I/O

Programmable fuse link to control output polarity

To AND array

To AND array

PALs and GALs


The GAL22V10 is a typical SPLD. It has 12 dedicated inputs pins and 10 pins that can be used as inputs or outputs.

Link to datasheet

GAL22V10

http://people.sinclair.edu/nickreeder/eet131/gal22v10.pdf


CPLDsA complex programmable logic device (CPLD) has multiple logic array blocks (LABs), each roughly equivalent to an SPLD. LABs are connected via a programmable interconnect array (PIA). Various CPLDs have different structures for these elements.

I/O

PIA

I/O

I/O I/O

I/O I/O

Logic arrayblock (LAB)

SPLD


SPLD


SPLD


SPLD


SPLD


SPLD

The PIA is the interconnection between the LABs.


CPLDsThe architecture of a CPLD is the way in which the internal elements are configured. A portion of the Altera MAX 7000 series is shown. This structure is typical for CPLDs, but densities and features (macrocells, etc) will vary between manufacturers.

I/O pins I/O pins

General-purpose inputs

8-168Ð16 36

16

I/Ocontrolblock

Logic array block(LAB A)

36

16

I/Ocontrolblock

Macrocell 1

Macrocell 2

Macrocell 16

Logic array block(LAB B)

Macrocell 1

Macrocell 2

Macrocell 16

8-168-16

PIA


CPLDsMacrocells in the Altera MAX 7000 series can generate up to five product terms. For expressions requiring more terms, the output can be expanded as described in the text.

15 expanderproduct termsfrom othermacrocells

36 lines from PIA

Sharedexpander

Parallel expandersfrom othermacrocells

Associatedlogic

To I/Ocontrolblock

Product-termselectionmatrix

ABC ABC(E + F)=ABCE + ABCF

E + FEF Product term from another

macrocell in same LAB

Expander example


CPLD Macrocells

In addition to combinational logic, many macrocells have registered outputs available (using programmable flip-flops). This allows the CPLD to perform sequential logic.

15 expander productterms from othermacrocells

36 linesfrom PIA

Sharedexpander

Parallel expandersfrom othermacrocells

To I/O

Product-term

selectionmatrix

D/T

C

EN

PRE

CLR

QMUX 1

MUX 2

MUX 3VCC

MUX 4

MUX 5FromI/O

Globalclear

Globalclock

Copyright ©2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458

All rights reserved.

Digital Fundamentals, Tenth EditionThomas L. Floyd

Figure 11.24 Commonly used symbol for a multiplexer. It can have any number of inputs.




Figure 11.25 A macrocell in the Altera MAX 7000 family of CPLDs.




Figure 11.26 A macrocell configured for generation of an SOP logic function. Red indicates data path.




Figure 11.27 A macrocell configured for generation of a registered logic function. Red indicates data path.


Programmable Logic Software

All manufacturers of programmable logic provide software to support their products. The process is illustrated in the flowchart.

Design entry

Synthesis

Deviceprogramming(downloading)

TimingsimulationFunctional

simulation

Implementation

SchematicHDL

The first step is to enter the logic design into a computer. It is done in one of two ways:

1) Schematic entry2) Hardware description

language (HDL).


Programmable Logic Software

In schematic entry, the design is drawn on a computer screen by placing components and connecting then with simulated wires. After drawing the schematic, it can be reduced to a single block symbol:

Design entry

SchematicHDL


Functional Simulation

After entering the circuit, the circuit is tested in a functional simulation. You can test the circuit with waveforms to verify the operation.

The following shows the functional test of a counter using a waveform editor:

Functionalsimulation


Synthesis

After the simulation, the computer program optimizes the logic by eliminating redundant terms and generating a netlist, (a connection list) that is a complete description of the circuit.

Synthesis

Z

A1

A0

A2

A3

net1net2

net3net4

and1net5

net6

net7net9

and2 net10

net8

net11inv1

net14 and3net15

net13

net12

net16inv2

net17and4

net20

net19

net18

net21

inv3

net23

net25

net24

and5inv4 net22

I1

I2

I3

I4

or1net26

O1

Netlist (Logic3)net<name>: instance<name>, <from>; <to>;instances: and1, and2, and3, and4, and5, or1, inv2,inv3, inv4;Input/outputs: I1, I2, I3, I4, O1;net1: and1, inport1; I1;net2: and1, inport2; I2;net3: and1, inport3; I3;net4: and1, inport4; I4;net5: and1, outport1; or1, inport1;net6: and2, inport1; I1;net7: and2, inport2; I3;net8: and2, inport3; inv2,outport1net9: and2, inport4; inv4,outport1net10: and2, outport1; or1,inport2;net11: and3, inport1; inv2,outport1net12: and3, inport2; inv3,outport1net13: and3, inport3; I4;net14: and3, inport4; I1; 5: and3

Netlist


Implementation

The computer next “maps” the design from the netlist to fit it to a target device. Data for all potential target devices are in a software library. The computer must account for the I/O pins and fit the logic to the target device.

Implementation


Timing Simulation

After implementation, a timing simulation is done that takes into account the specific delays in the target device and verifies that there are no problems with the timing. As in the case of the functional simulation, the waveform editor can be used to review final timing.

Timingsimulation

Waveform Editor

Name:

A0

4 sm

A1

A2

A3

Z

1 sm 8 sm 12 sm 16 sm

0

0

0

0

X

Glitch

If a problem is revealed, it is not too late to correct it

before downloading the file.


Device Programming

The final step is to send the programming file from the computer to the target device and test the implementation.

Deviceprogramming(downloading)

Shown is a PLDT-2 prototyping board with an Altera PLD as the target device. Connections are added to the board from a pulse generator and oscilloscope to test the actual circuit in a laboratory environment. The prototyping board has built-in power supplies, interfacing, I/O, and more.

© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th ed

Selected Key Terms

PAL

GAL

Macrocell

CPLD

A type of one-time programmable SPLD that consists of a programmable array of AND gates that connects to a fixed array of OR gates.

A reprogrammable type of SPLD that that is similar to a PAL except it uses a reprogrammable process technology, such as EEPROM instead of fuses.

Part of a PAL, GAL, or CPLD that generally consists of one OR gate and some associated output logic.

A complex reprogrammable logic device that consists basically of multiple SPLD arrays with programmable interconnections.

eet 252 unit 4 programmable logic: splds & cplds read floyd, sections 11-1 to 11-4. study unit...

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