ee105 –fall 2015 microelectronic devices and circuitsee105/fa17/lectures/module_4-4... · ee105...
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EE105 – Fall 2015Microelectronic Devices and Circuits
Multi-Stage Amplifiers
Prof. Ming C. Wu
511 Sutardja Dai Hall (SDH)
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Terminal Gain and I/O Resistances of MOS Amplifiers
AV ,t = −gmRL
1+ gmRSRi =∞
Ro = ro 1+ gmRE( )#$ %&
AI ,t =∞
Without degeneration:Simply set RS = 0
AV ,t =RL1gm
+ RL
Ri =∞
Ro =1gm
AI ,t =∞
AV ,t = gmRL
Ri =1gm
Ro = ro 1+ gmRE( )!" #$
AI ,t ≈1
For the gain, Ri, Ro of the whole amplifier, you need to include voltage/current dividers at input and output stages
Common Source (CS) Common Drain (CD) Common Gate (CG)
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Summary of MOS Single-Transistor Amplifiers
MOS Common Source
Common Sourcewith Deg.
Common Drain
Common Gate
Ri ∞ ∞ ∞ SmallRo Large Very Large Small LargeAV Moderate Small ~ 1 ModeratefH Small Moderate Large Large
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Single Stage Amplifier Cannot Meet All Requirements
• For example, a general purpose operational amplifier requires– High input resistance ~ 1MΩ– Low output resistance ~ 100Ω– High voltage gain ~ 100,000
• No single transistor amplifier can satisfy all spec’s
• Cascading multiple stages of amplifiers offers a path towards the design
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Multistage Amplifiers
• Usually– An input stage to provide required input resistance– Middle stage(s) to provide gain– An output stage to provide required output resistance or drive external loads
• More gain !– Gain/stage limited, especially in nanoscale devices
• Improve Bandwidth– De-couple high impedance nodes from large capacitors
• DC coupling (no passive elements to block the signal)– Use amplifiers to naturally “level shift” signal
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Impedance “Match”
• On-chip circuits often use “voltage/current” matching to minimize loading
• Keep in mind the input resistance and output resistance of each type of stage so that the loading does not create an undesired effect
Ideal Rin Ideal RoutVoltage Amplifier ∞ 0Current Amplifier 0 ∞Transconductance Amplifier ∞ ∞Transresistance Amplifier 0 0
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Two-Stage Voltage Amplifier
• Boost gain by cascading Common-Source stages
CS1 CS2
Can combine into a single 2-port modelResults of new 2-port: Rin = Rin1, Rout = Rout2
CS1,2
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CS Cascade Analysis
vin voutgm1vin gm2vintvint
Results of new 2-port: Rin = Rin1 = Rout = Rout2 =AV = vout/vin =
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CS Cascade Bandwidth
vin voutgm1vin gm2vintvint
Two time constants:τ1 =τ2 =
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Bandwidth Extension
• Common Source stage has high gain, but low bandwidth
• Note that Miller effect is the culprit
• Follower stage can buffer source resistance from Miller cap
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Bandwidth Extension Using Source Follower (SF)
vin gm1vin vint voutgm2vint
COMMON SOURCE COMMON DRAIN COMMON SOURCE
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CS Example with Cap Load
• Cin and CS are very large, therefore they look like short circuits to the AC signal.
• If CL is very large, its pole dominates, let’s analyze
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CS with Cap Load – Small Signal
Rd
• What are the time constants associated with the capacitors in this circuit?
• What can we do if we have to drive a large CL?
R2//Rg1//Rg2~R2
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CS with Cap Load – Bandwidth
• How can we reduce the impact of CL?
• One way is to reduce the resistance Rd, but this reduces our low-frequency gain
• To recover the gain we can increase gm1. What does this cost us?
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CS with Cap Load – BW Extension
• A better way to extend the bandwidth is to add a source-follower stage.
• Similar to previous example
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CS with Cap Load – BW Extension
vin gm1vin vint
• By adding a CD (Source Follower) we can increase the bandwidth
• It costs us power for the CD stage
• Remember that increasing the BW by increasing gm1 costs us much more
vint
1/gm2
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CS + CG
• Common source provides gain, CG acts as a buffer, but is it even helping?
• How do you bias this circuit?
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Merged CS + CG = Cascode
• Let’s apply 2-port small-signal analysis
• In this case, we care about the input current to the second stage
• Note that the input resistance of the CG is low, therefore the majority of the CS current is fed to the CG
• Av =
vint
vout
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Cascode Bandwidth
• Draw in the Cgs and Cgd capacitors.
• Which ones are Miller effected?
• Is this better or worse than a CS without a CG?
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Cascode Bandwidth
• Draw in the capacitors and input resistance
vint
vout
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Cascode Biasing
l CG has a very large output resistancel Loading it with RD is likely to reduce the voltage gainl We can increase the gain by using a current source load, but rocneeds to be very large. Can use a cascode current mirror!
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Complete Amplifier Design
Goals: gm1 = 1 mS, Rout =5 MWWFor simplicity, let’s assume all gm and ro values are equal
AV ≈ −gm1Rout = −1mS *5MΩ = −5,000
Rout ≈12gmro
2 = 5MΩ
ro =20MΩgm
=10MΩ1mS
=100kΩ
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Bias Current & Device Sizing
ro =1
λIDS=100kΩ
IDS =1
.1V −1 *100kΩ=100µA
gm = 2k ' WL
⎛
⎝⎜
⎞
⎠⎟IDS =1mS
WL=
gm2
2k ' IDS=
(1mS)2
2*100µ *100µA= 50
Need to know process parameters to solve for W/Lk’ = 100 μA/V2λ = 0.1 [V-1]
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Output (Voltage) Swing
Maximum VOUT =Minimum VOUT =Input Bias VIN =
Need to know VGS – VT (e.g. VDSAT , VOV)
gm =2IDS
VGS −VT=1mS
VGS −VT =2IDSgm
=2*100µA1mS
= 0.2V