ee 218: introduction to nanotechnology and nanoelectronicshspwong/ee 218 - section 0 -...
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Stanford University
Center for Integrated Systems EE 218 Department of Electrical Engineering
EE 218: Introduction to Nanotechnology and Nanoelectronics
H.-S. Philip WongProfessor of Electrical Engineering Stanford University, Stanford, California, [email protected]
http://www.stanford.edu/~hspwong
Stanford University
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What is Nanotechnology?
Source: Apple Computer, Inc.
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The Beginning of Nano
Gerd Binnig, Heinrich Rohrer
Nobel Prize, 1986
Invention of the Scanning Tunneling Microscope (STM)
Source: IBM
Source: IBM
Stanford University
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Source: IBM
Stanford University
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Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005.
6DNA~2-1/2 nm diameter
Things Natural Things Manmade
MicroElectroMechanical Devices10 -100 µm wide
Red blood cellsPollen grain
Fly ash~ 10-20 µm
Atoms of siliconspacing ~tenths of nm
Head of a pin1-2 mm
Quantum corral of 48 iron atoms on copper surfacepositioned one at a time with an STM tip
Corral diameter 14 nm
Human hair~ 10-50 µm wide
Red blood cellswith white cell
~ 2-5 µm
Ant~ 5 mm
The Scale of Things -- Nanometers and More
The
Mic
row
orld
0.1 nm
1 nanometer (nm)
0.01 µm10 nm
0.1 µm100 nm
1 micrometer (µm)
0.01 mm10 µm
0.1 mm100 µm
1 millimeter (mm)
1 cm10 mm
10-2 m
10-3 m
10-4 m
10-5 m
10-6 m
10-7 m
10-8 m
10-9 m
10-10 m
Visib
lesp
ectru
m
The
Nan
owor
ld
1,000 nanometers =
1,000,000 nanometers =
Dust mite200 µm
ATP synthase
~10 nm diameterNanotube electrode
Carbon nanotube~2 nm diameter
Nanotube transistor
O O
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OO
O OO O OO OO
O
S
O
S
O
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O
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O
S
O
S
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21st Century Challenge
Combine nanoscale building blocks to make functional devices, e.g., a photosynthetic reaction center with integral semiconductor storage
Source: NSF website
Nanotechnology Progress G
enerating New
Excitement
Source: J. Sphorer (IBM)
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US Nanotechnology Funding
Source: M. Roco, NNI (10/29/2003).
Stanford University
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NNI Funding by Agency
Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005.
Stanford University
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Global Nanotechnology Investment
Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005.
Stanford University
Department of Electrical Engineering10 H.-S. Philip Wong EE 218
Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005.
Stanford University
Department of Electrical Engineering11 H.-S. Philip Wong EE 218
Source: M. Roco, NNI (10/29/2003).
Stanford University
Department of Electrical Engineering12 H.-S. Philip Wong EE 218
Source: M. Roco (NNI), National Research Council, Washington, D.C., March 23, 2005
Stanford University
Department of Electrical Engineering13 H.-S. Philip Wong EE 218Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005.
Stanford University
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http://www.research.ibm.com/pics/nanotech/
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Questions?
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An 8 nm Transistor Gate
Source Drain
Gate
Lgate=8 nmSource: IBM
Stanford University
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When one atom high “bumps” look significant in a photo of your transistors, both their manufacture and behavior are “exciting”
Atoms are starting to look big
Source: IBM
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Integrated Circuit Complexity
Source: G. Moore, Intel (2003)
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Source: K. David (Intel)
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Source: K. David (Intel)
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State-of-the-Art Technology
Source: M. Bohr, Intel (2004)
90 nm technology
65 nm technology
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A view from Intel
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Time Horizon
2004 2007 2010 2013 2016 2020
37 nm 25 nm 18 nm 13 nm 9 nm 6 nm Physical Gate
back-gate
channel
isolation
buried oxide
channel
top-gate
Double-Gate CMOS
Source Drain
Gate
depletion layer
isolation
buried oxidehalo
raised source/drain
Silicon Substrate
doped channel
High k gate dielectric
Strained Si, Ge, SiGe
FinFET
Strained Si, Ge, SiGe
isolation
buried oxide
Silicon Substrate
Ultrathin SOI
Evolutionary Revolutionary
Blue Sky
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Future Si DevicesGate
Drain
Poly-silicon
Tox=16A
Tsi=7 nm
Source
Source
Gate
Drain
NiSi Gate
Si Fin
BOX
Tox = 1.6nm
NiSi
Si
Tsi = 25nm
J. Kedzierski et al., IEDM2001 , IEDM 2002
B. Doris et al., IEDM 2002
60nm
Buried oxide
Strained silicon
SiGe
CoSi2 on RSD
Si
W
HfO2
SiO2
K. Rim et al., IEDM 2003
M. Yang et al., IEDM 2003 B. Lee et al., IEDM 2002
H. Shang et al., IEDM 2002
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Innovation Overtakes Scaling in Driving Performance
IBM Transistor Perform ance Improv em ent
0
20
40
60
80
100
CM
OS
5X
CM
OS
6X
CM
OS
7S-S
OI
CM
OS
8S2
CM
OS
9S
CM
OS
10S
CM
OS
11S
Rel
ativ
e %
Impr
ovem
ent
Gain by Traditional Scaling Gain by Innovation
65 nm
90 nm
130 nm
180 nm
350 nm
250 nm
500 nm
Innovation (invention) will increasingly dominate performance gains– Scheduled "invention" is now the majority component in all plans
• Risk has increased significantly
Source: IBM
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Straight Line Projections Can Be Wrong…
Therefore, we need to focus on the fundamentals
Source:
G. Moore, Intel (2003)
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To Learn More About Si Technology…
EE 212 – Fabrication technology (J. Plummer)
EE 316 – Si CMOS device (H.-S. P. Wong)
EE 311 – Device technology (K. Saraswat)
EE 309 – Semiconductor memory (H.-S. P. Wong)
EE 410 – Fabrication lab (K. Saraswat)
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Questions?
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Several distinct technologies have been used to implement complex logic
Data from R. Kurzweil, 1999, The Age of Spiritual Machines
We are here !$1000 buys...
1.E-03
1.E+00
1.E+03
1.E+06
1.E+09
1.E+12
1940 1950 1960 1970 1980 1990 2000 2010 2020
Year
Add
ition
s pe
r sec
ond
Vacuum tube
Discrete transistor
Integrated circuit
ENIAC
DEC PDP-8
IBM PC
Pentium 4 PC
Source: IBM
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Gestation for Technologies
012345
1870 1880 1890 1900 1910 1920 1930
Background/Infrastructure: 1874 (Braun)
Prototype built 1900 (Braun)
Commercialization: 1907 (Entrant)
Market production (Established Technology)
T1~ 20years
~10years
T2 T3
‘Research Curve’
Example: Solid State RectifierSolid State DiodeT1 26 (1874-1900)T2 7 (1900-1907)T3 6 (1907-1913)Learning Period 13 years
Vacuum TubeT1 20 (1884-1904)T2 9 (1904-1913)T3 6 (1913-1919)Learning Period 15 years
TransistorT1 25 (1923-1948)T2 6 (1948-1954)T3 5 (1954-1959)Learning period 11years
Integrated CircuitT1 17 (1942-1959)T2 3 (1959-1961)T3 5(1961-1966)Learning Period 8 years
After Ralph Cavin, SRC
• To be ready for 2016 - start now narrowing down options
Dev
elop
me n
t Lev
el
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International Technology Roadmap for Semiconductors
The International Technology Roadmap for Semiconductors (ITRS) is an assessment of the semiconductor technology requirements. The objective of the ITRS is to ensure advancements in the performance of integrated circuits. This assessment, called roadmapping, is a cooperative effort of the global industry manufacturers and suppliers, government organizations, consortia, and universities.The ITRS identifies the technological challenges and needs facing the semiconductor industry over the next 15 years. It is sponsored by the European Semiconductor Industry Association (ESIA), the Japan Electronics and Information Technology Industries Association (JEITA), the Korean Semiconductor Industry Association (KSIA), the Semiconductor Industry Association (SIA), and Taiwan Semiconductor Industry Association (TSIA). International SEMATECH is the global communication center for this activity. The ITRS team at International SEMATECH also coordinates the USA region events.
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Emerging Research Logic Devices 2003 ITRS PIDS/ERD Chapter
Device
FET RSFQ 1D structures
Resonant Tunneling Devices
SET Molecular QCA Spin transistor
Cell Size 100 nm 0.3 µm 100 nm 100 nm 40 nm Not known 60 nm 100 nm
Density (cm-2) 3E9 1E6 3E9 3E9 6E10 1E12 3E10 3E9
Switch Speed
700 GHz 1.2 THz Not
known 1 THz 1 GHz Not known 30 MHz 700 GHz
Circuit Speed 30 GHz 250–
800 GHz 30 GHz 30 GHz 1 GHz <1 MHz 1 MHz 30 GHz
Switching Energy, J 2×10–18 >1.4×10–17 2×10–18 >2×10–18 >1.5×10–17 1.3×10–16 >1×10–18 2×10–18
Binary Throughput, GBit/ns/cm2
86 0.4 86 86 10 N/A 0.06 86
Source: ITRS, J. Hutchby
http://public.itrs.net
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Emerging Research Memory Devices2003 ITRS PIDS/ERD Chapter
Present Day Baseline Technologies
Phase Change
Memory*
Floating Body
DRAM
Nano-floating
Gate Memory**
Single/Few Electron
Memories**
Insulator Resistance
Change Memory**
Molecular Memories**
Storage Mechanism
Device Types DRAM NOR
Flash OUM 1TDRAM eDRAM
Engineered tunnel
barrier or nanocrystal
SET MIM oxides
Bi-stable switch
Molecular NEMS
Availability 2004 2004 ~2006 ~2006 ~2006 >2007 ~2010 >2010
Cell Elements 1T1C 1T 1T1R 1T 1T 1T 1T1R 1T1R
Source: ITRS, J. Hutchby
http://public.itrs.net
Stanford University
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Source: M. Roco (NNI), Nanotechnology Research Directions II, September 8, 2004.
Stanford University
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Questions?