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Stanford University Center for Integrated Systems EE 218 Department of Electrical Engineering EE 218: Introduction to Nanotechnology and Nanoelectronics H.-S. Philip Wong Professor of Electrical Engineering Stanford University, Stanford, California, U.S.A. [email protected] http://www.stanford.edu/~hspwong

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Page 1: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Center for Integrated Systems EE 218 Department of Electrical Engineering

EE 218: Introduction to Nanotechnology and Nanoelectronics

H.-S. Philip WongProfessor of Electrical Engineering Stanford University, Stanford, California, [email protected]

http://www.stanford.edu/~hspwong

Page 2: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering2 H.-S. Philip Wong EE 218

What is Nanotechnology?

Source: Apple Computer, Inc.

Page 3: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering3 H.-S. Philip Wong EE 218

The Beginning of Nano

Gerd Binnig, Heinrich Rohrer

Nobel Prize, 1986

Invention of the Scanning Tunneling Microscope (STM)

Source: IBM

Source: IBM

Page 4: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering4 H.-S. Philip Wong EE 218

Source: IBM

Page 5: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering5 H.-S. Philip Wong EE 218

Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005.

Page 6: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

6DNA~2-1/2 nm diameter

Things Natural Things Manmade

MicroElectroMechanical Devices10 -100 µm wide

Red blood cellsPollen grain

Fly ash~ 10-20 µm

Atoms of siliconspacing ~tenths of nm

Head of a pin1-2 mm

Quantum corral of 48 iron atoms on copper surfacepositioned one at a time with an STM tip

Corral diameter 14 nm

Human hair~ 10-50 µm wide

Red blood cellswith white cell

~ 2-5 µm

Ant~ 5 mm

The Scale of Things -- Nanometers and More

The

Mic

row

orld

0.1 nm

1 nanometer (nm)

0.01 µm10 nm

0.1 µm100 nm

1 micrometer (µm)

0.01 mm10 µm

0.1 mm100 µm

1 millimeter (mm)

1 cm10 mm

10-2 m

10-3 m

10-4 m

10-5 m

10-6 m

10-7 m

10-8 m

10-9 m

10-10 m

Visib

lesp

ectru

m

The

Nan

owor

ld

1,000 nanometers =

1,000,000 nanometers =

Dust mite200 µm

ATP synthase

~10 nm diameterNanotube electrode

Carbon nanotube~2 nm diameter

Nanotube transistor

O O

O

OO

O OO O OO OO

O

S

O

S

O

S

O

S

O

S

O

S

O

S

O

S

PO

O

21st Century Challenge

Combine nanoscale building blocks to make functional devices, e.g., a photosynthetic reaction center with integral semiconductor storage

Source: NSF website

Nanotechnology Progress G

enerating New

Excitement

Source: J. Sphorer (IBM)

Page 7: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering7 H.-S. Philip Wong EE 218

US Nanotechnology Funding

Source: M. Roco, NNI (10/29/2003).

Page 8: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering8 H.-S. Philip Wong EE 218

NNI Funding by Agency

Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005.

Page 9: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering9 H.-S. Philip Wong EE 218

Global Nanotechnology Investment

Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005.

Page 10: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering10 H.-S. Philip Wong EE 218

Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005.

Page 11: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering11 H.-S. Philip Wong EE 218

Source: M. Roco, NNI (10/29/2003).

Page 12: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering12 H.-S. Philip Wong EE 218

Source: M. Roco (NNI), National Research Council, Washington, D.C., March 23, 2005

Page 13: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering13 H.-S. Philip Wong EE 218Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005.

Page 14: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering14 H.-S. Philip Wong EE 218

http://www.research.ibm.com/pics/nanotech/

Page 15: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering15 H.-S. Philip Wong EE 218

Questions?

Page 16: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering16 H.-S. Philip Wong EE 218

An 8 nm Transistor Gate

Source Drain

Gate

Lgate=8 nmSource: IBM

Page 17: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering17 H.-S. Philip Wong EE 218

When one atom high “bumps” look significant in a photo of your transistors, both their manufacture and behavior are “exciting”

Atoms are starting to look big

Source: IBM

Page 18: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering18 H.-S. Philip Wong EE 218

Integrated Circuit Complexity

Source: G. Moore, Intel (2003)

Page 19: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering19 H.-S. Philip Wong EE 218

Source: K. David (Intel)

Page 20: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering20 H.-S. Philip Wong EE 218

Source: K. David (Intel)

Page 21: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering21 H.-S. Philip Wong EE 218

State-of-the-Art Technology

Source: M. Bohr, Intel (2004)

90 nm technology

65 nm technology

Page 22: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering22 H.-S. Philip Wong EE 218

A view from Intel

Page 23: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering23 H.-S. Philip Wong EE 218

Time Horizon

2004 2007 2010 2013 2016 2020

37 nm 25 nm 18 nm 13 nm 9 nm 6 nm Physical Gate

back-gate

channel

isolation

buried oxide

channel

top-gate

Double-Gate CMOS

Source Drain

Gate

depletion layer

isolation

buried oxidehalo

raised source/drain

Silicon Substrate

doped channel

High k gate dielectric

Strained Si, Ge, SiGe

FinFET

Strained Si, Ge, SiGe

isolation

buried oxide

Silicon Substrate

Ultrathin SOI

Evolutionary Revolutionary

Blue Sky

Page 24: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering24 H.-S. Philip Wong EE 218

Future Si DevicesGate

Drain

Poly-silicon

Tox=16A

Tsi=7 nm

Source

Source

Gate

Drain

NiSi Gate

Si Fin

BOX

Tox = 1.6nm

NiSi

Si

Tsi = 25nm

J. Kedzierski et al., IEDM2001 , IEDM 2002

B. Doris et al., IEDM 2002

60nm

Buried oxide

Strained silicon

SiGe

CoSi2 on RSD

Si

W

HfO2

SiO2

K. Rim et al., IEDM 2003

M. Yang et al., IEDM 2003 B. Lee et al., IEDM 2002

H. Shang et al., IEDM 2002

Page 25: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering25 H.-S. Philip Wong EE 218

Innovation Overtakes Scaling in Driving Performance

IBM Transistor Perform ance Improv em ent

0

20

40

60

80

100

CM

OS

5X

CM

OS

6X

CM

OS

7S-S

OI

CM

OS

8S2

CM

OS

9S

CM

OS

10S

CM

OS

11S

Rel

ativ

e %

Impr

ovem

ent

Gain by Traditional Scaling Gain by Innovation

65 nm

90 nm

130 nm

180 nm

350 nm

250 nm

500 nm

Innovation (invention) will increasingly dominate performance gains– Scheduled "invention" is now the majority component in all plans

• Risk has increased significantly

Source: IBM

Page 26: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering26 H.-S. Philip Wong EE 218

Straight Line Projections Can Be Wrong…

Therefore, we need to focus on the fundamentals

Source:

G. Moore, Intel (2003)

Page 27: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering27 H.-S. Philip Wong EE 218

To Learn More About Si Technology…

EE 212 – Fabrication technology (J. Plummer)

EE 316 – Si CMOS device (H.-S. P. Wong)

EE 311 – Device technology (K. Saraswat)

EE 309 – Semiconductor memory (H.-S. P. Wong)

EE 410 – Fabrication lab (K. Saraswat)

Page 28: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering28 H.-S. Philip Wong EE 218

Questions?

Page 29: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering29 H.-S. Philip Wong EE 218

Several distinct technologies have been used to implement complex logic

Data from R. Kurzweil, 1999, The Age of Spiritual Machines

We are here !$1000 buys...

1.E-03

1.E+00

1.E+03

1.E+06

1.E+09

1.E+12

1940 1950 1960 1970 1980 1990 2000 2010 2020

Year

Add

ition

s pe

r sec

ond

Vacuum tube

Discrete transistor

Integrated circuit

ENIAC

DEC PDP-8

IBM PC

Pentium 4 PC

Source: IBM

Page 30: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering30 H.-S. Philip Wong EE 218

Gestation for Technologies

012345

1870 1880 1890 1900 1910 1920 1930

Background/Infrastructure: 1874 (Braun)

Prototype built 1900 (Braun)

Commercialization: 1907 (Entrant)

Market production (Established Technology)

T1~ 20years

~10years

T2 T3

‘Research Curve’

Example: Solid State RectifierSolid State DiodeT1 26 (1874-1900)T2 7 (1900-1907)T3 6 (1907-1913)Learning Period 13 years

Vacuum TubeT1 20 (1884-1904)T2 9 (1904-1913)T3 6 (1913-1919)Learning Period 15 years

TransistorT1 25 (1923-1948)T2 6 (1948-1954)T3 5 (1954-1959)Learning period 11years

Integrated CircuitT1 17 (1942-1959)T2 3 (1959-1961)T3 5(1961-1966)Learning Period 8 years

After Ralph Cavin, SRC

• To be ready for 2016 - start now narrowing down options

Dev

elop

me n

t Lev

el

Page 31: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering31 H.-S. Philip Wong EE 218

International Technology Roadmap for Semiconductors

The International Technology Roadmap for Semiconductors (ITRS) is an assessment of the semiconductor technology requirements. The objective of the ITRS is to ensure advancements in the performance of integrated circuits. This assessment, called roadmapping, is a cooperative effort of the global industry manufacturers and suppliers, government organizations, consortia, and universities.The ITRS identifies the technological challenges and needs facing the semiconductor industry over the next 15 years. It is sponsored by the European Semiconductor Industry Association (ESIA), the Japan Electronics and Information Technology Industries Association (JEITA), the Korean Semiconductor Industry Association (KSIA), the Semiconductor Industry Association (SIA), and Taiwan Semiconductor Industry Association (TSIA). International SEMATECH is the global communication center for this activity. The ITRS team at International SEMATECH also coordinates the USA region events.

Page 32: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering32 H.-S. Philip Wong EE 218

Emerging Research Logic Devices 2003 ITRS PIDS/ERD Chapter

Device

FET RSFQ 1D structures

Resonant Tunneling Devices

SET Molecular QCA Spin transistor

Cell Size 100 nm 0.3 µm 100 nm 100 nm 40 nm Not known 60 nm 100 nm

Density (cm-2) 3E9 1E6 3E9 3E9 6E10 1E12 3E10 3E9

Switch Speed

700 GHz 1.2 THz Not

known 1 THz 1 GHz Not known 30 MHz 700 GHz

Circuit Speed 30 GHz 250–

800 GHz 30 GHz 30 GHz 1 GHz <1 MHz 1 MHz 30 GHz

Switching Energy, J 2×10–18 >1.4×10–17 2×10–18 >2×10–18 >1.5×10–17 1.3×10–16 >1×10–18 2×10–18

Binary Throughput, GBit/ns/cm2

86 0.4 86 86 10 N/A 0.06 86

Source: ITRS, J. Hutchby

http://public.itrs.net

Page 33: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering33 H.-S. Philip Wong EE 218

Emerging Research Memory Devices2003 ITRS PIDS/ERD Chapter

Present Day Baseline Technologies

Phase Change

Memory*

Floating Body

DRAM

Nano-floating

Gate Memory**

Single/Few Electron

Memories**

Insulator Resistance

Change Memory**

Molecular Memories**

Storage Mechanism

Device Types DRAM NOR

Flash OUM 1TDRAM eDRAM

Engineered tunnel

barrier or nanocrystal

SET MIM oxides

Bi-stable switch

Molecular NEMS

Availability 2004 2004 ~2006 ~2006 ~2006 >2007 ~2010 >2010

Cell Elements 1T1C 1T 1T1R 1T 1T 1T 1T1R 1T1R

Source: ITRS, J. Hutchby

http://public.itrs.net

Page 34: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering34 H.-S. Philip Wong EE 218

Source: M. Roco (NNI), Nanotechnology Research Directions II, September 8, 2004.

Page 35: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering35 H.-S. Philip Wong EE 218

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Page 36: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering36 H.-S. Philip Wong EE 218

Nano Cosmetics

Page 37: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering37 H.-S. Philip Wong EE 218

Nano Skin Care Products

Page 38: EE 218: Introduction to Nanotechnology and Nanoelectronicshspwong/EE 218 - Section 0 - Introduction.pdf · International Technology Roadmap for Semiconductors The International Technology

Stanford University

Department of Electrical Engineering38 H.-S. Philip Wong EE 218

Questions?