ece c03 lecture 141 lecture 14 vhdl modeling of sequential machines hai zhou ece 303 advanced...

ECE C03 Lecture 14 1

Lecture 14 VHDL Modeling of Sequential Machines

Hai Zhou

ECE 303

Advanced Digital Design

Spring 2002


Outline

• Describing Sequential Behavior in VHDL• Latches• Flip-Flops• Finite State Machines• Synthesis Using VHDL• Using Packages in VHDL• READING: Dewey 17.1, 17.3, 17.4, 17.5, 17.6,

17.7, 17.8, 17.10, 18.1, 18.2


Latches• Latches are easily described by using the concurrent signal

assignment statemententity JK_LATCH isport ( J, K : in BIT;

Q : inout BIT := ‘0’;Q_BAR : inout BIT := ‘1’;)

end JK_LATCH;architecture TRUTH_TABLE of JK_LATCH isbegin

-- Map truth table into conditional concurrent statements Q <= Q when (J = ‘0’ and K = ‘0’) else ‘0’ when (J = ‘0’ and ‘K=‘1’) else

‘1’ when (J=‘1’ and K = ‘0’) elseQ_BAR;

Q_BAR <= not Q;end TRUTH_TABLE;

J K Q+

0 0 Q

0 1 0

1 0 1

1 1 Q/


Level-sensitive Synchronous Behavior• When a control signal like a clock controls whether the gated

latch responds to inputsentity JK_GATED_LATCH isport ( J, K, CLK : in BIT;

Q : inout BIT := ‘0’;Q_BAR : inout BIT := ‘1’;) end JK_LATCH;

architecture TRUTH_TABLE of JK_GATED_LATCH isbeginCLKED : block (CLK = ‘1’) -- guard expressionbegin Q <= guarded Q when (J = ‘0’ and K = ‘0’) else ‘0’ when (J = ‘0’ and ‘K=‘1’) else


Q_BAR <= not Q;end block CLKED; end TRUTH_TABLE;


Block Statements• A block statement provides a way to combine a group of

concurrent statements together• A group of statements can be placed under a guard• FORMAT

label: block (guard expression)-- declarative partbegin-- statement partend block label

• A guard is a boolean expression that evaluates to true or false.

• Concurrent statements in block execute if guard is true


Guarded Statement

• A guarded assignment statement executes if either– (1) the guard expression changes from FALSE to TRUE

– (2) The guard expression is TRUE and one of the signals appearing on the right hand side of the signal assignment changes value

• Example:B1 : block (CONTROL_SIGNAL = ‘1’)

begin

X <= guarded A or B after 5 min;

Y <= A or B after 5 min;

end blcok B1

5 10 15 20 25 30 35


Flip-flops• Edge-triggered flip-flops are controlled by signal transitions,

latches are controlled by levels. entity JK_FF isport ( J, K, CLK : in BIT;

Q : inout BIT := ‘0’;Q_BAR : inout BIT := ‘1’;) end JK_LATCH;

architecture DATA_FLOW of JK_FF isbeginCLKED : block (CLK = ‘1’ and not CLK’STABLE) -- guard expressionbegin Q <= guarded Q when (J = ‘0’ and K = ‘0’) else ‘0’ when (J = ‘0’ and ‘K=‘1’) else


Q_BAR <= not Q;end block CLKED; end DATA_FLOW;


Predefined Signal Attributes

• VHDL provides several predefined attributes which provide information about the signals

signal_name’ACTIVE: indicates if a transaction has occurred

signal_name’QUITE: indicates that transaction has not occurred

signal_name’EVENT : If an event has occurred on signal_name

signal_name’STABLE: If an event has not occurred

signal_name’LAST_EVENT: Time elapsed since last event has occurred

signal_name’DELAYED(T): A signal identical to signal_name but delayed by T units of type TIME;


Setup and Hold Times• Setup and hold times are timing restrictions placed on synchronous

sequential systems• Use assertions in VHDL to describe requirements

architecture DATA_FLOW of D_FF isbeginassert not

(CLK’DELAYED(HOLD) = ‘1’ andnot CLK’DELAYED(HOLD)’STABLE andnot D’STABLE(SETUP+HOLD)

report “Setup/Hold Timing Violation”;CLKED: block (CLK = ‘1’ and not CLK’STABLE)Q <= guarded D;Q_BAR <= not Q;Q_BAR <= not Q;end DATA_FLOW;

HoldSetup

D

CLK

CLK’DELAYED(HOLD)


Synchronous Finite State Machines• Consider example of binary counter

Z0

Z1

Z2

A

B

C


Data flow VHDL Modeling of Counterentity BIN_COUNTER isport (CLK : in BIT; Z : out BIT_VECTOR(2 downto 0));end BIN_COUNTER;architecture DATA_FLOW of BIN_COUNTER is

type FF_INDEX is (A, B, C);type FF_TYPE is array (FF_INDEX) of BIT;signal Q : FF_TYPE;

beginDFF: block (CLK = ‘1’ and not CLK’STABLE) -- rising edgebegin -- State D flip flops Q(A) <= guarded (Q(A) and not Q(B) ) or (Q(A) and not Q(C)) or (not Q(A) and Q(B) and Q(C); Q(B) <= guarded Q(B) xor Q(C); Q(C) <= guarded not Q(C);end block DFF;-- output function

Z <= Q(A) & Q(B) & Q(C);end DATA_FLOW;


Algorithmic Modeling of State Machines

• Until now, we showed state machines being modeled by data flow (using concurrent statements)

• We will describe using algorithmic or procedural form using conventional programming language semantics– process statements

– wait statements

– variable and signal assignments

– if and case statements

– loop statements


Binary Counter State Diagram

S0000

S5101

S3011

S1001S7

111

S6110

S2010

S4100


VHDL Model of Counterarchitecture ALGORITHM of BIN_COUNTER isbegin process variable PRESENT_STATE: BIT_VECTOR(2 downto 0) := B”111”; begin

case PRESENT_STATE iswhen B”000” => PRESENT_STATE := B”001”;when B”001” => PRESENT_STATE := B”010”;when B”010” => PRESENT_STATE := B”011”;when B”011” => PRESENT_STATE := B”100”;when B”100” => PRESENT_STATE := B”101”;when B”101” => PRESENT_STATE := B”110”;when B”110” => PRESENT_STATE := B”111”;when B”111” => PRESENT_STATE := B”000”;

end case;Z <= PRESENT_STATE after 10 nsec; wait until (CLK = ‘1’;end process;

end ALGORITHM;


VHDL Model of FSMs for Synthesis

• One can define a VHDL model of a FSM (Mealy Machine) using two processes– One for the combinational logic for the next state and

output functions

– One for the sequential elements

Memory elements, FFs

Next state Logic function

Output logic function

Primaryinputs

Presntstate


Architecture Body of FSM

architecture rtl of entname issubtype state_type is std_ulogic_vector(3 downto 0); constant s0 : state_type := "0001"; constant s1 : state_type := "0010"; constant s2 : state_type := "0100"; constant s3 : state_type := "1000";signal state, next_state : state_type; signal con1, con2, con3 : std_ulogic; signal out1, out2 : std_ulogic; signal clk, reset : std_ulogic;-- process comb logic-- process state registersend architecture rtl;

s0

s1

s2

s3


Process Statements for Comb/State Reg Logic

begin state_logic : process (state, con1, con2, con3) isbegin case state is when s0 => out1 <= '0'; out2 <= '0'; next_state <= s1; when s1 => out1 <= '1'; if con1 = '1' then next_state <= s2; else next_state <= s1;

end if; when s2 => out2 <= '1'; next_state <= s3;

when s3 => if con2 = '0' then

next_state <= s3; elsif con3 = '0' then

out1 <= '0'; next_state <= s2;else next_state <= s1;

end if; when others => null;end case; end process state_logic;

state_register : process (clk, reset) is begin if reset = '0' then state <= s0; elsif rising_edge(clk) then state <= next_state; end if; end process state_register;


Use of VHDL in Synthesis

• VHDL was initially developed as a language for SIMULATION

• Recently being used as a language for hardware synthesis from logic synthesis companies– Synopsys Design Compiler, Ambit BuildGates, Mentor

Graphics Autologic, ..

• Synthesis tools take a VHDL design at behavioral or structural level and generate a logic netlist – Minimize number of gates, delay, power, etc.

Area

delay


Synthesizable Subset of VHDL

• There are a number of constructs that cannot be synthesized into hardware– File operations including textio

– Assertion statements

• There are some generally accepted ways of entering VHDL descriptions such that it correctly synthesizes the logic


Use of Packages in VHDL

• A VHDL package is simply a way of grouping a collection of related declarations that serve a common purpose

• Can be reused by other designspackage identifier is

{package declaration}

end package identifier;


Predefined Packages• The predefined types in VHDL are stored in a library “std’• Each design unit is automatically preceded by the

following context clauselibrary std, work; use std.standard.all;

package standard istype boolean is (false, true); -- defined for operators =, <=, >=, ..type bit is (‘0’, ‘1’); -- defined for logic operations and, or, not…type character is (..);type integer is range IMPLEMENTATION_DEFINED;subtype natural is integer range 0 to integer’high;type bit_vector is array(natural range <>) of bit;…end package standard;


Summary

• Describing Sequential Behavior in VHDL• Latches• Flip-Flops• Finite State Machines• Synthesis Using VHDL• Using Packages in VHDL• NEXT LECTURE: Course review

ece c03 lecture 141 lecture 14 vhdl modeling of sequential machines hai zhou ece 303 advanced...

Documents

block clk

block guard expression

flow of jk

end jk

table of jk

block control

control signal

inputsentity jk