ECE 265 – LECTURE 5

The M68HC11 Basic Instruction Set

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Joanne E. DeGroat, OSU

Lecture Overview

The M68HC11 Basic Instruction Set How to partition the instruction set to learn it What are those partitions The 68HC11 data movement instructions

Material from Chapter 2 and 3 plus a 68HC11 reference manual. Instruction set details are in Appendix A of the text.

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Basic guide to any architecture

The instruction set of any processor can be partitioned into logical groupings.

Instructions for Data Movement – no operation or manipulation – just transfer

the data from one location to another Arithmetic – an take note of any unique aspects – most

architecture treat data such that it is treated as 2’s complement. Multiply and Divide – if these are supported by instructions. Logical Instructions – Boolean operations Testing and Bit Manipulation – even in the CCR Shift and Rotate

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Joanne E. DeGroat, OSU

Basic guide (cont.)

Instruction classes continued Condition Code Register Branch – what conditional branches are supported Jump – direct? How different from Branch? Subroutine Calls and Return – calls that save register

and data and calls that don’t. Stack Pointer Index Register and Indexed access to data Interrupts and Interrupt Handling Any miscellaneous instructions

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Joanne E. DeGroat, OSU

Data Movement

These instructions allow for the transfer of data from one location to another.

In a RISC (Reduced Instruction Set Computer) these transfers are the only data movement instructions. Operational instructions are typically register to register with both operands being in register to start.

In a CISC (Complex Instruction Set Computer) there are complex instruction that not only perform the operation on data but also result in complex data movement and/or storage.

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Joanne E. DeGroat, OSU

Data Movement Instructions

These are listed in the table for the 68HC11.

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CLR

Operation: ACCX 0 or M 0 Description: The contents of the accumulator or the

memory location are set to 0s. CC effects: N, V, C are cleared, Z is set Forms: CLRA CLRB CLR

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Joanne E. DeGroat, OSU

Load data

Operation: place the operand data into accumulator A, B, or D.

Description: Load the accumulator CC effects: V cleared, N and Z set or cleared

depending on value of data. Forms: LDAA LDAB LDD

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Joanne E. DeGroat, OSU

Example of load

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Store data

Operation: Store the accumulator at the effective address.

Forms: STAA STAB STD

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Joanne E. DeGroat, OSU

The Stack

The stack is an area of RAM used for temporary storage, typically for subroutine calls and then the subsequent return. It is also used when servicing and interrupt.

One of the Programmers Model registers is the stack pointer register. This is a 16-bit register that points to the next free location on the stack. The stack grows down in memory.

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Joanne E. DeGroat, OSU

Stack and stack growth

Two important facts to note on stacks. Direction of growth What does the stack

pointer point to Data Free location

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Joanne E. DeGroat, OSU

Push and Pop

Two common operations on stacks are to add data, a Push, and the retrieval of data, a Pop.

For the 68HC11 A PUSH – Simply store the data at the address pointed

to by the stack pointer. After storing the data, decrement the stack pointer.

A POP – Increment the stack pointer. Use the data that the stack pointer now points to. Location is now considered free.

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Joanne E. DeGroat, OSU

Push and Pull

Operation: A/B Mem(SP) Pull Mem(SP) A/B Push Description: Transfers the contents of the

Accumulator to or from the top of the stack. CC effects: none Forms: this is an inherent instruction

PSHA PSHB PULA PULB

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Store the Accumulator

Operation: Mem(ea) A/B Description: Store the contents of the given

accumulator in the effective memory address CC effects: N V Z Forms: STAA STAB STD

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Joanne E. DeGroat, OSU

Transfer register

Operation: Transfers allowed are from A to B or CCR from B to A from CCR to A Description: Transfers the contents of one register

to another. CC effects: A to B and B to A N V Z Forms: only inherent

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Joanne E. DeGroat, OSU

Exchange registers

Operation: D X concurrent with X D D Y concurrent with Y D Description: Exchange the contents of the D

accumulator with the X or Y index register CC effects: None Forms: Inherent form instruction

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Lecture summary

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Have covered How to partition the instruction set when learning an

architecture. The data transfer instructions

Joanne E. DeGroat, OSU

Assignment

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Read Chapter 3 through section 3.4

Problems 3.3 3.4 3.5 3.6