ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 1
ROBUSPIC Workshop
ESSDERC ’06 – Montreux, SwitzerlandFriday 22nd of September
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 2
ESSDERC ’06 – Montreux, SwitzerlandFriday 22nd of September
Vladimir Ceperic, Adrijan Baric - University of Zagreb, CroatiaRenaud Gillon - AMI Semiconductors, Belgium
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 3
ContentsContentsContents
1 Introduction2 PCB modelling3 SMD components4 Chip packaging5 On-chip circuit6 Results7 Conclusion
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 4
IntroductionIntroductionIntroduction
We would like to achieve:
• Deal with EMC issues in a simple way • Use conducted EMC standards
• Achieve good agreement between simulations and measurements !!!
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 5
IntroductionIntroductionIntroduction
Conducted EMC standards:• IEC 61967-4:
“Integrated circuits – Measurements of electromagnetic emissions, 150 kHz to 1 GHz – Part 4: Measurements of conducted emissions – 1 Ohm/150 Ohm direct coupling method”
• IEC 62132-4: ”Integrated circuits - Measurement of radiated immunity – Part 4: Direct RF power injection method”
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 6
IntroductionIntroductionIntroduction
• IEC 61967-4: conducted electromagnetic emissions(to check EMISSIONS)
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 7
IntroductionIntroductionIntroduction
• IEC 62132-4: direct RF power injection method (to check IMMUNITY)
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 8
IntroductionIntroductionIntroduction
To achieve good agreement between simulations and measurements we deal with the following models:
• PCB tracks (including connectors)• SMD components on a PCB• Chip packaging (lead-frame, bond-wires, ...)• Chip, i.e. circuit itself (including parasitics)
e.g.
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 9
IntroductionIntroductionIntroduction
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 10
ContentsContentsContents
1 Introduction2 PCB modelling3 SMD components4 Chip packaging5 On-chip circuit6 Results7 Conclusion
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 11
PCB modellingPCB modellingPCB modelling
Various approaches:1. Simulate by using 3D EM field solvers (or 2D and a
half EM field solvers) hmmmm?!?!?!2. Build PCB, measure and model hmmmm?!?!?!
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 12
PCB modellingPCB modellingPCB modelling
• Ansoft Q3D Extractor: it generates a Spectre compatible netlist
next slide
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 13
PCB modellingPCB modellingPCB modelling
EM field solver
Not a bad solution: • It just:
– takes substantial time– does not necessarily get to the solution– does not necessarily produce accurate result
• Problems:– vias are generally a huge problem because of the number of
nodes that they generate during discretization of the simulated space (PCB trace is a relatively small issue)
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 14
PCB modellingPCB modellingPCB modelling
Build measure model
• This approach seems to be simpler• It may also include the influence of SMD components
(something that is simply hard to estimate exclusively from simulations!!!) we’ll deal with this issue later
(in Section 3)• PCB can be built, measured and modelled
concurrently while designing a chip/circuit (it is not necessary to wait for the chip to be processed!!!)
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 15
PCB modellingPCB modellingPCB modelling
Modelling of a short and medium line on a PCB
• Various lines have been produced and measured to model SMD components
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PCB modellingPCB modellingPCB modelling
• Short line (15 mm between SMA connectors)
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PCB modellingPCB modellingPCB modelling
• Medium line (30 mm between SMA connectors)
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 18
PCB modellingPCB modellingPCB modelling
• Long line (147 mm between SMA connectors)
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PCB modellingPCB modellingPCB modelling
• The model parameters are obtained by simultaneous optimization of model parameters for all three lines (short, medium, long)
• Model parameters of the mtline (Spectre model):r = 0.073 Ohm/ml = 2.67 uH/mc = 13.38 pF/mg = 8.83e-14 S/mrskin = 3.75e-7 Ohm/(m*sqrt(f))gdloss = 2.17e-12 S/(m*Hz)
(rskin and gdloss model skin effect resistance and dielectric loss conductance as a function of frequency)
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 20
ContentsContentsContents
1 Introduction2 PCB modelling3 SMD components4 Chip packaging5 On-chip circuit6 Results7 Conclusion
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 21
SMD componentsSMD componentsSMD components
• SMD components are modelled based on the measurements of various structures/PCBs and by assuming (or not) various simplifications
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 22
SMD componentsSMD componentsSMD components
• Approach 1 includes: – Modelling of PCB traces by Ansoft Q3D (3D/2D quasi-static
EM field solver that produces a Spectre sub-circuit netlist)– Measurement of the PCB– Modelling through the optimization procedure in order to
extract the equivalent circuit elements of the SMD components on the PCB
(this is an obviously slightly confusing approach)
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 23
SMD componentsSMD componentsSMD components
• Approach 1: - PCB traces are modelled by an EM field solver
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 24
SMD componentsSMD componentsSMD components
• Approach 1:- various SMD components are modelled by using the following equivalent circuits
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 25
SMD componentsSMD componentsSMD components
• Approach 1 example:- the network consisting of two resistors used in conducted EMC tests is shown below
- Two measurements are performed: the first for P2 left OPEN, and the second for P2 shorted to the ground
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 26
SMD componentsSMD componentsSMD components
• Approach 1 example:- based on 2 measurements the parameters of the equivalent circuit models for R1 and R2 are extracted
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 27
SMD componentsSMD componentsSMD components
• Approach 1 example:- the equivalent circuit parameters for R1 and R2 are shown in Table 1
SMD resistor Ls Rp Cp
R1, 1 Ω 0.86 nH 0.94 Ohm 31 pF
R2, 48.7 Ω 1.01 nH 48.77 Ohm 0 pF
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 28
SMD componentsSMD componentsSMD components
• Approach 2:- firstly, PCB lines including SMA connectors are measured (shortline, medium line, long line) (no SMD components are present)- secondly, PCB lines that contain SMD components are measured- thirdly, the ‘de-embedding’ of the lines is indirectly performed by taking into account the influence of the lines when determining the values of the equivalent circuit parameters
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 29
SMD componentsSMD componentsSMD components
• Approach 2:- two types of circuit structures are used
- PCB2 network is used to model either a resistor or a capacitor
P1 P2
Z1
Z2P1 P2
Z2
PCB1 PCB2
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 30
SMD componentsSMD componentsSMD components
• Approach 2 – Example 1:- modelling of a 4.7 nF capacitor
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 31
SMD componentsSMD componentsSMD components
• Approach 2 – Example 2:- modelling of a 48.7 Ohm resistor
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 32
SMD componentsSMD componentsSMD components
• Approach 2 – Example 2 (continued):- modelling of a 48.7 Ohm resistor
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 33
SMD componentsSMD componentsSMD components
• Tolerance of SMD components is a separate issue:
- a family of 10 curves for the capacitor C = 4.7 nF (10% tolerance)
0.5 1 1.5 2 2.5 3x 109
-45
-40
-35
-30
-25
-20
-15
C=4.7 nF (534-5724)Maximum difference = 6.38 db
Frequency [Hz]
S11
[db]
0.5 1 1.5 2 2.5 3x 109
-6
-5
-4
-3
-2
-1
C=4.7 nF (534-5724)Maximum difference = 1.16 rad
Frequency [Hz]
S11
[rad
]
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 34
SMD componentsSMD componentsSMD components
• Tolerance (continued):- a family of 10 curves for the capacitor C = 4.7 nF (10% tolerance)
0.5 1 1.5 2 2.5 3x 109
-0.8
-0.6
-0.4
-0.2
0
C=4.7 nF (534-5724)Maximum difference = 0.14 db
Frequency [Hz]
S12
[db]
0.5 1 1.5 2 2.5 3x 109
-3
-2
-1
0
1
C=4.7 nF (534-5724)Maximum difference = 0.09 rad
Frequency [Hz]
S12
[rad
]
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 35
SMD componentsSMD componentsSMD components
• Tolerance (continued):- a family of 10 curves for the capacitor C = 4.7 nF (10% tolerance) produces the following variation of the model parameters:
• Max C=5.17e-09 F (+10% of nominal value of 4.7nF)• Min C=4.23e-09 F (-10% of nominal value of 4.7nF)• Max Rp=8.18e+11 Ohm, Min Rp=1.47e+11 Ohm
• Max Ls=5.08e-10 H, Min Ls=2.84e-10 H• Max Rs=0.517 Ohm, Min Rs=0
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 36
SMD componentsSMD componentsSMD components
• Tolerance of SMD resistors:- a family of 10 curves for the resistor R = 48.7 Ohm (1% tolerance)
0.5 1 1.5 2 2.5 3x 109
-10.5
-10
-9.5
-9
-8.5
-8
-7.5
R=48.7 Ohm (117-0657)Maximum difference = 0.70 db
Frequency [Hz]
S11
[db]
0.5 1 1.5 2 2.5 3x 109
-5
-4
-3
-2
-1
0
R=48.7 Ohm (117-0657)Maximum difference = 0.13 rad
Frequency [Hz]
S11
[rad
]
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 37
SMD componentsSMD componentsSMD components
• Tolerance of SMD resistors (continued):- a family of 10 curves for the resistor R = 48.7 Ohm (1% tolerance)
0.5 1 1.5 2 2.5 3x 109
-6
-5.5
-5
-4.5
-4
-3.5
-3
R=48.7 Ohm (117-0657)Maximum difference = 0.47 db
Frequency [Hz]
S12
[db]
0.5 1 1.5 2 2.5 3x 109
-3
-2.5
-2
-1.5
-1
-0.5
0
R=48.7 Ohm (117-0657)Maximum difference = 0.10 rad
Frequency [Hz]
S12
[rad
]
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 38
SMD componentsSMD componentsSMD components
• Tolerance of the family of 48.7 Ohm resistors- a family of 10 resistors of R = 48.7 Ohm (1% tolerance) produces the following variation of the model parameters:
• Max R1=48.7 Ohm (+0.03% of nominal value of 48.7 Ohm)• Min R1=46.9 Ohm (-3.6% of nominal value of 48.7 Ohm)• Max Cp=5.04e-14 F, Min Cp=0• Max Ls=1.88e-09 H, Min Ls=1.35e-09 H
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 39
ContentsContentsContents
1 Introduction2 PCB modelling3 SMD components4 Chip packaging5 On-chip circuit6 Results7 Conclusion
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 40
Chip packagingChip packagingChip packaging
• Ansoft Q3D Extractor is used to extract the parasitics from the 3D model of the package
• Three different packages are modelled:
– JLCC 84 pin
– CLCC 84 pin– PLCC 84 pin
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 41
Chip packagingChip packagingChip packaging
• The 3D model of the JLCC 84 package consists of:– Bondwires– Leadframe– Ceramic case– Pins– Silicon chip
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 42
ContentsContentsContents
1 Introduction2 PCB modelling3 SMD components4 Chip packaging5 On-chip circuit6 Results7 Conclusion
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 43
On-chip circuitOnOn--chip circuitchip circuit
• There is nothing special about this stage (almost nothing)
• Cadence Spectre is used as a circuit simulator• Normally, an RC extraction of the circuit is performed to check
the influence of parasitics
• HERE, as the conducted EM emissions are measured at the ground pin of the chip (i.e. packaged chip), a separate extraction of the on-chip power/ground (PWR/GND) lines is performed by using Ansoft Q3D Extractor
• Thus, when using the description ‘RC extracted circuit’, these words denote the RC extracted circuit without the PWR/GND lines
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 44
ContentsContentsContents
1 Introduction2 PCB modelling3 SMD components4 Chip packaging5 On-chip circuit6 Results7 Conclusion
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 45
Results – EMC modelsResults Results –– EMC modelsEMC models
EMC models and simulation strategy• The following levels of modelling are used
– Complete model– Without packaging model (all other models included)– Without RC extraction of the circuit layout (PWR/GND lines
are included as they are extracted separately)– Without SMD parasitics– Withouth extracted PWR/GND lines– Without extracted PCB tracks
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 46
Results – Simulation timeResults Results –– Simulation timeSimulation time
LIN interface is selected as a test circuit
LIN ver. non-opt.
LIN ver. opt.
M1M1High
Voltage partHighVoltage part
LowVoltagepart
LowVoltagepart
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 47
Results – Simulation timeResults Results –– Simulation timeSimulation time
• The simulations are performed on Pentium 4 – 3.2 GHZ PC
• Table presents the influence of various EMC models on the simulation time of the reflected and injected power according to the DPI method (IEC 62132-4)
next page
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 48
Results – Simulation timeResults Results –– Simulation timeSimulation time
NOTE:1. RC extracted layout consumes most of the simulation time2. Packaging and PCB tracks introduce approximately the same load3. PWR/GND extraction has relatively minor influence, while SMD
components on the PCB practically present no effort to simulate
EMC Model Simulation time (CPU time)
Simulation time w.r.t. full model simulation time
Complete model 1 min 9 s 100 %
Without packaging model 44 s 64.2 %
Without RC extraction of the layout 20 s 28.3 %
Without SMD parasitics model 1 min 9 s 100 %
Without extracted PWR/GND 57 s 82.6 %
Without PCB tracks model 48 s 69.9%
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 49
Results – Simulation timeResults Results –– Simulation timeSimulation time
• Table on the next page presents the influence of various EMC models on the simulation time of the conducte EM emissions according to IEC 61967-4)
• Here, the model of the input signal generator is added to correctly reproduce the input signal as it is measured
next page
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 50
Results – Simulation timeResults Results –– Simulation timeSimulation time
NOTE:1. RC extracted layout consumes most of the simulation time again2. Packaging and PCB tracks contribute similarly to the simulation load, as
well as the input signal generator model3. SMD parasitics have the smallest influence on the simulation time
EMC Model Simulation time (CPU time)
Simulation time w.r.t. full model simulation time
Complete model 13 min 31 s 100 %
Without packaging model 6 min 40 s 49.3 %
Without RC extraction of the layout 2m 53.3s 21.3 %
Without SMD parasitics model 11 min 23 s 84.2 %
Without extracted PWR/GND 7 min 55 s 58.6 %
Without PCB tracks model 5 min 35 s 41.3 %
Without model of the input signal generator 5 min 48 s 42.9 %
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Results - AccuracyResults Results -- AccuracyAccuracy
• Accuracy of simulations is also checked on the LIN circuit
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Results - AccuracyResults Results -- AccuracyAccuracy
• Transmitted and reflected power according to 62123-4 (complete model)
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Results - AccuracyResults Results -- AccuracyAccuracy
• Transmitted and reflected power according to 62123-4 (without RC extraction of the layout)
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Results - AccuracyResults Results -- AccuracyAccuracy
• Transmitted and reflected power according to 62123-4 (without PCB parasitics)
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 55
Results - AccuracyResults Results -- AccuracyAccuracy
• Transmitted and reflected power according to 62123-4 (without on-chip PWR/GND parasitics)
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 56
Results - AccuracyResults Results -- AccuracyAccuracy
• Transmitted and reflected power according to 62123-4 (without packaging parasitics)
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 57
Results - AccuracyResults Results -- AccuracyAccuracy
• Transmitted and reflected power according to 62123-4 – SUMMARY
• NOTE: SMD components, packing and PCB tracks are of great importance
Model MSE_transmitted MaxE_transmitted
MSE_reflected MaxE_reflected
Complete model 0.7878 1.5219 0.4120 1.3866
Without PCB tracks model 8.3136 4.9160 2.3204 2.9344
Without packaging model 1.1398 2.5309 3.8925 5.9822
Without extracted PWR/GND 0.6290 1.2289 0.3451 1.3144
Without SMD parasitics model 7.6348 3.8962 47.7584 13.2396
Without RC extraction of the layout 0.8156 1.5932 0.3400 1.2384
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 58
Results - AccuracyResults Results -- AccuracyAccuracy
• Transmitted and reflected power according to 62123-4 – SUMMARY for LIN2 (second version of the LIN interface)
• NOTE: SMD components, PCB tracks and PWR/GND parasitics are of great importance (as well as RC extracted circuit)
Model MseR_transmitted
MaxE_transmitted
MseR_refl MaxE_refl
Complete model 1.1842 1.9641 0.6955 1.8750
Without PCB tracks model 24.8539 9.8015 1.2883 1.8023
Without packaging model 1.7627 2.2555 1.7870 2.6733
Without extracted PWR/GND 3.1627 3.3152 14.3338 6.9177
Without SMD parasitics model 8.1255 4.6209 77.7651 16.6159
Without RC extraction of the layout
3.5901 3.0528 2.7673 4.4898
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 59
ContentsContentsContents
1 Introduction2 PCB modelling3 SMD components4 Chip packaging5 On-chip circuit6 Results7 Conclusion
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 60
Conclusion - 1Conclusion Conclusion -- 11
This presentation shows the importance of various models that can be used in conducted EMC tests:
SMD components:• It is shown that SMD components mounted on the PCB are of
paramount importance for the accuracy of simulations• It is also shown that modelling SMD components introduces a
minimum load on the simulation time• On the other hand, the extraction of SMD parasitics has to be
performed separately for various families of SMD components; variations of the model parameters have to be known
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 61
Conclusion - 2Conclusion Conclusion -- 22
PCB tracks:• Correct modelling of PCB tracks is equally important• PCB model does consume more time than SMD model, but it is
still not the major load during simulations• Similarly to modelling SMD components, it does not seem that
there is a simple and accurate approach to modelling PCBs exclusively by simulations
• It seems that it is difficult to build an accurate PCB model without previously manufacturing a PCB
• 3D EM field simulations, if possible at all for more complex PCBlayouts, do not seem to be simple and accurate enough
ESSDERC ’06, Montreux ROBUSPIC Workshop A. Baric – Slide 62
Conclusion - 3Conclusion Conclusion -- 33
Packaging:• Correct model of the package can be built and simulated relatively
easily• Defining the model for the 3D EM simulations is time consuming
Power/ground extraction:• This extraction is of great importance for the accuracy of simulations
RC circuit extraction:• Although RC extracted circuit consumes a lot of simulation time, this
step has to be performed