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VII. GATE LEVEL MINIMIZATIONVII. GATE LEVEL MINIMIZATIONAA.. IMPLEMENTASIIMPLEMENTASI NANDNAND dandan NORNOR
ImplementasiImplementasi ++ BooleanBoolean dengandengan gerbanggerbang NANDNANDdandan NORNOR merupakanmerupakan teknikteknik manipulasimanipulasimenyederhanakanmenyederhanakan rangkaianrangkaian yangyang merubahmerubahdaridari diagramdiagram ANDAND –– OROR menjadimenjadi diagramdiagram NANDNANDatauatau NORNOR sajasaja11.. ImplementasiImplementasi NANDNAND
X
X
X
Y
Y
X . Y
X’
( X . Y )’
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Simbol 2 Gambar gerbang NANDSimbol 2 Gambar gerbang NAND
Contoh 1.Implementasikan fungsi boolean dengan gerbang NAND untuk Ekspresi minterm ( Sum of Product ) sbb : F = AB + CD
X X
YY
X’ + Y’(XY)’ Atau
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Jawab : ….Jawab : ….
D
A
D
C
B F
A
D
C
B F
A
C
B F
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Contoh 2. Implementasi fungsi boolean dengan Contoh 2. Implementasi fungsi boolean dengan gerbang NAND untuk F(XYZ) = gerbang NAND untuk F(XYZ) = ∑ 1,2,3,4,5,7
JawabJawab ::
Fungsi Boolean F = XY’ + X’Y + Z
YZ YZ YZ YZX’ O 1 1 1X 1 1 1 0
X
YX’
Y’ F
Z
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Lanjutan …
Z
X
YX’
Y’F
Z
X
YX’
Y’F
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2. Implementasi NOR
X
X
X
Y
Y
X + Y
X’
( X’ + Y’ )’ = XY
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Simbol 2 Gambar gerbang NORSimbol 2 Gambar gerbang NOR
Atau
Contoh 1.Implementasi fungsi boolean dengan gerbang NOR untuk : F = (A+B)(C+D)E
X
X
Y
Y X’ + Y’ =
(X+Y+Z)’
(X+Y+Z)’
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Jawab : ….Jawab : ….
A
DC
BF
EA
DC
BF
E
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Lanjutan …Lanjutan …
A
DC
BF
E
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VIII. GATE LEVEL MINIMIZATION
A. EXCLUSIVE – OR FUNCTION ( XOR )Operasi Boolean1. XOR X ⊕ Y = XY’ + X’Y2. XNOR X’ ⊕ Y’ = XY + X’Y’
3. Identitas pada operasi XORX ⊕ 0 = X X ⊕ 1 = X’X ⊕ X = 0 X ⊕ X’ = 1 X ⊕ Y’ = X’ ⊕ Y = (X ⊕ Y)’X(Y)” + (XY)’ = (XY)’ + (X)”Y = (X ⊕Y)’
4. Hukum Commutative dan Associative pada operasi XORA ⊕ B = B ⊕ A (A ⊕ B) ⊕ C = A ⊕ (B ⊕ C) = A ⊕ B ⊕ C
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Implementasi XOR
a) Dengan gerbang AND – OR - NOT
b) Dengan gerbang NAND
X
Y
Y
X
X + Y = XY’ + X’Y
X + Y = ((X(XY)’)’ (Y(XY)’)’)’
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BuktiBukti ::XX ++ YY == XYXY’ ++ XX’YY
== XYXY’ ++ XX’YY ++ XXXX’ ++ YYYY’== (X(X ++ Y)Y) (X(X’ ++ YY’))== (X(X ++ Y)Y) (XY)(XY)’== X(XY)X(XY)’ ++ Y(XY)Y(XY)’== ((X(XY)((X(XY)’))’ (Y(XY)(Y(XY)’))’))’
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B. Odd Function dan Even Function
1. Odd FunctionTabel kebenaran
AA BB CC FF0000000011111111
0000111100001111
0011001100110011
0011110011000011
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Fungsi Boolean dengan peta K
Odd Function (3 variabel)F = A’ (B’C + BC’) + A (B’C’ + BC)
= A⊕B⊕CGb. Rangkaian logika
BB’’CC’’ BB’’CC BCBC BCBC’’AA’’ 11 11AA 11 11
A
B
C
F
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2. Event FunctionTabel kebenaran
AA BB CC FF0000000011111111
0000111100001111
0011001100110011
1100001100111100
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FungsiFungsi BooleanBoolean dengandengan petapeta KK
EventEvent FunctionFunction ((33 variabel)variabel)FF == A’A’ (B’C’(B’C’ ++ BC)BC) ++ AA (B’C(B’C ++ BC’)BC’)
== (A(A ⊕⊕ BB ⊕⊕ C)’C)’GbGb.. RangkaianRangkaian digital/logikadigital/logika
B’C’B’C’ B’CB’C BCBC BC’BC’A’A’ 11 11AA 11 11
A
B
C
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C. Parity Generation and Checking
Bit parity digunakan untuk mendeteksi error bitselama terjadi transmisi dan processing data.1. Parity Generator
Adalah bit parity yang dibangkitkan padatransmitter (pengirim).Contoh.Tabel even parity generator untuk 3 variabel
3 bit message3 bit message Bit parityBit parityAA BB CC PP0000000011111111
0000111100001111
0011001100110011
0011110011000011
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DenganDengan petapeta K,K, makamakaPP == AA ⊕⊕ BB ⊕⊕ CC
GbGb.. RangkaianRangkaian logikalogika eveneven parityparity genaratorgenarator
22.. ParityParity ChickerChickerAdalahAdalah bitbit parityparity yangyang digunakandigunakan untukuntukcheckcheck padapada rankaianrankaian receiverreceiver (penerima)(penerima)
A
B
C
P
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ContohContoh..TabelTabel eveneven parityparity checkerchecker untukuntuk 33 variabelvariabel
4 bit Receiver4 bit Receiver Parity checkerParity checkerAA BB CC DD CkCk00000000000000001111111111111111
00000000111111110000000011111111
00001111000011110000111100001111
00110011001100110011001100110011
00111100110000111100001100111100
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DenganDengan petapeta K,K, makamakaCnCn == AA ⊕⊕ BB ⊕⊕ CC ⊕⊕ PP
RangkaianRangkaian logikalogika eveneven parityparity checkerchecker
A
BCn
C
D
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BB.. HARDWARE DESCRIPTION LANGUAGEHDL adalah suatu perangkat lunak berbasistekstual dan berorientasi pada struktur dansifat perangkat keras sistem digital.Penulisan program ini menggunakanalgoritma pemrograman dengan denganstruktur urutan instruksi – instruksi yangdiberikan. Proses pada program aplikasiHDL ini ada 2 yaitu simulasi dan sintesis.1. Logic Simulation
Program ini mempresentasikan strukturdan sifat sistem logika digital,menampilkan nilai output, mampumendeteksi kesalahn dan dapatdigunakan sebagai verifikasi desain.
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2. Logic SynthesisProgram ini dapat memproses daftarkomponen dan interkoneksi dari modelsistem digital. Logic Synthesis ini hampirsama dengan komplikasi ( Compiling ) padabahasa pemrograman konvensional tingkattinggi, bedanya pada program ini mampumenghasilkan kode obyec.Contoh :Tulis program HDL untuk Gbr rangkaianlogika ini.
C
B
Ae
Y
Xg3
g2
g1
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Jawab :“ Description of circuit “Module circuit ( A,B,C,X,Y )
Input A,B,C ;Output X,Y;Wire e;and g1 ( e, A, B )not g2 ( Y, C )or g3 ( X, e, Y )end module