Download - FPGA Disadvantages
Layout Styles
• Full-custom• Gate-array• Standard-cell• Macro-cell• FPGA (Field Programmable Gate-Array)
Full-custom• Complete control over transistor and interconnect
dimensions (within design rule constraints)• Produces Optimized Design (density, power,
performance)• Circuit Designers create application-specific building
blocks– Technology Provider (foundry) provide SPICE/HSPICE transistor
models, parasitic extraction tools– Models are used to drive transistor sizing/layout constraints
• Layout technician creates graphics from design schematic
• Top level down/Bottom level up• Continual verification of design as it becomes more
defined
Design Rule Constraints
• Minimum Spacing– Between metal lines (varies per layer)– Line width– Transistor channel lengths– Active area
• Via stacks• (Check from work)
Full-custom Disadvantages
• Most time-consuming• Most error-prone• Highest NRE (non-recurring expense)
– Design time– Layout time– Mask costs
• Longest time to manufacture
Gate-array Layout
• Transistors pre-placed, fixed in size
• Personalized by metal routing
• Fastest to manufacture
• Lowest mask cost
• Lends itself to automated placement and wiring
Gate Array
VddG
nd
Horizontal Routing ChannelVertical R
outing Channel
Sea of Gates: Routing Channels removed,route at higher metal layers
Gate Array Example
VddG
nd
A A
B B
Vdd Vdd
Schematic
A
A
B
B
OutOut
Gate-array Disadvantages
• Non-optimized spacing
• Limited transistor sizing options– Density– Performance– Power
• Wiring blockages/inefficiencies
• Excess circuitry
Standard Cell Layout
• Design partitioned into cells of standard height• Power and Ground (Power grid) wiring preset• Technology provider supplies libraries of pre-designed
cell elements for usage (utilize varying numbers of cells)– Primitives (NAND, NOR, etc.)– Storage Elements (DFF)
• Libraries can be tailored to specific applications (e.g., low power vs. high performance)
• Requires full manufacturing sequence• Typically automated place and wiring
Standard Cell Layout
Routing Channel
Routing Channel Feed-through cell
Note uniformheight
Our Cell Library
• Need specifics on library students will be using
Standard Cell Disadvantages
• Cell height restrictions limits cell library contents
• Full set of masks
• Longer manufacturing times
Macro-cell Layout• Library elements provided by technology supplier (e.g.,
foundry)• Elements can be of varying heights and widths• Richer variety of library elements (IP friendly)
Macro-cell Disadvantages
• Similar to Standard-cell in length of manufacturing times, mask costs
• Placement and wiring more complex
• Pre-layout of power grid more difficult, may not be possible
FPGA
• Field Programmable Gate Array• Array of logic blocks (Configurable Logic Blocks CLB)• Switchable interconnect resources
– Wire segments of varying lengths– Programmable switches that connect logic resources to wire
segments
• Final user sets switches (CLB and interconnect)• Immediate Use (“zero” fab time)• Minimal expense• Great for hardware prototyping
FPGA: Virtex-II Architecture
• Virtex™-II architecture’s core voltage operates at 1.5V
• Virtex™-II architecture’s core voltage operates at 1.5V
I/O Blocks (IOBs)I/O Blocks (IOBs)
ConfigurableLogic Blocks (CLBs)
ConfigurableLogic Blocks (CLBs)
Clock Management (DCMs, BUFGMUXes)Clock Management (DCMs, BUFGMUXes)
Block SelectRAM™resourceBlock SelectRAM™resource
Dedicated multipliersDedicated multipliers
Programmable interconnectProgrammable interconnect
© 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only
Slices and CLBs
• Each Virtex™-II CLB contains four slices– Local routing provides
feedback between slices in the same CLB, and it provides routing to neighboring CLBs
– A switch matrix provides access to general routing resources
CIN
SwitchMatrix
BUFTBUF T
COUTCOUT
Slice S0
Slice S1
Local Routing
Slice S2
Slice S3
CIN
SHIFT
© 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only
Slice 0
LUTLUT CarryCarry
LUTLUT CarryCarry D QCE
PRE
CLR
DQCE
PRE
CLR
Simplified Slice Structure
• Each slice has four outputs– Two registered outputs,
two non-registered outputs– Two BUFTs associated
with each CLB, accessible by all 16 CLB outputs
• Carry logic runs vertically, up only– Two independent
carry chains per CLB
© 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only
FPGA Disadvantages
• Least efficient use of silicon/wiring resources• Limited size options• Limited performance• Not good for high volume applications• If used for prototyping, still may have significant changes
when migrate to higher performance design and package solution