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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 1
Chapter 6Chapter 6
Test CompressionTest Compression
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 2
What is this chapter about?What is this chapter about?
� Introduce the basic concepts of test data
compression
� Focus on stimulus compression and response
compaction techniques
� Present and discuss commercial tools on test
compression
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 3
Test CompressionTest Compression
� Introduction
� Test Stimulus Compression
� Test Response Compaction
� Industry Practices
� Concluding Remarks
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 4
IntroductionIntroduction
� Why do we need test compression?
� Test data volume
� Test time
� Test pins
� Why can we compress test data?
� Deterministic test vector has “don’t care” (X’s)
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 5
(Source: Blyler, Wireless System Design, 2001)
1 2 4 8 16 32 640
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 6
Test compression categoriesTest compression categories
� Test Stimulus Compression� Code-based schemes
� Linear-decompression-based schemes
� Broadcast-scan-based schemes
� Test Response Compaction� Space compaction
� Time compaction
� Mixed time and space compaction
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 7
Architecture for test compressionArchitecture for test compression
Core
De
co
mp
resso
r
Co
mp
acto
rStimulus Response
Compacted Response
Compressed Stimulus
Low-Cost
ATE
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 8
Test Test stimulusstimulus compressioncompression
� Code-based schemes
� Linear-decompression-based schemes
� Broadcast-scan-based schemes
![Page 9: Chapter 06 Compression slides 091806Chapter 06 Compression.pdfTest time Test pins Why can we compress test data? Deterministic test vector has “don’t care” (X’s) EE141 5](https://reader030.vdocuments.us/reader030/viewer/2022040909/5e824c59954e9c1ddf2e5733/html5/thumbnails/9.jpg)
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 9
Test stimulus compressionTest stimulus compression
� Code-based schemes
� Dictionary code (fixed-to-fixed)
� Huffman code (fixed-to-variable)
� Run-length code (variable-to-fixed)
� Golomb code (variable-to-variable)
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 10
CodeCode--based schemesbased schemes
� Dictionary code (fixed-to-fixed)
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 11
CodeCode--based schemesbased schemes
� Huffman code (fixed-to-variable)
![Page 12: Chapter 06 Compression slides 091806Chapter 06 Compression.pdfTest time Test pins Why can we compress test data? Deterministic test vector has “don’t care” (X’s) EE141 5](https://reader030.vdocuments.us/reader030/viewer/2022040909/5e824c59954e9c1ddf2e5733/html5/thumbnails/12.jpg)
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 12
CodeCode--based schemesbased schemes
� Huffman code (fixed-to-variable)
![Page 13: Chapter 06 Compression slides 091806Chapter 06 Compression.pdfTest time Test pins Why can we compress test data? Deterministic test vector has “don’t care” (X’s) EE141 5](https://reader030.vdocuments.us/reader030/viewer/2022040909/5e824c59954e9c1ddf2e5733/html5/thumbnails/13.jpg)
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 13
CodeCode--based schemesbased schemes
� Run-length code (variable-to-fixed)
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 14
CodeCode--based schemesbased schemes
� Golomb code (variable-to-variable)
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 15
CodeCode--based schemesbased schemes
� Golomb code (variable-to-variable)
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 16
Test stimulus compressionTest stimulus compression
� Linear-decompression-based schemes
� Combinational linear decompressors
� Fixed-length sequential linear decompressors
� Variable-length sequential linear decompressors
� Combined linear and nonlinear decompressors
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 17
LinearLinear--decompressiondecompression--based schemesbased schemes
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 18
LinearLinear--decompressiondecompression--based schemesbased schemes
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 19
LinearLinear--decompressiondecompression--based schemesbased schemes
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 20
LinearLinear--decompressiondecompression--based schemesbased schemes
� Combinational linear decompressors
XOR
NetworkXOR Network
MISR
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 21
s1 s2 s3
o1 o2 o3 o4 o5
XOR XOR nnetwork: a 3etwork: a 3--toto--5 5 eexamplexample
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 22
LinearLinear--decompressiondecompression--based schemesbased schemes
� Fixed-length sequential linear decompressors
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 23
LinearLinear--decompressiondecompression--based schemesbased schemes
� Variable-length sequential linear decompressors
� Can vary the number of free variables
� Better encoding efficiency
� More control logic and control information
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 24
LinearLinear--decompressiondecompression--based schemesbased schemes
� Combined linear and nonlinear decompressors
� Specified bits tend to be highly correlated
� Combine linear and nonlinear decompression together can achieve greater compression than either alone
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 25
Test stimulus compressionTest stimulus compression
� Broadcast-scan-based schemes
� Broadcast scan
� Illinois scan
� Multiple-input broadcast scan
� Reconfigurable broadcast scan
� Virtual scan
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 26
BroadcastBroadcast--scanscan--based schemesbased schemes
� Broadcast scan
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 27
Generate patterns for broadcast scan Generate patterns for broadcast scan
� Force ATPG tool to generate patterns for broadcast scan
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 28
Broadcast scan for a pipelined circuitBroadcast scan for a pipelined circuit
� Broadcast scan for a pipelined circuit
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 29
BroadcastBroadcast--scanscan--based schemesbased schemes
� Illinois scan architecture
(a) Broadcast mode
(b) Serial chain mode
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 30
BroadcastBroadcast--scanscan--based schemesbased schemes
� Reconfigurable broadcast scan
� Reduce the number of channels that are required
� Static reconfiguration
– The reconfiguration can only be done when a new pattern is to be applied
� Dynamic reconfiguration
– The configuration can be changed while scanning in a pattern
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 31
BroadcastBroadcast--scanscan--based schemesbased schemes
� First configuration is: 1->{2,3,6}, 2->{7}, 3->{5,8}, 4->{1,4}
� Other configuration is: 1->{1,6}, 2->{2,4}, 3->{3,5,7,8}
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 32
BroadcastBroadcast--scanscan--based schemesbased schemes
� Block diagram of MUX network
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 33
BroadcastBroadcast--scanscan--based schemesbased schemes
� Virtual scan
� Pure MUX and XOR networks are allowed
� No need to solve linear equations
� Dynamic compaction can be effectively utilized during the ATPG process
� Very little or no fault coverage loss
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 34
Test Test responseresponse compactioncompaction
� Space compaction
� Time compaction
� Mixed time and space compaction
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 35
Test Test responseresponse compactioncompaction
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 36
Taxonomy of various response compaction schemesTaxonomy of various response compaction schemes
√√√Scalable Selector [Wohl 2004]
√√√√Compactor for SA [Wohl 2001]
√√√i-Compact [Patel 2003]
√√√√Block Compactor [Wang 2003]
√√√√OPMISR [Barnhart 2002]
√√√√Convolutional Compactor [Rajski 2005]
√√√√q-Compactor [Han 2003]
√√√X-Compact [Mitra 2004]
√√√√Enhanced Parity Tree [Sinanoglu 2003]
√√√Parity Tree [Karpovsky 1987]
√√√Zero-aliasing Compactor
[Chakrabarty 1998] [Pouya 1998]
NonlinearityLinearityCFICFSTimeSpace
IIIIIICompaction Schemes
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 37
Test Test responseresponse compactioncompaction
� Space compaction
� Zero-aliasing linear compaction
� X-compact
� X-blocking
� X-masking
� X-impact
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 38
Space compactionSpace compaction
� Zero-aliasing linear compaction
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 39
An example of response graphAn example of response graph
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 40
Space compactionSpace compaction
� X-compact
� X-tolerant response compaction technique
� X-compact matrix
� Error masking
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 41
Space compactionSpace compaction
� X-compact
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 42
Space compactionSpace compaction
� X-compactor with 8 inputs and 5 outputs
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 43
XX--compact Matrixcompact Matrix
S=
SC1
SC2
SC3
SC4
SC5
SC6
SC7
SC8
O=
O1
O2
O3
O4
O5
M X S = OT
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 44
Space compactionSpace compaction
� X-blocking (or X-bounding)
� X’s can be blocked before reaching the response compactor
� Can ensure that no X’s will be observed
� May result in fault coverage loss
� Add area overhead and may impact delay
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 45
Space compactionSpace compaction
� Illustration of the x-blocking scheme
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 46
Space compactionSpace compaction
� X-masking
� X’s can be masked off right before the response compactor
� Mask data is required to indicate when the
masking should take place
� Mask date can be compressed
– Possible compression techniques are weighted pseudo-random LFSR reseeding or run-length encoding
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VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 47
Space compactionSpace compaction
� An example of X-masking circuit
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Space compactionSpace compaction
� X-impact
� Simply use ATPG to algorithmically handle the impact of residual x’s on the space compactor
� Without adding any extra circuitry
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Space compactionSpace compaction
� Handling of X-impact
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Space compactionSpace compaction
� Handling of aliasing
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Test Test responseresponse compactioncompaction
� Time compaction
� A time compactor uses sequential logic to compact test responses
� MISR is most widely adopted
� n-stage MISR can be described by specifying a
characteristic polynomial of degree n
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MultipleMultiple--input signature register (MISR)input signature register (MISR)
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Test Test responseresponse compactioncompaction
� Mixed time and space compaction
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Industry practicesIndustry practices
� OPMISR+
� Embedded Deterministic Test
� Virtual Scan and UltraScan
� Adaptive Scan
� ETCompression
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Industry solutions categoriesIndustry solutions categories
� Linear-decompression-based schemes
� Two steps
– ETCompression, LogicVision
– TestKompress, Mentor Graphics
– SOCBIST, Synopsys
� Broadcast-scan-based schemes
� Single step
– SPMISR+, Cadence
– VirtualScan and UltraScan, SynTest
– DFT MAX, Synopsys
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Industry practicesIndustry practices
� OPMISR+
� Cadence
� Roots in IBM ‘s logic BIST and ATPG technology
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General scan architecture for OPMISR+ General scan architecture for OPMISR+
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Industry practicesIndustry practices
� Embedded Deterministic Test (TestKompress)
� Mentor Graphics
� First commercially available on-chip test
compression product
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EDT (EDT (TestKompressionTestKompression) architecture) architecture
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TestKompressTestKompress stimuli compressionstimuli compression
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TestKompressTestKompress response compactionresponse compaction
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Industry practicesIndustry practices
� Virtual Scan and UltraScan
� SynTest
� First commercial product based on the broadcast
scan scheme using combinational logic for pattern
decompression
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VirtualScanVirtualScan architecturearchitecture
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UltraScanUltraScan architecturearchitecture
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Industry practicesIndustry practices
� Adaptive Scan
� Synopsys
� Designed to be the next generation scan
architecture
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Adaptive scan architectureAdaptive scan architecture
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Industry practicesIndustry practices
� ETCompression
� LogicVision
� Built upon embedded logic test (ELT) technology
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ETCompressionETCompression architecturearchitecture
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Summary of industry practicesSummary of industry practices
MISR: multiple-input signature register
MUX: multiplexers
PRPG: pseudo-random pattern generator
TDDM: time-division demultiplexer
TDM: time-division multiplexers
XOR: exclusive-OR
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� Test compression is
� An effective method for reducing test data volume
and test application time with relatively small cost
� An effective test structure for embedded hard
cores
� Easy to implement and capable of producing
high-quality tests
� Successfully as part of design flow
� Need to unify different compression
architectures
Concluding remarksConcluding remarks