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EE141 – Fall 2005Lecture 16

Dynamic LogicDynamic Logic

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Administrative Stuff

Project help in labs this week

Hw 7 will be posted on Thursday

Project due Mon Oct 31 by 5pm• Electronic reports• Send report (using template from web-site) to

ee141@cory.eecs.berkeley.edu• Do NOT forget to include your SPICE file• No Slides!

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Schedule

Last lecture: • PTL

Today: • Complete PTL• Dynamic Logic

PassPass--Transistor Transistor LogicLogic

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Pass Transistor Logic (PTL)

Switch

Network

OutOut

A

B

B

BInpu

ts

N transistorsNo static power consumption

Allows primary inputs to drive S and D terminals!(idea: reduce the number of transistors)

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Example: AND Gate

B

B

A

F = AB

0

A B F0 0 00 1 01 0 01 1 1

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A = 2.5 V

B

C = 2.5V

CL

A = 2.5 V

C = 2.5 V

BM2

M1

Mn

NMOS-only Switch

VB does not pull up to 2.5V, but to 2.5V – VTn• Threshold voltage loss causes static power consumption• NMOS has higher threshold than PMOS (body effect)

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NMOS-Only Logic

0 0.5 1 1.5 20.0

1.0

2.0

3.0

Time [ns]

xOut

In

Volta

ge [V

]

VDD

In

Outx

0.5µm/0.25µm0.5µm/0.25µm

1.5µm/0.25µm

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M2

M1

Mn

Mr

OutA

B

VDDVDDLevel Restorer

X

Solution 1: Level Restoring Transistor

Advantage: Full swingRestorer adds capacitance, takes away PDN current at XRatio problem

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Restorer Sizing

0 100 200 300 400 5000.0

1.0

2.0

W/Lr =1.0/0.25 W /Lr =1.25/0.25

W/Lr =1.50/0.25

W/Lr =1.75/0.25

Time [ps]

3.0

Vol

tage

[V]

Upper limit on restorer sizePass-transistor PDN can have several transistors in stack

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Out

VDD

VDD

2.5V

VDD

0V 2.5V

0V

Watch out for leakage currents

Solution 2: Single Transistor Pass Gate with VT=0

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A

B

A

B

B B B B

A

B

A

B

F=AB

F=AB

F=A+B

F=A+B

B B

A

A

A

A

F=A⊕ΒÝ

F=A⊕ΒÝ

OR/NOR EXOR/NEXORAND/NAND

F

F

Pass-TransistorNetwork

Pass-TransistorNetwork

AABB

AABB

Inverse

(a)

(b)

Complementary Pass Transistor Logic (CPL)

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A B

C

C

A B

C

C

BCL

C = 0 V

A = 2.5 V

C = 2.5 V

Solution 3: Transmission Gate

• Bidirectionalswitch

• Rail-to-rail switching

• Requires two transistors

• More control signals needed

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Vout

0 V

2.5 V

2.5 VRn

Rp

0.0 1.0 2.00

10

20

30

Vout, V

Res

ista

nce,

ohm

s

Rn

Rp

Rn || Rp

Resistance of Transmission Gate

off

sat

sat

lin

Vout: 0 → 1

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GND

VDD

In1 In2S S

S S

Pass Transistor based Multiplexer

A M2

M1

B

S

S

S F

VDD

F A S B S= ⋅ + ⋅

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AF

A

B

BM1

M2

M3/M4

Transmission Gate XOR

• 6 transistors only

• 12 transistors in CMOS

“on” forB = 1

“on” forB = 0

B

B

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V1 Vi-1

C

2.5 2.5

0 0

Vi Vi+1

CC

2.5

0

Vn-1 Vn

CC

2.5

0

In

V1 Vi Vi+1

C

Vn-1 Vn

CC

InReqReq Req Req

CC

(a)

(b)

C

Req Req

C C

Req

C C

Req Req

C C

Req

CIn

m

(c)

Delay in Transmission Gate Networks

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Delay Optimization

Delay of RC chain

Delay of buffered chain

2)1(69.069.0

0

+== ∑

=

nnCRkCRt eq

n

keqp

bufeqp tmnmmCR

mnt

−+

+

= 12

)1(69.0

bufeq tmnmnCR

−+

+

= 12

)1(69.0

eq

bufopt CR

tm 7.1=

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Transmission Gate Full Adder

A

B

P

Ci

VDDA

A A

VDD

Ci

A

P

AB

VDD

VDD

Ci

Ci

Co

S

Ci

P

P

P

P

P

Sum Generation

Carry Generation

Setup

Similar delays for sum and carry

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Summary

Ratioed Logic• Reduced # of devices (reduced area)• Static power, increased NML

DCVSL• Differential outputs, reduced # of devices• Doubles the # of wires, increased Pdynamic

Pass-Transistor Logic• Modular design (the same gate topology…)• Need level restoration

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Practical Guidelines

Ratioed Logic, DCVSL, PTL• Reduced # of devices (area)• Difficult to design• Poor noise robustness

Static CMOS• Larger area• Easy to design• Very robust

Use CMOS in designs with no extreme area, speed or complexity

constraints

Dynamic LogicDynamic Logic

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Dynamic CMOS

In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.• fan-in of n requires 2n devices

(n N-type + n P-type)

Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.• Fan-in of n requires n + 2 transistors

(n+1 N-type + 1 P-type)

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Dynamic Gate: Basic Principle

In1

In2 PDNIn3

Me

Mp

CLK

CLKOut

CL

Out

CLK

CLK

A

BC

Mp

Me

Two phase operationPrecharge (CLK = 0)Evaluate (CLK = 1)

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Dynamic Gate

In1

In2 PDNIn3

Me

Mp

CLK

CLKOut

CL

Out

CLK

CLK

A

BC

Mp

Me

Two phase operationPrecharge (CLK = 0)Evaluate (CLK = 1)

on

off

1off

on

((AB)+C)

Out CLK A B C CLK= + ⋅ + ⋅

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Conditions on Output

Once the output of a dynamic gate is discharged, it cannot be charged again until the next prechargeoperation.

Inputs to the gate can make at most one transition during evaluation.

Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL

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Properties of Dynamic Gates

Logic function is implemented by the PDN only• number of transistors is N + 2 (versus 2N for static complementary CMOS)

Full swing outputs (VOL = GND and VOH = VDD)

Nonratioed - sizing of the devices does not affect the logic levels

Faster switching speeds• reduced load capacitance due to lower input capacitance (Cin)• reduced load capacitance due to smaller output loading (Cout)• no Isc, so all the current provided by PDN goes into discharging CL

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Overall power dissipation usually higher than static CMOS• no static current path ever exists between VDD and GND

(including Psc)• no glitching• higher transition probabilities• extra load on CLK

PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn• low noise margin (NML)

Needs a precharge/evaluate clock

Properties of Dynamic Gates

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Issues with Dynamic Gates

Charge Leakage

Charge Sharing

Capacitive Coupling

Clock Feedthrough

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CL

CLK

CLKOut

A

Mp

Me

Leakage sources

CLK

VOut

Precharge

Evaluate

Dynamic Design, Issue 1: Charge Leakage

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Solution to Charge Leakage

CL

CLK

CLK

Me

Mp

A

B

!Out

Mkp

Same approach as level restorer for pass transistor logic

Keeper

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CL

CLK

CLK

CA

CB

B=0

AOut

Mp

Me

Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness

Dynamic Design, Issue 2: Charge Sharing

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Charge Sharing Scenarios

Mp

Me

VDD

φOut

φ

A

B = 0

CL

Ca

Cb

Ma

Mb

X

CLVDD CLVout t( ) Ca VDD VTn VX( )–( )+=

or

∆Vout Vout t( ) VDD–CaCL-------- VDD VTn VX( )–( )–= =

∆Vout VDDCa

Ca CL+----------------------

–=

case 1) if ∆Vout < VTn

case 2) if ∆Vout > VTn

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Charge Sharing Example

CL=50fF

CLK

CLK

A !A

B !B B !B

C!C

Out

Ca=15fF

Cc=15fF

Cb=15fF

Cd=10fF

Worst-casecharge sharing:

!A*B*CA*!B*C

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Solution to Charge Redistribution

CLK

CLK

Me

Mp

A

B

OutMkp CLK

Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

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Dynamic Design, Issue 3: Capacitive Coupling

CL1

CLK

CLK

B=0

A=0

Out1Mp

Me

Out2

CL2In

Dynamic NAND Static NAND

=1 =1

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Capacitive Coupling Effect

-1

0

1

2

3

0 2 4 6

Vol

tage

(V)

Time (ns)

CLK

In

Out1

Out2

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Dynamic Design, Issue 4: Clock Feedthrough

CL

CLK

CLK

B

AOut

Mp

Me

Coupling between Out and CLK input of the prechargedevice due to the gate to drain capacitance…

So voltage of Out can rise above VDD.

The fast rising (and falling edges) of the clock couple to Out.

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CLK

CLK

In1

In2

In3

In4

Out

In &CLK

Out

Time (ns)

Vol

tage

(V)

Clock feedthrough

Clock feedthrough

Clock Feedthrough

-0.5

0.5

1.5

2.5

0 0.5 1

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Other Effects

Capacitive coupling (cross-talk)

Substrate coupling

Minority charge injection

Supply noise (ground bounce)

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Cascading Dynamic Gates

CLK

CLK

Out1In

Mp

Me

Mp

Me

CLK

CLK

Out2

V

t

CLK

In

Out1

Out2 ∆V

VTn

Only 0 → 1 transitions allowed at inputs!

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Cascading Dynamic Gates

Domino Logic

np-CMOS

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Domino Logic

In1

In2 PDNIn3

Me

Mp

CLK

CLK Out1

In4 PDNIn5

Me

Mp

CLK

CLKOut2

Mkp

1 → 00 → 0

1 → 1

0 → 1

Evaluation (conditional discharge)

ONLY 0→1 transitions during evaluation!

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Why Domino?

In1

CLK

CLK

Ini PDNInj

IniInj

PDN Ini PDNInj

Ini PDNInj

Like falling dominos!

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Properties of Domino Logic

Only non-inverting logic can be implemented

Very high speed• static inverter can be skewed, only L-H transition• Input capacitance reduced – smaller logical effort

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Designing with Domino Logic

Mp

Me

VDD

PDN

φ

In1In2

In3

Out1

φ

Mp

Me

VDD

PDN

φ

In4

φ

Out2

Mr

VDD

Inputs = 0during precharge

Can be eliminated!

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Footless Domino

Mp

VDD

CLK

Out1

In2 In1 1- >0 1->0

0->1

Mp

VDD

CLK

Out20- >1

In3 1->0

Mp

VDD

CLK

Outn

Inn 1->0

0->1

The first gate in the chain needs a foot switchPrecharge is rippling (next stage has to wait for propagation delay of inverter from the previous stage)

Static power consumption

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Differential (Dual Rail) Domino

A

B

Me

Mp

CLK

CLK!Out = !(AB)

!A !B

Mkp CLKOut = AB

Mkp Mp

Solves the problem of non-inverting logic

1 0 1 0

onoff

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np-CMOS

In1

In2 PDNIn3

Me

Mp

CLK

CLK Out1

In4 PUNIn5

Me

Mp!CLK

!CLK

Out2(to PDN)

1 → 11 → 0

0 → 00 → 1

Only 0 → 1 transitions allowed at inputs of PDN Only 1 → 0 transitions allowed at inputs of PUN

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NORA Logic

In1

In2 PDNIn3

Me

Mp

CLK

CLK Out1

In4 PUNIn5

Me

Mp!CLK

!CLK

Out2(to PDN)

1 → 11 → 0

0 → 00 → 1

to otherPDN’s

to otherPUN’s

WARNING: Very sensitive to noise!P-blocks are slower

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Choosing a Logic Style: No Style Fits all Needs

General design Considerations• Robustness (Static CMOS, Ratioed Logic)• Area (Pseudo-NMOS, Static CMOS)• Speed (Dynamic, Ratioed Logic)• Power (Static CMOS, Dynamic Logic)

Application-specific considerations• XOR-dominated functions (PTL)

Design tool considerations• Static CMOS

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Next Lecture

Arithmetic circuits and adders