digital system design verilog: finite state machine · 4 why fsm is important in digital design?...
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Digital System Design
Verilog: Finite State MachineDr. Bassam Jamil
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Finite State Machine (FSM) Definition
FSM is a behavioral model which is used to represent an software/hardware algorithm.
FSM consists of states, transitions State: FSM consists of finite number of states, where
each state represent unique configuration of the system.
Transition is an action initiated by a condition. It starts from one state and ends in another/same state.
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FSM Definition: More of Digital Design Definition
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Why FSM is Important in Digital Design?
Digital system design consists of: Datapath
• Adders, subtractors, multipliers, dividers
Memory • Register file, ROMs, Caches
Controller• Controls how the system execute the data
Controllers are implemented using FSMs
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FSM Types: Mealy vs. Moore
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FSM Types: FSM Output
The FSM output is specified based on the FSM type:
• Moore: output is specified in the state
• Mealy: output is specified on the transition
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Mealy vs. Moore
Comparison Mealy machine uses fewer states Mealy machine responds faster Mealy machine may be transparent to glitches
Which one is better? Depends who you ask. In the industry, they prefer
Moore. Why?• It is not recommended to have the output influenced by input
port. • Most of the time you are better off Flopping/Latching the input
ports of your design
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State Assignment
State assignment: assign binary representations to symbolic states
In a synchronous FSM All assignments work Good assignment reduce the complexity of next-
state/output logic
Typical assignment Binary, Gray, one-hot, almost one-hot
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State Assignment (Encoding)
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Gray Encoding
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One-hot Encoding
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Unused States
Some binary representations are not used. Unused means that the binary representation is not
associated with any FSM state.
What happens if the FSM enters an unused state? Ignore the condition Safe (Fault-tolerant) FSM: go to an error state or return
to the initial state.
Easy for the explicit state assignment
No portable code for the enumerated data type
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Other Types of Encoding
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FSM Example
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FSM Example: Moore Design
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FSM Example: Mealy Design
S0 S10/0 1/1
1/0
0/0
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Moore vs. Mealy (again)
Moore # states = 3 Output is generated by the state only
Mealy # states = 2 Output is generated by the state and inputs
We will implement Moore Machine in Verilog The same ideas/techniques can be implied on Mealy
implementation
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FSM Verilog Implementation: Single Always Block
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FSM Verilog Implementation: Single Always Block
endmodule
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FSM Verilog Implementation: Multiple Always Blocks
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FSM Verilog Implementation: 3-Always Block
endmodule
if (state == s1) q = 1;else q =0;
This is the recommended implementation of FSM.Last always (output) can be coded with assign statement
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FSM Implementation : Default State
endmodule
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FSM Implementation: Safe Implementation