EECE 353: Digital Systems DesignLecture 9: Adders, Subtractors, Multipliers

Cristian Grecugrecuc@ece.ubc.ca

Course web site: http://courses.ece.ubc.ca/353/

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Introduction to Lecture 9In Lab 3, your datapath containsan ALU that can perform addition,subtraction, and multiplication.

In this slide set, we will look at howto perform these operations.

Multi-cycle operation and division will come later, when we talkabout datapath circuits

“Typus Arithmeticae”, from "Margarita Philosophica," 1504 by Gregor Reisch

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Adders

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Connecting full-adders to make a multi-bit carry-propagate(ripple-carry) adder

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Carry-Lookahead Adders (Sect 5.4.1 of text)

propagateor

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Propagate

propagate

propagate

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propagate

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propagated

propagated

propagated

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7 Δ

(11+N/2)* Δ

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On the previous slide:After c4, c8, c12, … are propagated through the carry-skip structure

(chain of AND/OR gates), need to evaluate the correct partial sums.

According to slide 15, each 4-input adder block consists of 4 FA cells connected in a ripple carry structure.

For each FA cell, the delay from carry-in to carry-out is 2Δ (slide 7)For each 4-bit adder, there are 3 carry-in to carry-out transitions

Therefore, 6 Δ delay is taken by computing the correct 4-bit partial sums

For a N-bit carry-skip adder made of k-bit ripple carry adders, the critical path delay is 2(k-1)+(N/2-2)

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Carry-Select Adder

Exercise: what is the critical path delay of this adder?

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Multiplication

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Large Multipliers

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Summary of this lecture

Adders and Subtractors:- Carry-propagate adders- Carry-lookahead adders- Carry-skip adders- Carry-select adders- Carry-save adders

Multipliers:- Array multipliers

Each of these structures is “combinational” (computes the results in one cycle). We can also implement these using multi-cycle techniques using a controller and datapath. We’ll see this later in the course.