Sharif University of TechnologyDepartment of Computer Engineering

Digital System DesignDigital System DesignAn Introduction to An Introduction to VerilogVerilog®® HDLHDL

AlirezaAlireza EjlaliEjlali

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TextbookTextbook

Verilog HDLA guide to Digital Design and Synthesis

Samir Palnitkar

SunSoft Press

1996

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Hardware Description LanguagesHardware Description Languages

HDLHDLPopular Popular HDLsHDLs (IEEE Standard)(IEEE Standard)

VerilogVerilog®® ==VeriVerifying fying LogLogic ic VHDLVHDL

Other Other HDLsHDLsAHPLAHPLTITI--HDLHDLAHDLAHDL

Basic IdeaBasic IdeaProgramming LanguagesProgramming Languages

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HDL RequirementsHDL Requirements

ConcurrencyConcurrency

TimingTiming

Support for Design HierarchySupport for Design Hierarchy

Structural SpecificationStructural Specification

PragmaticsPragmatics

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ApplicationsApplications

CommunicationCommunicationHuman / ComputerHuman / ComputerHuman / HumanHuman / Human

DocumentationDocumentation

Computer Aided Design (CAD)Computer Aided Design (CAD)SimulationSimulationSynthesisSynthesis

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Why are Why are HDLsHDLs essential?essential?

SSI (Small Scale Integration)SSI (Small Scale Integration)

MSI (Medium Scale Integration)MSI (Medium Scale Integration)Paper and PencilPaper and Pencil

LSI (Large Scale Integration)LSI (Large Scale Integration)ASM (Algorithmic State Machine)ASM (Algorithmic State Machine)

VLSI (Very Large Scale Integration)VLSI (Very Large Scale Integration)CAD (CAD (HDLsHDLs))

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VerilogVerilog VS. VHDLVS. VHDL

VHDLVHDLMore general language More general language Not all constructs are synthesizableNot all constructs are synthesizable

VerilogVerilogNot as general as VHDLNot as general as VHDLMost constructs are synthesizableMost constructs are synthesizable

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Design FlowDesign Flow

1.1. Design specificationDesign specification

2.2. Behavioral descriptionBehavioral description

3.3. RTL descriptionRTL description

4.4. Functional verification and testingFunctional verification and testing

5.5. Logic synthesisLogic synthesis

6.6. GateGate--level level netlistnetlist

7.7. Logical verification and testingLogical verification and testing

8.8. Floor planning, automatic place & routeFloor planning, automatic place & route

9.9. Physical layoutPhysical layout

10.10. Layout verificationLayout verification

11.11. ImplementationImplementation

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Popularity of Popularity of VerilogVerilog HDLHDL

Easy to learn, Easy to writeEasy to learn, Easy to write

Similar in Syntax to CSimilar in Syntax to C

Allows different levels of abstraction and Allows different levels of abstraction and mixing themmixing them

Supported by most popular CAD tools and Supported by most popular CAD tools and vendorsvendors

PLI to customize PLI to customize VerilogVerilog simulators to simulators to designersdesigners’’ needsneeds

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Design MethodologiesDesign Methodologies

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44--bit Ripple Carry Counterbit Ripple Carry Counter

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TT--flipflopflipflop and the Hierarchyand the Hierarchy

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ModulesModules

modulemodule <<module_namemodule_name>>((<<module_terminal_listmodule_terminal_list>>););......<module internals> <module internals> ......

endmoduleendmodule

Example:Example:modulemodule T_ffT_ff((qq, clock, reset, clock, reset););

......<functionality of <functionality of T_flipflopT_flipflop> > ......

endmoduleendmodule

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Ripple Carry Counter (Structural)Ripple Carry Counter (Structural)module module ripple_carry_counter(qripple_carry_counter(q, , clkclk, reset);, reset);

output [3:0] q; output [3:0] q;

input input clkclk, reset; , reset;

//4 instances of the module TFF are created. //4 instances of the module TFF are created.

TFF tff0(q[0],clk, reset);TFF tff0(q[0],clk, reset);

TFF tff1(q[1],q[0], reset);TFF tff1(q[1],q[0], reset);

TFF tff2(q[2],q[1], reset);TFF tff2(q[2],q[1], reset);

TFF tff3(q[3],q[2], reset);TFF tff3(q[3],q[2], reset);

endmoduleendmodule

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TFF (Structural)TFF (Structural)

module module TFF(qTFF(q, , clkclk, reset);, reset);

output q; output q;

input input clkclk, reset;, reset;

wire d;wire d;

DFF dff0(q, d, DFF dff0(q, d, clkclk, reset); , reset);

not n1(d, q); // not is a not n1(d, q); // not is a VerilogVerilog provided primitive.provided primitive.

endmoduleendmodule

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DFF (Behavioral)DFF (Behavioral)// module DFF with asynchronous reset// module DFF with asynchronous resetmodule module DFF(qDFF(q, d, , d, clkclk, reset);, reset);output q; output q; input d, input d, clkclk, reset;, reset;regreg q;q;

always @(always @(posedgeposedge reset or reset or negedgenegedge clkclk))if (reset)if (reset)

q = 1'b0;q = 1'b0;elseelse

q = d;q = d;

endmoduleendmodule

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Test BenchTest Bench

Circuit Under Design(CUD)

84

Generatinginputs to CUD

Checkingoutputsof CUD

Test bench

Stimulus block

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Test BenchTest Benchmodule stimulus;module stimulus;regreg clkclk; ; regreg reset; wire[3:0] q;reset; wire[3:0] q;

// instantiate the design block// instantiate the design block

ripple_carry_counterripple_carry_counter r1(q, r1(q, clkclk, reset);, reset);

// Control the // Control the clkclk signal that drives the design block.signal that drives the design block.

initial initial clkclk = 1'b0;= 1'b0;always #5 always #5 clkclk = ~= ~clkclk;;

// Control the reset signal that drives the design block// Control the reset signal that drives the design blockinitialinitial

beginbeginreset = 1'b1;reset = 1'b1;

#15 reset = 1'b0;#15 reset = 1'b0;#180 reset = 1'b1;#180 reset = 1'b1;

#10 reset = 1'b0;#10 reset = 1'b0;#20 $stop;#20 $stop;

endend

initial // Monitor the outputs initial // Monitor the outputs

$$monitor($timemonitor($time, " Output q = %d", q);, " Output q = %d", q);endmoduleendmodule

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VerilogVerilog SyntaxSyntaxWhite SpaceWhite Space

Space Space \\bbTab Tab \\ttNewlineNewline \\nn

CommentsComments/* Comments *//* Comments */// Comments// Comments

Number Specification (Number Specification (‘‘b, b, ‘‘h, h, ‘‘o, o, ‘‘d)d)44’’b1111b11111212’’habchabc1616’’d255d255

Default length = at least 32, Default radix = decimalDefault length = at least 32, Default radix = decimal

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44--Value LogicValue LogicSet of values = {0,1,x,z}Set of values = {0,1,x,z}

1212’’h13x, 4h13x, 4’’b1x0zb1x0zZ=?Z=?

ExtensionExtensionFilled with x if the specified MSB is xFilled with x if the specified MSB is xFilled with z if the specified MSB is zFilled with z if the specified MSB is zZeroZero--extended otherwiseextended otherwise

66’’hx, 32hx, 32’’bz, bz, ‘‘hf0hf0

TwoTwo’’s complements complement--66’’d3 = 6d3 = 6’’d61 (d61 (-- 000011=111101)000011=111101)--66’’b01zz00 = 6b01zz00 = 6’’bxxxxxxbxxxxxx

ReadabilityReadability1616’’b0110_1011_0100_0001b0110_1011_0100_0001

U0

1

0

z

1

1

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Value SetValue Set

Value levelValue level HW ConditionHW Condition

00 Logic zero, falseLogic zero, false

11 Logic one, trueLogic one, true

xx UnknownUnknown

zz High imp., floatingHigh imp., floating

Strength levelStrength level TypeType

supplysupply DrivingDriving

strongstrong DrivingDriving

pullpull DrivingDriving

largelarge StorageStorage

weakweak DrivingDriving

mediummedium StorageStorage

smallsmall StorageStorage

highzhighz High ImpedanceHigh Impedance

In 1

In 2

Out

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Signal StrengthSignal Strength

DrivingDriving

StorageStorage

Vdd

Vdd

Vss

Vss

C

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wire and wire and regreg

wirewireUsed to represent connections between HW Used to represent connections between HW elementselementsDefault Value = zDefault Value = z

regregRetain value until next assignmentRetain value until next assignmentNOTE: this is not a hardware register or NOTE: this is not a hardware register or flipflopflipflopDefault Value = xDefault Value = x

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VectorsVectorsSyntax:Syntax:

wire/wire/regreg [[msb_indexmsb_index : : lsb_indexlsb_index] ] data_iddata_id;;

ExampleExample

wire a;wire a;wire [7:0] bus;wire [7:0] bus;wire [31:0] wire [31:0] busAbusA, , busBbusB, , busCbusC;;regreg clock;clock;regreg [0:40] [0:40] virtual_addrvirtual_addr;;

Access to parts of a vectorAccess to parts of a vector

Bus[2:0]Bus[2:0]

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Other data typesOther data types

Integer

32 bits

Integer, Real, Time,Integer, Real, Time,……

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Net Data Types (wire)Net Data Types (wire)

Nets represent physical connections Nets represent physical connections between structural entities.between structural entities.

A net value shall be determined by the A net value shall be determined by the values of its drivers. values of its drivers.

A net may have 0,1,2 or more drivers.A net may have 0,1,2 or more drivers.

If no driver is connected to a net, its If no driver is connected to a net, its value shall be highvalue shall be high--impedance (z).impedance (z).

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Example1: a net with two driversExample1: a net with two driversmodule example;module example;

regreg i1,i2,i3,i4;i1,i2,i3,i4;wire o;wire o;

and g1(o,i1,i2);and g1(o,i1,i2);or g2(o,i3,i4); or g2(o,i3,i4);

initialinitialbeginbegin

i1=0; i2=0; i3=0; i4=0;i1=0; i2=0; i3=0; i4=0;#4 i1=1; i3=1;#4 i1=1; i3=1;#4 i2=1; i4=1;#4 i2=1; i4=1;#4 i1=0; i3=1;#4 i1=0; i3=1;#4 i2=0; i4=1;#4 i2=0; i4=1;

endend

endmoduleendmodule

i1

i2

i3

i4

o

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Register Data Types (Register Data Types (regreg))

Registers are data storage elements Registers are data storage elements (like variables in programming (like variables in programming languages).languages).

A register shall store a value from A register shall store a value from one assignment to the next. one assignment to the next.

The default initialization value for a The default initialization value for a regreg data type shall be the unknown data type shall be the unknown value, x.value, x.

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Example2: Illegal reference to netsExample2: Illegal reference to netsmodule example;module example;

regreg i1,i2,i3,i4;i1,i2,i3,i4;wire o;wire o;

and g1(o,i1,i2);and g1(o,i1,i2);or g2(o,i3,i4); or g2(o,i3,i4);

initialinitialbeginbegin

i1=0; i2=0; i1=0; i2=0; o=0;o=0; //Illegal reference to net: o//Illegal reference to net: oi3=0; i4=0;i3=0; i4=0;#4 i1=1; i3=1;#4 i1=1; i3=1;#4 i2=1; i4=1;#4 i2=1; i4=1;#4 i1=0; i3=1;#4 i1=0; i3=1;#4 i2=0; i4=1;#4 i2=0; i4=1;

endendendmoduleendmodule

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Assignment 1Assignment 1

Design a 4Design a 4--bit binary adder using topbit binary adder using top--down down methodology. methodology.

Write a behavioral description for HA units.Write a behavioral description for HA units.Delay (S)= 5, Delay (C)=2Delay (S)= 5, Delay (C)=2

Use structural description for all the other Use structural description for all the other parts.parts.Write a Write a testbenchtestbench for your design.for your design.What is the delay of the 4What is the delay of the 4--bit binary adder bit binary adder (use (use ModelSimModelSim).).

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IntegerInteger

Keyword: integerKeyword: integer

integer variables are signed numbersinteger variables are signed numbers

Bit width: implementationBit width: implementation--dependent (at least 32dependent (at least 32--bits)bits)

Designer can also specify a width: Designer can also specify a width: integer [7:0] integer [7:0] tmptmp;;

Examples:Examples:

integer counter;integer counter;

initialinitial

counter = counter = --1;1;

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RealRealKeyword: realKeyword: realValues: Values:

Default value: 0Default value: 0Decimal notation: 12.24Decimal notation: 12.24Scientific notation: 3e6 (=3x10Scientific notation: 3e6 (=3x1066))

Cannot have range declarationCannot have range declarationExample:Example:

real delta;real delta;initialinitialbeginbegin

delta=4e10;delta=4e10;delta=2.13;delta=2.13;

endendinteger i;integer i;initialinitial

i = delta; // i gets the value 2 (rounded value of 2.13)i = delta; // i gets the value 2 (rounded value of 2.13)

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TimeTime

Used to store values of simulation timeUsed to store values of simulation time

Keyword: timeKeyword: time

Bit width: implementationBit width: implementation--dependent (at least 64)dependent (at least 64)

$time system function gives current simulation time$time system function gives current simulation time

Example:Example:

time time save_sim_timesave_sim_time;;

initial initial

save_sim_timesave_sim_time = $time;= $time;

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ArraysArrays

Only oneOnly one--dimensional arrays supporteddimensional arrays supportedAllowed for Allowed for regreg, , integerinteger, , time time

Not allowed for Not allowed for realreal data typedata type

Syntax:Syntax:<data_type> <<data_type> <var_namevar_name>>[[start_idxstart_idx : : end_idxend_idx]];;

Examples:Examples:integer countinteger count[0:7][0:7];;regreg boolbool[31:0][31:0];;time chk_pointtime chk_point[1:100][1:100];;regreg [4:0] port_id[4:0] port_id[0:7][0:7];;integer matrix[4:0][4:0]; // illegalinteger matrix[4:0][4:0]; // illegal

count[5]count[5]chk_point[100]chk_point[100]port_id[3]port_id[3]

Note the difference between vectors and arraysNote the difference between vectors and arrays