digital logic and verilog
TRANSCRIPT
DIGITAL LOGIC AND VERILOG
GRAPHIC INPUT
RTL Diagram for the circuit
GRAPHIC INPUT -RESULTS
FULL ADDERS – 16 BIT AND 4 BIT
FULL ADDERS – 16 BIT AND 4 BIT – VERIFICATION RESULTS
FINITE STATE MACHINE- MOORE
FINITE STATE MACHINE- MOORE – VERIFICATION RESULTS
FINITE STATE MACHINE- MEALY
FINITE STATE MACHINE- MEALY – VERIFICATION RESULTS
ENCODER 3:8 BIT
DECODER 8:1 TEST RESULTS
12 BIT TWO’S COMPLEMENT ALU TEST RESULTS -1
12 BIT TWO’S COMPLEMENT ALU TEST RESULTS -2
12 BIT TWO’S COMPLEMENT ALU TEST RESULTS -3
12 BIT TWO’S COMPLEMENT ALU TEST RESULTS -4
8 BIT BARREL SHIFT REGISTER
8 BIT BARREL SHIFT REGISTER – TEST RESULT
STACK – PUSH AND POP
ALU TESTER
ALU TESTER – VERIFICATION AND TEST RESULT