verilog for digital design copyright © 2007 frank vahid and roman lysecky 1 verilog for digital...

Verilog for Digital DesignCopyright © 2007 Frank Vahid and Roman Lysecky

1

Verilog for Digital Design

Chapter 3:

Sequential Logic Design


2

Introduction

• Sequential circuit– Output depends not just on present inputs (as in

combinational circuit), but on past sequence of inputs• Stores bits, also known as having “state”

– Simple example: a circuit that counts up in binary

• In this chapter, we will:– Design a new building block, a flip-flop, that stores

one bit

– Combine that block to build multi-bit storage – a register

– Describe the sequential behavior using a finite state machine

– Convert a finite state machine to a controller – a sequential circuit having a register and combinational logic

3.1

si

ze

ansis

Combinational

digital circuit

1a

b

1F0

1a

b? F0

Must know sequence of past inputs to know

output

Sequential

digital circuit

Note: Slides with animation are denoted with a small red "a" near the animated items


Example Needing Bit Storage

• Flight attendant call button– Press call: light turns on

• Stays on after button released

– Press cancel: light turns off

– Logic gate circuit to implement this?

QCall

Cancel

Doesn’t work. Q=1 when Call=1, but doesn’t stay 1 when Call returns to 0

Need some form of “feedback” in the circuit

a

a

3.2

BitStorage

Blue lightCallbutton

Cancelbutton

1. Call button pressed – light turns on

BitStorage


Cancelbutton

2. Call button released – light stays on

BitStorage


Cancelbutton

3. Cancel button pressed – light turns off


4

Clocks

• Clock period: time interval between pulses – Above signal: period = 20 ns

• Clock cycle: one such time interval– Above signal shows 3.5 clock cycles

• Clock frequency: 1/period– Above signal: frequency = 1 / 20 ns = 50 MHz

• 1 Hz = 1/s

100 GHz10 GHz1 GHz

100 MHz10 MHz

0.01 ns0.1 ns

1 ns10 ns

100 ns

PeriodFreq


5

D Flip-Flop• Flip-flop: Bit storage that stores on clock edge, not level • One design -- master-servant

– Two latches, output of first goes to input of second, master latch has inverted clock signal

– So master loaded when C=0, then servant when C=1– When C changes from 0 to 1, master disabled, servant

loaded with value that was at D just before C changed -- i.e., value at D during rising edge of C

Clk

D/Dm

Qm/Ds

Cm

Cs

Qs

Clk

rising edges

Note: Hundreds of different flip-flop designs

exist

D latch

master

D latch

servant

D Dm Ds

Cs

Qm Qs’

Qs Q

Q’

Cm

Clk

D flip-flop


6

D Flip-Flop

D Q’

Q

Q’D

Q

Symbol for rising-edge

triggered D flip-flop

Symbol for falling-edge

triggered D flip-flop

Clk

rising edges

Clk

falling edges

Internal design: Just invert servant clock rather than master

The triangle means clock input, edge triggered


7

D Flip-Flop• Solves problem of not knowing through how many latches a signal

travels when C=1 – In figure below, signal travels through exactly one flip-flop, for Clk_A or

Clk_B– Why? Because on rising edge of Clk, all four flip-flops are loaded

simultaneously -- then all four no longer pay attention to their input, until the next rising edge. Doesn’t matter how long Clk is 1.

Two latches inside each flip-flop

D1 Q1 D2 Q2 D3 Q3 D4 Q4Y

Clk

Clk_A Clk_B

Two lat

fli


8

Flight-Attendant Call Button Using D Flip-Flop

• D flip-flop will store bit• Inputs are Call, Cancel, and present value

of D flip-flop, Q• Truth table shown below

Preserve value: if Q=0, make D=0; if Q=1, make D=1

Cancel -- make D=0

Call -- make D=1

Let’s give priority to Call -- make

D=1

Circuit derived from truth table, using Chapter 2 combinational

logic design process

Call

button

Cancel

button

Flight

attendant

call-button

system

Blue

light

D Q’

QClk

Callbutton

Cancelbutton

Blue

light

Call

Cancel

Q


9

Basic Register• Typically, we store multi-bit items

– e.g., storing a 4-bit binary number

• Register: multiple flip-flops sharing clock signal– From this point, we’ll use registers for bit storage

• No need to think of latches or flip-flops• But now you know what’s inside a register

DQ

DQ

DQ

DQ

I2I3

Q2Q3 Q1 Q0

I1 I0

clk

4-bit register

I3 I2 I1 I0

Q3 Q2Q1Q0

reg(4)


10

Example Using Registers: Temperature Display• Temperature history display

– Sensor outputs temperature as 5-bit binary number– Timer pulses C every hour– Record temperature on each pulse, display last three recorded values

a4x4x3x2x1x0

C

a3a2a1a0

tempe

rature

sensor

timer

Display

Present

b4b3b2b1b0

Display

TemperatureHistoryStorage

1 hour ago

c4 c3 c2 c1c0

Display

2 hours ago

(In practice, we would actually avoid connecting the timer output

C to a clock input, instead only connecting an oscillator output to a clock input.)


11

Example Using Registers: Temperature Display

• Use three 5-bit registers

15 18 20

0

0

0

18

0

0

21

18

0

24

21

18

25

24

21

26

25

24

27

26

25

21 21 22 24 24 24 25 25 26 26 26 27 27 27 27x4...x0

C

Ra

Rb

Rc

Q4

C

x4x3x2x1x0

Q3Q2Q1Q0

Ra Rb

I4I3I2I1I0

Q4

a4 a3 a2 a1 a0

Q3Q2Q1Q0

I4I3I2I1I0

Rc

Q4

b4 b3 b2 b1 b0

Q3Q2Q1Q0

I4I3I2I1I0

c4 c3 c2 c1 c0

TemperatureHistoryStorage


12

D Latch vs. D Flip-Flop• Latch is level-sensitive: Stores D when C=1• Flip-flop is edge triggered: Stores D when C changes from 0 to 1

– Saying “level-sensitive latch,” or “edge-triggered flip-flop,” is redundant– Two types of flip-flops -- rising or falling edge triggered.

• Comparing behavior of latch and flip-flop:

Clk

D

Q (D latch)

Q (D flip-flop) 10

87

654

9

3

1 2


13

Register Behavior


14

Register Behavior• Sequential circuits have storage• Register: most common storage component

– N-bit register stores N bits– Structure may consist of connected flip-flops

I3 I2 I1 I0

Q3Q2Q1Q0

reg(4)Rst

I2I3

Q2Q3 Q1 Q0

I1 I0

Clk

4-bit register

D

Q

R

D

Q

R

D

Q

R

D

Q

R

Rst


15

Register BehaviorVectors

• Typically just describe register behaviorally

– Declare output Q as reg variable to achieve storage

• Uses vector types– Collection of bits

• More convenient than declaring separate bits like I3, I2, I1, I0

– Vector's bits are numbered• Options: [0:3], [1:4], etc.• [3:0]

– Most-significant bit is on left– Assign with binary constant (more

on next slide)

`timescale 1 ns/1 ns

module Reg4(I, Q, Clk, Rst); input [3:0] I; output [3:0] Q; reg [3:0] Q; input Clk, Rst; always @(posedge Clk) begin if (Rst == 1 ) Q <= 4'b0000; else Q <= I; endendmodule

vldd_ch3_Reg4.v

I3 I2 I1 I0

Q3Q2Q1Q0

reg(4)Rst

I3 I2 I1 I0

module Reg4(I3,I2,I1,I0,Q3,...);input I3, I2, I1, I0;

module Reg4(I, Q, ...); input [3:0] I;

I:I[3]I[2]I[1]I[0]


16

Register BehaviorConstants

• Binary constant– 4'b0000

• 4: size, in number of bits• 'b: binary base• 0000: binary value

• Other constant bases possible– d: decimal base, o: octal base, h: hexadecimal

base– 12'hFA2

• 'h: hexadecimal base• 12: 3 hex digits require 12 bits• FA2: hex value

– Size is always in bits, and optional • 'hFA2 is OK

– For decimal constant, size and 'd optional• 8'd255 or just 255 • In previous uses like “A <= 1;” 1 and 0 are

actually decimal numbers. ‘b1 and ‘b0 would explicitly represent bits

• Underscores may be inserted into value for readability

– 12'b1111_1010_0010– 8_000_000



vldd_ch3_Reg4.v

I3 I2 I1 I0

Q3Q2Q1Q0

reg(4)Rst


17



Register Behavior• Procedure's event control

involves Clk input– Not the I input. Thus,

synchronous– "posedge Clk"

• Event is not just any change on Clk, but specifically change from 0 to 1 (positive edge)

• negedge also possible

• Process has synchronous reset– Resets output Q only on rising

edge of Clk

• Process writes output Q– Q declared as reg variable,

thus stores value too

vldd_ch3_Reg4.v

I3 I2 I1 I0

Q3Q2Q1Q0

reg(4)Rst


18

Register BehaviorTestbench

• reg/wire declarations and module instantiation similar to previous testbenches

• Module uses two procedures– One generates 20 ns clock

• 0 for 10 ns, 1 for 10 ns• Note: always procedure

repeats

– Other provides values for inputs Rst and I (i.e., vectors)

• initial procedure executes just once, does not repeat

• (more on next slide)

vldd_ch3_Reg4TB.v


module Testbench(); reg [3:0] I_s; reg Clk_s, Rst_s; wire [3:0] Q_s;

Reg4 CompToTest(I_s, Q_s, Clk_s, Rst_s); // Clock Procedure always begin Clk_s <= 0; #10; Clk_s <= 1; #10; end // Note: Procedure repeats // Vector Procedure initial begin Rst_s <= 1; I_s <= 4'b0000; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b0000; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1010; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1111; endendmodule


19


• Variables/nets can be shared between procedures

– Only one procedure should write to variable

• Variable can be read by many procedures

• Clock procedure writes to Clk_s• Vector procedures reads Clk_s

• Event control "@(posedge Clk_s)"– May be prepended to statement

to synchronize execution with event occurrence

• Statement may be just ";" as in example

• In previous examples, the “statement” was a sequential block (begin-end)

– Test vectors thus don't include the clock's period hard coded

• Care taken to change input values away from clock edges

vldd_ch3_Reg4TB.v



Reg4 CompToTest(I_s, Q_s, Clk_s, Rst_s); // Clock Procedure always begin Clk_s <= 0; #10; Clk_s <= 1; #10; end // Note: Procedure repeats // Vector Procedure initial begin Rst_s <= 1; I_s <= 4'b0000; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b0000; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1010; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1111; endendmodule


20


• Simulation results– Note that Q_s updated only

on rising clock edges– Note Q_s thus unknown until

first clock edge• Q_s is reset to “0000” on

first clock edgevldd_ch3_Reg4TB.v

... always @(posedge Clk) begin if (Rst == 1 ) Q <= 4'b0000; else Q <= I; end... vldd_ch3_Reg4.v

...

// Vector Procedure initial begin Rst_s <= 1; I_s <= 4'b0000; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b0000; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1010; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1111; end

I_s

Q_s

time (ns)10 20 30 40

Clk_s

50 70

0000 1010 1111

xxxx 0000 1010 1111

Rst_s

60 80

Remember that Q_s is connected to Q, and I_s to I, in the testbench

Initial value of a bit is the unknown value x


21

Common Pitfalls

• Using "always" instead of "initial" procedure– Causes repeated procedure execution

• Not including any delay control or event control in an always procedure– May cause infinite loop in the simulator

• Simulator executes those statements over and over, never executing statements of another procedure

• Simulation time can never advance

– Symptom – Simulator appears to just hang, generating no waveforms

// Vector Procedure always begin Rst_s <= 1; I_s <= 4'b0000; @(posedge Clk_s); ... @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1111; end

// Vector Procedure always begin Rst_s <= 1; I_s <= 4'b0000; end

time (ns)

I_s

Q_s

10 20 30 40

Clk_s

50 70

Rst_s

60 80


22

Common Pitfalls

• Not initializing all module inputs– May cause undefined outputs

– Or simulator may initialize to default value. Switching simulators may cause design to fail.

– Tip: Immediately initialize all module inputs when first writing procedure

// Vector Procedure always begin Rst_s <= 1; I_s <= 4'b0000; @(posedge Clk_s); ... @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1111; end


23

Common Pitfalls• Forgetting to explicitly declare as a wire

an indentifier used in a port connection– e.g., Q_s – Verilog implicitly declares identifier as a

net of the default net type, typically a one-bit wire

• Intended as shortcut to save typing for large circuits

• May not give warning message during compilation

• Works fine if a one-bit wire was desired

• But may be mismatch – in this example, the wire should have been four bits, not one bit

• Unexpected simulation results

– Always explicitly declare wires• Best to avoid use of Verilog's implicit

declaration shortcut



Reg4 CompToTest(I_s, Q_s, Clk_s, Rst_s); ...


24

Finite-State Machines (FSMs)—Sequential Behavior


Finite-State Machines (FSMs) and Controllers

• Want sequential circuit with particular behavior over time

• Example: Laser timer– Push button: x=1 for 3 clock cycles

– How? Let’s try three flip-flops• b=1 gets stored in first D flip-flop• Then 2nd flip-flop on next cycle, then

3rd flip-flop on next• OR the three flip-flop outputs, so x

should be 1 for three cycles

3.3

Controllerx

b

clk

laser

patient

D Q D Q D Q

clk

b

x


Need a Better Way to Design Sequential Circuits• Trial and error is not a good design method

– Will we be able to “guess” a circuit that works for other desired behavior?• How about counting up from 1 to 9? Pulsing an output for 1 cycle every 10

cycles? Detecting the sequence 1 3 5 in binary on a 3-bit input?

– And, a circuit built by guessing may have undesired behavior• Laser timer: What if press button again while x=1? x then stays one another 3

cycles. Is that what we want?

• Combinational circuit design process had two important things1. A formal way to describe desired circuit behavior

• Boolean equation, or truth table

2. A well-defined process to convert that behavior to a circuit

• We need those things for sequence circuit design


Describing Behavior of Sequential Circuit: FSM• Finite-State Machine (FSM)

– A way to describe desired behavior of sequential circuit

• Akin to Boolean equations for combinational behavior

– List states, and transitions among states

• Example: Make x change toggle (0 to 1, or 1 to 0) every clock cycle

• Two states: “Off” (x=0), and “On” (x=1)

• Transition from Off to On, or On to Off, on rising clock edge

• Arrow with no starting state points to initial state (when circuit first starts)

Outputs: x

OnOff

x=0 x=1

clk̂

clk̂

Off On Off On Off On Off On

cycle 1

Off OffOn On

cycle 2 cycle 3 cycle 4clk

state

x

Outputs:


FSM Example: 0,1,1,1,repeat

• Want 0, 1, 1, 1, 0, 1, 1, 1, ...– Each value for one clock cycle

• Can describe as FSM– Four states

– Transition on rising clock edge to next state

Off OffOn1On1On2 On2On3 On3Off

clk

x

State

Outputs:

Outputs: x

On1Off On2 On3

clk̂

clk̂

clk̂x=1x=1x=0 x=1clk̂


Extend FSM to Three-Cycles High Laser Timer

• Four states• Wait in “Off” state while b is 0 (b’) • When b is 1 (and rising clock

edge), transition to On1– Sets x=1

– On next two clock edges, transition to On2, then On3, which also set x=1

• So x=1 for three cycles after button pressed

Off OffOn1Off Off Off On2 On3Off

clk

State

Outputs:

Inputs:

x

b

On2On1 On3

Off

clk̂

clk̂

x=1x=1x=1

x=0

clk̂

b’*clk̂

b*clk̂

Inputs: b; Outputs: x


FSM Simplification: Rising Clock Edges Implicit

• Showing rising clock on every transition: cluttered– Make implicit -- assume every edge

has rising clock, even if not shown

– What if we wanted a transition without a rising edge

• We don’t consider such asynchronous FSMs -- less common, and advanced topic

• Only consider synchronous FSMs -- rising edge on every transition

Note: Transition with no associated condition thus transistions to next state on next clock cycle

On2On1 On3

Off

x=1x=1x=1

x=0

b’

b


On2On1 On3

Off

x=1x=1x=1

x=0

b’

clk̂

clk̂

^clk

*clk̂

*clk̂b


a


FSM Definition

• FSM consists of– Set of states

• Ex: {Off, On1, On2, On3}

– Set of inputs, set of outputs• Ex: Inputs: {x}, Outputs: {b}

– Initial state• Ex: “Off”

– Set of transitions• Describes next states• Ex: Has 5 transitions

– Set of actions• Sets outputs while in states• Ex: x=0, x=1, x=1, and x=1


On2On1 On3

Off

x=1x=1x=1

x=0

b’

b

We often draw FSM graphically, known as state diagram

Can also use table (state table), or textual languages


Standard Controller Architecture• How implement FSM as sequential circuit?

– Use standard architecture • State register -- to store the present state• Combinational logic -- to compute outputs, and

next state• For laser timer FSM

– 2-bit state register, can represent four states– Input b, output x

– Known as controller

a

On2On1 On3

Off

x=1x=1x=1

x=0

b’

b


Combinationallogic

State register

s1 s0

n1

n0

xb

clkFS

Min

puts

FSM

outp

uts

General version

Combinationallogic

Sm

m

N

OI

clkm-bit

state register

FSM

outp

uts

FSM

inp

uts


33


• Finite-state machine (FSM) is a common model of sequential behavior– Example: If B=1, hold X=1 for 3

clock cycles• Note: Transitions implicitly ANDed

with rising clock edge

– Implementation model has two parts:

• State register• Combinational logic

– HDL model will reflect those two parts

Inputs: B; Outputs: X

On2On1 On3

Off

X=1X=1X=1

X=0

B

B

Combinationallogic

State register

State

XB

ClkFS

Min

puts

FSM

outp

uts

StateNext


34

Finite-State Machines (FSMs)—Sequential BehaviorModules with Multiple Procedures and Shared Variables

• Code will be explained on following slides


module LaserTimer(B, X, Clk, Rst); input B; output reg X; input Clk, Rst; parameter S_Off = 0, S_On1 = 1, S_On2 = 2, S_On3 = 3; reg [1:0] State, StateNext; // CombLogic always @(State, B) begin case (State) S_Off: begin X <= 0; if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; end ...

... S_On1: begin X <= 1; StateNext <= S_On2; end S_On2: begin X <= 1; StateNext <= S_On3; end S_On3: begin X <= 1; StateNext <= S_Off; end endcase end // StateReg always @(posedge Clk) begin if (Rst == 1 ) State <= S_Off; else State <= StateNext; endendmodule

vldd_ch3_LaserTimerBeh.v


On2On1 On3

Off

X=1X=1

X=1

X=0

B

B

Combinational

logic

State register

State

XB

Clk

FSM

inp

uts

FSM

outp

uts

StateNext


35


• Modules has two procedures– One procedure for combinational

logic

– One procedure for state register

– But it's still a behavioral description


module LaserTimer(B, X, Clk, Rst); input B; output reg X; input Clk, Rst; parameter S_Off = 0, S_On1 = 1, S_On2 = 2, S_On3 = 3; reg [1:0] State, StateNext; // CombLogic always @(State, B) begin ... end // StateReg always @(posedge Clk) begin ... endendmodule

Combinationallogic

State register

State

XB

Clk

FSM

inputs

FSM

outp

uts

StateNext



36



Finite-State Machines (FSMs)—Sequential BehaviorParameters

• parameter declaration– Not a variable or net, but rather a

constant– A constant is a value that must be

initialized, and that cannot be changed within the module’s definition

– Four parameters defined• S_Off, S_On1, S_On2, S_On3• Correspond to FSM’s states

– Should be initialized to unique values



37


• Module declares two reg variables– State, StateNext– Each is 2-bit vector (need two bits to

represent four unique state values 0 to 3)– Variables are shared between CombLogic

and StateReg procedures• CombLogic procedure

– Event control sensitive to State and input B– Will output StateNext and X

• StateReg procedure– Sensitive to Clk input– Will output State, which it stores

Combinationallogic

State register

State

XB

Clk

FSM

inpu

ts

FSM

ou

tputs

StateNext





38

Finite-State Machines (FSMs)—Sequential BehaviorProcedures with Case Statements

• Procedure may use case statement– Preferred over if-else-if when just one

expression determines which statement to execute

– case (expression)• Execute statement whose case item

expression value matches case expression

– case item expression : statement– statement is commonly a begin-end

block, as in example

– First case item expression that matches executes; remaining case items ignored

– If no item matches, nothing executes– Last item may be "default : statement"

• Statement executes if none of the previous items matched

// CombLogic always @(State, B) begin case (State) S_Off: begin X <= 0; if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; end S_On1: begin X <= 1; StateNext <= S_On2; end S_On2: begin X <= 1; StateNext <= S_On3; end S_On3: begin X <= 1; StateNext <= S_Off; end endcase end



39

Finite-State Machines (FSMs)—Sequential BehaviorProcedures with Case Statements

• FSM’s CombLogic procedure– Case statement describes states– case (State)

• Executes corresponding statement (often a begin-end block) based on State's current value

– A state's statements consist of• Actions of the state• Setting of next state (transitions)

• Ex: State is S_On1 – Executes statements for state On1,

jumps to endcase

reg [1:0] State, StateNext;

// CombLogic always @(State, B) begin case (State) S_Off: begin X <= 0; if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; end S_On1: begin X <= 1; StateNext <= S_On2; end S_On2: begin X <= 1; StateNext <= S_On3; end S_On3: begin X <= 1; StateNext <= S_Off; end endcase end

Suppose State is S_On1

Inputs: X; Outputs: B

On2On1 On3

Off

X=1X=1X=1

X=0

B'

B



40


• FSM StateReg Procedure– Similar to 4-bit register

• Register for State is 2-bit vector reg variable

– Procedure has synchronous reset• Resets State to FSM’s initial state,

S_Off

... parameter S_Off = 0, S_On1 = 1, S_On2 = 2, S_On3 = 3; reg [1:0] State, StateNext;

...

// StateReg always @(posedge Clk) begin if (Rst == 1 ) State <= S_Off; else State <= StateNext; end...



41

Finite-State Machines (FSMs)—Sequential BehaviorModules with Multiple Procedures and Shared Variables

• Code should now be clear


module LaserTimer(B, X, Clk, Rst); input B; output reg X; input Clk, Rst; parameter S_Off = 0, S_On1 = 1, S_On2 = 2, S_On3 = 3; reg [1:0] State, StateNext; // CombLogic always @(State, B) begin case (State) S_Off: begin X <= 0; if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; end ...

... S_On1: begin X <= 1; StateNext <= S_On2; end S_On2: begin X <= 1; StateNext <= S_On3; end S_On3: begin X <= 1; StateNext <= S_Off; end endcase end // StateReg always @(posedge Clk) begin if (Rst == 1 ) State <= S_Off; else State <= StateNext; endendmodule



On2On1 On3

Off

X=1X=1

X=1

X=0

B

B

Combinational

logic

State register

State

XB

Clk

FSM

inp

uts

FSM

outp

uts

StateNext


42

Finite-State Machines (FSMs)—Sequential BehaviorSelf-Checking Testbenches

• FSM testbench– First part of file (variable/net declarations,

module instantiations) similar to before– Vector Procedure

• Resets FSM• Sets FSM's input values (“test vectors”)• Waits for specific clock cycles

– We observe the resulting waveforms to determine if FSM behaves correctly

... // Clock Procedure always begin Clk_s <= 0; #10; Clk_s <= 1; #10; end // Note: Procedure repeats // Vector Procedure initial begin Rst_s <= 1; B_s <= 0; @(posedge Clk_s); #5 Rst_s <= 0; @(posedge Clk_s); #5 B_s <= 1; @(posedge Clk_s); #5 B_s <= 0; @(posedge Clk_s); @(posedge Clk_s); @(posedge Clk_s); endendmodule

vldd_ch3_LaserTimerTB.v

B_s

X_s

time (ns)10 20 30 40

Clk_s

50 70

Rst_s

60 80 90 110100


43

Finite-State Machines (FSMs)—Sequential BehaviorSelf-Checking Testbenches

vldd_ch3_LaserTimerTBDisplay.v

// Vector Procedure initial begin Rst_s <= 1; B_s <= 0; @(posedge Clk_s); #5 if (X_s != 0) $display("%t: Reset failed", $time); Rst_s <= 0; @(posedge Clk_s); #5 B_s <= 1; @(posedge Clk_s); #5 B_s <= 0; if (X_s != 1) $display("%t: First X=1 failed", $time); @(posedge Clk_s); #5 if (X_s != 1) $display("%t: Second X=1 failed", $time); @(posedge Clk_s); #5 if (X_s != 1) $display("%t: Third X=1 failed", $time); @(posedge Clk_s); #5 if (X_s != 0) $display("%t: Final X=0 failed", $time); end

B_s

X_s

time (ns)10 20 30 40

Clk_s

50 70

Rst_s

60 80 90 110100

• Reading waveforms is error-prone• Create self-checking testbench

– Use if statements to check for expected values

• If a check fails, print error message• Ex: if X_s fell to 0 one cycle too

early, simulation might output:– 95: Third X=1 failed


44

Finite-State Machines (FSMs)—Sequential Behavior$display System Procedure

vldd_ch3_LaserTimerTBDisplay.v

// Vector Procedure initial begin Rst_s <= 1; B_s <= 0; @(posedge Clk_s); #5 if (X_s != 0) $display("%t: Reset failed", $time); Rst_s <= 0; @(posedge Clk_s); #5 B_s <= 1; @(posedge Clk_s); #5 B_s <= 0; if (X_s != 1) $display("%t: First X=1 failed", $time); @(posedge Clk_s); #5 if (X_s != 1) $display("%t: Second X=1 failed", $time); @(posedge Clk_s); #5 if (X_s != 1) $display("%t: Third X=1 failed", $time); @(posedge Clk_s); #5 if (X_s != 0) $display("%t: Final X=0 failed", $time); end

• $display – built-in Verilog system procedure for printing information to display during simulation

– A system procedure interacts with the simulator and/or host computer system

• To write to a display, read a file, get the current simulation time, etc.

• Starts with $ to distinguish from regular procedures

• String argument is printed literally...– $display("Hello") will print "Hello"– Automatically adds newline character

• ...except when special sequences appear– %t: Display a time expression– Time expression must be next argument

• $time – Built-in system procedure that returns the current simulation time

– 95: Third X=1 failed


Controller Example: Button Press Synchronizer

• Want simple sequential circuit that converts button press to single cycle duration, regardless of length of time that button actually pressed– We assumed such an ideal button press signal in earlier example, like the

button in the laser timer controller

cycle1 cycle2 cycle3 cycle4clk

Inputs:

Outputs:

bi

bo

Button press synchronizer

controller

bi bo


Controller Example: Button Press Synchronizer (cont)

A

B

C

s100001111

s000110011

bi01010101

Inputs

n100010100

n001000000

bo00110000

OutputsCombinational logic

unused

Step 4: State table

a

Step 1: FSM

A B C

bo=1bo=0 bo=0bi

bibi’

bi’bi’

bi

FSM inputs: bi; FSM outputs: bo

Step 3: Encode states

00 01 10

bo=1bo=0 bo=0bi

bibi’

bi’

bi’bi

FSM inputs: bi; FSM outputs: bo

Step 5: Create combinational circuit


clkState register

bo

bi

s1 s0

n1

n0

Combinational logic

n1 = s1’s0bi + s1s0bin0 = s1’s0’bibo = s1’s0bi’ + s1’s0bi = s1s0

Step 2: Create architectureCombinational

logic

n0s1 s0

n1

bobi

clk State register

FSM

inpu

ts

FSM

ou

tputs


Controller Example: Sequence Generator• Want generate sequence 0001, 0011, 1100, 1000, (repeat)

– Each value for one clock cycle– Common, e.g., to create pattern in 4 lights, or control magnets of a “stepper motor”

00

01 10

11A

B

D

wxyz=0001 wxyz=1000

wxyz=0011 wxyz=1100

C

Inputs: none; Outputs: w,x,y,z

Step 3: Encode states

Step 4: Create state tableclk State register

wx

yz

n0s0s1 n1


w = s1x = s1s0’y = s1’s0z = s1’n1 = s1 xor s0n0 = s0’

a

Step 1: Create FSM

A

B

D

wxyz=0001 wxyz=1000

wxyz=0011 wxyz=1100

C

Inputs: none; Outputs: w,x,y,z

Step 2: Create architecture

Combinationallogic

n0s1 s0

n1

clk State register

wxyz


FSM Example: Secure Car Key (cont.)

• Nice feature of FSM– Can evaluate output behavior for

different input sequence

– Timing diagrams show states and output values for different input waveforms

K1 K2 K3 K4

r=1 r=1 r=0 r=1

Waitr=0

Inputs: a;Outputs: r

a’a

Wait Wait K1 K2 K3 K4 Wait Wait

clk

Inputs

Outputs

State

a

r

clk

Inputsa

K1Wait Wait K1 K2 K3 K4 Wait

Output

State

r

Q: Determine states and r value for given input waveform:

a


Controller Example: Secure Car Key• (from earlier example)

K1 K2 K3 K4

r=1 r=1 r=0 r=1

Waitr=0

Inputs: a; Outputs: r

a’a

Ste

p 1

Combinationallogic

s2 s1 s0

n2

ra

n1n0

clk State register

Ste

p 2

a’a

r=0

r=1 r=1 r=0 r=1

000

001 010 011 100

Inputs: a;Outputs: r

Ste

p 3

Step 4

a

We’ll omit Step 5


FSM Example: Code Detector• Unlock door (u=1) only when buttons

pressed in sequence: – start, then red, blue, green, red

• Input from each button: s, r, g, b– Also, output a indicates that some

colored button pressed

• FSM– Wait for start (s=1) in “Wait”– Once started (“Start”)

• If see red, go to “Red1”• Then, if see blue, go to “Blue”• Then, if see green, go to “Green”• Then, if see red, go to “Red2”

– In that state, open the door (u=1)

• Wrong button at any step, return to “Wait”, without opening door

Start

RedGreen

Blue

s

rg

ba

Doorlock

u

Codedetector

Q: Can you trick this FSM to open the door, without knowing the code?

A: Yes, hold all buttons simultaneouslya

a

a

Wait

Start

Red1 Red2GreenBlue

s’

a’

ar’ ab’ ag’ ar’

a’

ab ag ar

a’ a’u=0

u=0ar

u=0 s

u=0 u=0 u=1

Inputs: s,r,g,b,a;Outputs: u


Improve FSM for Code Detector

• New transition conditions detect if wrong button pressed, returns to “Wait”• FSM provides formal, concrete means to accurately define desired behavior

Note: small problem still remains; we’ll discuss later

Wait

Start

Red1 Red2GreenBlue

s’

a’

a’ab ag ar

a’ a’u=0

u=0ar

u=0 s

u=0 u=0 u=1

ar’ ab’ ag’ ar’a

Inputs: s,r,g,b,a;Outputs: u


Common Pitfalls Regarding Transition Properties

• Only one condition should be true– For all transitions leaving a state

– Else, which one?

• One condition must be true– For all transitions leaving a state

– Else, where go?

a

bab=11 –

next state?

a

a’b

a

what ifab=00?

a

a’b

a’b’

a’b

a


Verifying Correct Transition Properties

• Can verify using Boolean algebra– Only one condition true: AND of each condition pair (for

transitions leaving a state) should equal 0 proves pair can never simultaneously be true

– One condition true: OR of all conditions of transitions leaving a state) should equal 1 proves at least one condition must be true

– Example

a

a’b

a + a’b= a*(1+b) + a’b= a + ab + a’b= a + (a+a’)b= a + bFails! Might not be 1 (i.e., a=0, b=0)

a

Q: For shown transitions, prove whether:* Only one condition true (AND of each pair is always 0)* One condition true (OR of all transitions is always 1)

a * a’b= (a * a’) * b= 0 * b= 0OK!

Answer:


Evidence that Pitfall is Common• Recall code detector FSM

– We “fixed” a problem with the transition conditions

– Do the transitions obey the two required transition properties?

• Consider transitions of state Start, and the “only one true” property

Wait

Start

Red1 Red2GreenBlue

s’

a’

a’ab ag ar

a’ a’u=0

u=0ar

u=0s

u=0 u=0 u=1

a

ar * a’ a’ * a(r’+b+g) ar * a(r’+b+g) = (a*a’)r = 0*r = (a’*a)*(r’+b+g) = 0*(r’+b+g) = (a*a)*r*(r’+b+g) = a*r*(r’+b+g) = 0 = 0 = arr’+arb+arg

= 0 + arb+arg = arb + arg = ar(b+g) Fails! Means that two of Start’s

transitions could be true

Intuitively: press red and blue buttons at same time: conditions ar, and a(r’+b+g) will both be true. Which one should be taken?

Q: How to solve? a

A: ar should be arb’g’(likewise for ab, ag, ar)

Note: As evidence the pitfall is common,we admit the mistake was not intentional. A reviewer of the book caught it.


Simplifying Notations

• FSMs– Assume unassigned output

implicitly assigned 0

• Sequential circuits– Assume unconnected clock inputs

connected to same external clock

a=0b=1c=0

a=0b=0c=1

b=1 c=1

clk a

a

a


More on Flip-Flops and Controllers

• Other flip-flop types– SR flip-flop: like SR latch, but edge triggered

– JK flip-flop: like SR (SJ, RK)• But when JK=11, toggles• 10, 01

– T flip-flop: JK with inputs tied together• Toggles on every rising clock edge

– Previously utilized to minimize logic outside flip-flop• Today, minimizing logic to such extent is not as important• D flip-flops are thus by far the most common

3.5


Non-Ideal Flip-Flop Behavior• Can’t change flip-flop input too close to clock edge

– Setup time: time that D must be stable before edge• Else, stable value not present at internal latch

– Hold time: time that D must be held stable after edge• Else, new value doesn’t have time to loop around and

stabilize in internal latch

clk

D

clk

D

setup time

hold time

R

SD

C

u

D latch

Q

Q’1

2

3 4

5 6

7

C

D

S

u

R

Q’

Q

Setup time violation

Leads to oscillation!


Metastability• Violating setup/hold time can lead to bad

situation known as metastable state– Metastable state: Any flip-flop state other than

stable 1 or 0• Eventually settles to one or other, but we don’t

know which

– For internal circuits, we can make sure observe setup time

– But what if input comes from external (asynchronous) source, e.g., button press?

• Partial solution– Insert synchronizer flip-flop for asynchronous

input• Special flip-flop with very small setup/hold time

– Doesn’t completely prevent metastability

clk

D

Q

setup timeviolation

metastablestate

ai

ai

synchronizer

a


Metastability• One flip-flop doesn’t completely solve problem

• How about adding more synchronizer flip-flops?– Helps, but just decreases probability of metastability

• So how solve completely?– Can’t! May be unsettling to new designers. But we just can’t guarantee a design that

won’t ever be metastable. We can just minimize the mean time between failure (MTBF) -- a number often given along with a circuit

ai

synchronizers

lowverylow

veryverylow

incrediblylow

Probability of flip-flop being metastable is…


Flip-Flop Set and Reset Inputs

• Some flip-flops have additional inputs– Synchronous reset: clears Q to 0 on

next clock edge

– Synchronous set: sets Q to 1 on next clock edge

– Asynchronous reset: clear Q to 0 immediately (not dependent on clock edge)

• Example timing diagram shown

– Asynchronous set: set Q to 1 immediately

D Q’

QR

Q’

AR

D

Q

Q’

AS

ARD

Q

cycle 1 cycle 2 cycle 3 cycle 4clk

D

AR

Q


Initial State of a Controller

• All our FSMs had initial state– But our sequential circuit designs did

not

– Can accomplish using flip-flops with reset/set inputs

• Shown circuit initializes flip-flops to 01

– Designer must ensure reset input is 1 during power up of circuit

• By electronic circuit design

Inputs: x; Outputs: b

On2On1 On3

Off

x=1x=1x=1

x=0

b’

b

D Q’ Q’

QR S

D

Q

State registerclk

reset

s1 s0n0

n1

b xCombinational

logic


63

Top-Down Design – FSMs to Controller Structure


64

Top-Down Design – FSMs to Controller Structure• Recall from Chapter 2

– Top-down design• Capture behavior, and simulate• Capture structure (circuit),

simulate again• Gets behavior right first,

unfettered by complexity of creating structure

• Capture behavior: FSM• Capture structure: Controller

– Create architecture (state register and combinational logic)

– Encode states– Create stable table (describes

combinational logic)– Implement combinational logic

Capture behavior

SimulateW_s

P_sS_s

K_s

Capture structure

SimulateW_s

P_sS_s

K_s

Should be the same

Combinationallogic

State register

S1 S0

N1

N0

XB

Clk

FSMoutputs

FSM

inputs

FSM

outp

uts

X=1 X=1 X=1

X=0

B

B'

01

00

10 11On2On1

Off

On3

Inputs: B; Outputs: X LaserTimer example


65









X=1 X=1 X=1

X=0

B

B'

01

00

10 11On2On1

Off

On3

Inputs: B; Outputs: XFSMoutputsCombinational

logic

State register

s1 s0

n1

n0

xb

clk

FSM

outputs

FSM

inpu

ts

FSM

outp

uts

Combinationallogic

State register

s1 s0

n1

n0

xb

clk

FSM

outputs

FSM

inpu

ts

FSM

outp

uts


66









X=1 X=1 X=1

X=0

B

B'

01

00

10 11On2On1

Off

On3

Inputs: B; Outputs: XFSMoutputsCombinational

logic

State register

s1 s0

n1

n0

xb

clk

FSM

outputs

FSM

inpu

ts

FSM

outp

uts

Combinationallogic

State register

s1 s0

n1

n0

xb

clk

FSM

outputs

FSM

inpu

ts

FSM

outp

uts

X = S1 + S0N1 = S1’S0 + S1S0’N0 = S1’S0’B + S1S0’


67

Controller Structure

• Structural description• Test with LaserTimerTB

– Same results

FSMoutputs

X = S1 + S0N1 = S1’S0 + S1S0’N0 = S1’S0’B + S1S0’


module LaserTimer(B, X, Clk, Rst); input B; output reg X; input Clk, Rst; parameter S_Off = 2'b00; reg [1:0] State, StateNext; // State encodings: // S_Off 00, S_On1 01, S_On2 10, S_On3 11 // CombLogic always @(State, B) begin X <= State[1] | State[0]; StateNext[1] <= (~State[1] & State[0]) | (State[1] & ~State[0]); StateNext[0] <= (~State[1] & ~State[0] & B) | (State[1] & ~State[0]); end

// StateReg always @(posedge Clk) begin if (Rst == 1 ) State <= S_Off; else State <= StateNext; endendmodule

Combinationallogic

State register

S1 S0

N1

N0

XB

Clk

FSMoutputs

FSM

inp

uts

FSM

outp

uts

vldd_ch3_LaserTimerStruct.v

B_s

X_s

time (ns)10 20 30 40

Clk_s

50 70

Rst_s

60 80 90 110100


68

Controller Structure

• Initial state is S_Off– Encoded as "00"– State register set to

S_Off during FSM reset

• Note that CombLogic uses equations, not case statement

– Actually CombLogic is still behavioral

– Do top-down design again, this time on CombLogic, to get structure

FSMoutputs

vldd_ch3_LaserTimerStruct.v


module LaserTimer(B, X, Clk, Rst); input B; output reg X; input Clk, Rst; parameter S_Off = 2'b00; reg [1:0] State, StateNext; // State encodings: // S_Off 00, S_On1 01, S_On2 10, S_On3 11 // CombLogic always @(State, B) begin X <= State[1] | State[0]; StateNext[1] <= (~State[1] & State[0]) | (State[1] & ~State[0]); StateNext[0] <= (~State[1] & ~State[0] & B) | (State[1] & ~State[0]); end

// StateReg always @(posedge Clk) begin if (Rst == 1 ) State <= S_Off; else State <= StateNext; endendmodule


69

Common Pitfall: Not Assigning Every Output in Every State

• FSM outputs should be combinational function of current state (for Moore FSM)

• Not assigning output in given state means previous value is remembered– Output has memory– Behavior is not an FSM

• Solution 1– Be sure to assign every output

in every state

• Solution 2– Assign default values before

case statement– Later assignment in state

overwrites default

// CombLogic always @(State, B) begin X <= 0; case (State) S_Off: begin X <= 0; if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; end S_On1: begin X <= 1; StateNext <= S_On2; end S_On2: begin X <= 1; StateNext <= S_On3; end S_On3: begin X <= 1; StateNext <= S_Off; end endcase end

Could delete this without changing

behavior (but probably clearer to

keep it)


70

Common Pitfall: Not Assigning Every Output in Every State

• Solution 2– Assign default values before

case statement

– Later assignment in state overwrites default

– Helps clarify which actions are important in which state

– Corresponds directly to the common simplifying FSM diagram notation of implicitly setting unassigned outputs to 0

TSA=0B=1C=0

A=0B=0C=1

TS

B=1 C=1

case State S: begin A <= 0; B <= 1; C <= 0; end T: begin A <= 0; B <= 0; C <= 1; endendcase A <= 0;B <= 0;C <= 0;case State S: begin B <= 1; end T: begin C <= 1; endendcase


71

More Simulation Concepts


72

The Simulation Cycle• Instructive to consider how an HDL

simulator works– HDL simulation is complex; we'll introduce

simplified form

• Consider example SimEx1– Three reg variables – Q, Clk, S– Three procedures – P1, P2, P3

• Simulator's job: Determine values for nets and variables over time– Repeatedly executes and suspends

procedures• Note: Actually considers more objects,

known collectively as processes, but we'll keep matters simple here to get just the basic idea of simulation

– Maintains a simulation time Time


module SimEx1(Q);

output reg Q; reg Clk, S;

// P1 always begin Clk <= 0; #10; Clk <= 1; #10; end

// P2 always @(S) begin Q <= ~S; end

// P3 initial begin @ (posedge Clk); S <= 1; @ (posedge Clk); S <= 0; end

endmodule

vldd_ch3_SimEx1.v


73

The Simulation Cycle• Start of simulation

– Simulation time Time is 0– Bit variables/nets initialized to the unknown value x– Execute each procedure

• In any order, until stops at a delay or event control


module SimEx1(Q);





endmodule

vldd_ch3_SimEx1.v

Q

Clk

SVar

iabl

es x

x

x

Start

x

0

x

0Time (ns):

P1

P2

P3

Clk <= 0, then stop. Activate when Time is 0+10=10 ns.No actions, then stop. Activate when S changes.No actions, then stop. Activate when Clk changes to 1

Pro

cedu

res

We'll use arrow to show where a procedure stops


74

The Simulation Cycle• Simulation cycle

– Set time to next time at which a procedure activates (note: could be same as current time)

• In this case, time = 10 ns (P1 activates)

– Execute active procedures (in any order) until stops

vldd_ch3_SimEx1.v

Q

Clk

SVar

iabl

es x

x

x

Start

x

0

x

0Time (ns):

x

1

x

10

P1

P2

P3

Activate when Time is 10 ns.

Activate when S changes.

Activate when Clk changes to 1.

Pro

cedu

res

Clk <= 1, stop, activate when Time=10+10=20 ns.


module SimEx1(Q);





endmodule


75


– Set time to next time at which a procedure activates• Still 10 ns; Clk just changed to 1 (P3 activates)

– Execute active procedures (in any order) until stops

vldd_ch3_SimEx1.v

Q

Clk

SVar

iabl

es x

x

x

Start

x

0

x

0

x

1

x

10

x

1

1

10Time (ns):

P1

P2

P3



Activate when Clk changes to 1Pro

cedu

res

S <= 1, stop, activate when Clk changes to 1 again


module SimEx1(Q);





endmodule


76


– Set time to next time at which a procedure activates

• Still 10 ns; S just changed (P2 activates)

– Execute active procedures until stops

vldd_ch3_SimEx1.v

Q

Clk

S

Var

iabl

es x

x

x

Start

x

0

x

0

x

1

x

10

x

1

1

10

0

1

1

10Time (ns):

P1

P2

P3



Activate when change on Clk to 1.

Pro

cedu

res

Q <= 0 (~S), stop, activate when S changes.


module SimEx1(Q);





endmodule


77


– Set time to next time at which a procedure activates

• In this case, set Time = 20 ns (P1 activates)

– Execute active procedures until stops

vldd_ch3_SimEx1.v

Q

Clk

SVar

iabl

es x

x

x

Init

x

0

x

0

x

1

x

10

x

1

1

10

0

1

1

10Time (ns):

P1

P2

P3



Activate when change on Clk to 1.

Pro

cedu

res

Clk <= 0, stop, activate when T=20+10=30ns.

0

0

1

20


module SimEx1(Q);





endmodule


78

The Simulation Cycle• Simulation ends when user-specified time is

reached

• Variable/net values translate to waveforms

vldd_ch3_SimEx1.v

Q

Clk

S

Var

iabl

es x

x

x

Init

x

0

x

0

x

1

x

10

x

1

1

10

0

1

1

10Time (ns):

0

0

1

20

0

1

1

30

0

1

0

30

1

1

0

30

1

0

0

40

1

1

0

50

Q

Clk

SVar

iabl

es

Time (ns)

10 20 30 40 500

x

x


module SimEx1(Q);





endmodule


79

Variable Updates• Assignment using "<=" ("non blocking assignment")

doesn't change variable's value immediately– Instead, schedules a change of value by placing an

event on an event queue – Scheduled changes occur at end of simulation cycle

• Important implications– Procedure execution order in a simulation cycle doesn't

matter• Assume procedures 1 and 2 are both active

– Proc1 schedules B to be 1, but does not change the present value of B. B is still 0.

– Proc2 schedules A to be 0 (the present value of B). – At end of simulation cycle, B is updated to 1 and A to 0

– Order of assignments to different variables in a procedure doesn't matter

• Assume C was 0. Scheduled values will be C=1 and D=0, for either Proc3a or Proc3b.

– Later assignment in procedure effectively overwrites earlier assignment

• E will be updated with 0, but then by 1; so E is 1 at the end of the simulation cycle.

• Simulation cycle (revised)– Set time to next time at

which a procedure resumes– Execute active procedures– Update variables with

schedule values

Assume B is 0. Proc1: B <= ~B; Proc2: A <= B;

A will be 0, not 1.

Proc3a:C <= ~C;D <= C;

Proc3b:D <= C;C <= ~C;

Same

Proc4: E <= 0; ... E <= 1;

Recall FSM output assignment example, in which default assignments were added

before the case statement.


80

Resets


81

Resets• Reset – Behavior of a register when

a reset input is asserted• Good practice dictates having

defined reset behavior for every register

• Reset behavior should always have priority over normal register behavior

• Reset behavior– Usually clears register to 0s– May initialize to other value

• e.g., state register of a controller may be initialized to encoding of initial state of FSM

• Reset usually asserted externally at start of sequential circuit operation, but also to restart due to failure, user request, or other reason


module Reg4(I, Q, Clk, Rst);

input [3:0] I; output [3:0] Q; reg [3:0] Q; input Clk, Rst;

always @(posedge Clk) begin if (Rst == 1 ) Q <= 4'b0000; else Q <= I; endendmodule

vldd_ch3_Reg4.v

I3 I2 I1 I0

Q3Q2Q1Q0

reg(4)Rst


82

RstClk

QI

xxxx

Synchronous Reset• Previous examples used

synchronous resets– Rst input only considered

during rising clock `timescale 1 ns/1 ns



always @(posedge Clk) begin if (Rst == 1 ) Q <= 4'b0000; else Q <= I; endendmodule

vldd_ch3_Reg4.v

I3 I2 I1 I0

Q3Q2Q1Q0

reg(4)Rst

Rst=1 has no effect until rising clock


83

RstClk

QI

xxxx

Asynchronous Reset• Can also use asynchronous

reset– Rst input considered

independently from clock• Add "posedge Rst" to

sensitivity list`timescale 1 ns/1 ns



always @(posedge Clk, posedge Rst) begin if (Rst == 1 ) Q <= 4'b0000; else Q <= I; endendmodule

vldd_ch3_Reg4AsyRst.v

I3 I2 I1 I0

Q3Q2Q1Q0

reg(4)Rst

RstClk

QI

Asynchronous reset

Synchronous reset

Rst=1 has almost immediate effect

Rst=1 has no effect until next rising clock


84

Asynchronous Reset

• Could have used asynchronous reset for FSM state register too

... // StateReg always @(posedge Clk, posedge Rst) begin if (Rst == 1 ) State <= S_Off; else State <= StateNext; end...

vldd_ch3_LaserTimerBehAsyRst.v

... // StateReg always @(posedge Clk) begin if (Rst == 1 ) State <= S_Off; else State <= StateNext; end...

Synchronous

Asynchronous


85

Synchronous versus Asynchronous Resets

• Which is better – synchronous or asynchronous reset?– Hotly debated in design community

• Each has pros and cons – e.g., asynchronous can still reset even if clock is not functioning,

synchronous avoids timing analysis problems sometimes accompanying asynchronous designs

• We won’t try to settle the debate here

– What’s important is to be consistent throughout a design• All registers should have defined reset behavior that takes priority

over normal register behavior

• That behavior should all be synchronous reset or all be asynchronous reset

– We will use synchronous resets in all of our remaining examples


86

Describing Safe FSMs


87


• Safe FSM – If enters illegal state, transitions to a legal state

• Example– Suppose example has only three

states

– Two-bit encoding has illegal state encoding "11"

• Also known as "unreachable" state • Not possible to enter that state under

normal FSM operation• But actually possible to enter that

state due to circuit error – e.g., electrical noise that causes state register bit to switch

X=1 X=1

X=0

B

B'

01

00

10On2On1

Off



88


• Safe FSM – If enters illegal state, transitions to a legal state

• Example– Suppose example has only three

states

– Two-bit encoding has illegal state encoding "11"

– Safe implementation• Transition to appropriate legal state• Even though that undefined state

appears to be unreachable• Thus, FSM recovers from the error X=1 X=1

X=0

B

B'

01

00

10On2On1

Off

Inputs: B; Outputs: XX=0

11


89

Describing Safe FSMs in Verilog HDL

• Unsafe FSM description – Only describes legal states, ignores

illegal states

• Some synthesis tools support "safe" option during synthesis– Automatically creates safe FSM from

an unsafe FSM description

... reg [1:0] State, StateNext; always @(State, B) begin case (State) S_Off: begin X <= 0; if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; end S_On1: begin X <= 1; StateNext <= S_On2; end S_On2: begin X <= 1; StateNext <= S_Off; end endcase end...


90

Describing Safe FSMs in Verilog HDL

• Explicitly describing a safe FSM– Include case item(s) to describe illegal

states– Can use "default" case item

• Executes if State equals anything other than S_Off, S_On1, or S_On2

• Note: Use of default is wise regardless of number of states

– Even if number is power of two, because state encoding may use more than minimum number of bits

• e.g., one-hot encoding has many more illegal states than legal states

• Note: If synthesis tool support "safe" option, use it

– Otherwise, tool may automatically optimize away unreachable states to improve performance and size, but making state machine unsafe

... reg [1:0] State, StateNext; always @(State, B) begin case (State) S_Off: begin X <= 0; if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; end S_On1: begin X <= 1; StateNext <= S_On2; end S_On2: begin X <= 1; StateNext <= S_Off; end default: begin X <= 0; StateNext <= S_Off; end endcase end...

vldd_ch3_LaserTimerBehSafe.v

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