logic design in verilog reports

Use of QUARTUS Graphic input

I. Objective : To use the Quartus to build a circuit (graphic input) for the function,

F = A’B’C’ + A’BC’ + AB’C’ + ABC.

Also to obtain simulation results for all possible values.

II. Design Specification and structure :

Inputs :

A, B, C are the inputs .Total number of input values for each is 2^3=8 bits.

Outputs :

A 8 bit function ‘F’ .

Functional behavior :

F = A’B’C’ + A’BC’ + AB’C’ + ABC.

Generates an output –F .

Timing:

Operates asynchronously.

Other considerations :

None.

III. Design Structure :

Inputs are A ,B , C and the output F is F = A’B’C’ + A’BC’ + AB’C’ + ABC. This function has the following truth

table .

A B C F

0 0 0 1

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1

Table 2.1 : Truth table

IV. Design Entry :

A’B’C’ + A’BC’ + AB’C’ + ABC

F

C B A

Circuit ( RTL Viewer and schematic block diagram)

Fig 2.1 : Schematic circuit

Fig 2.2 : RTL Viewer

In this circuit , 4 AND logic units are used with one OR gate. The F resembles the function. Three inputs

are used. Corresponding, three NOT gates are also used.

Compilation report :

Fig 2.3 : Compilation report

Simulation report :

Fig 2.4 : Simulation report

Design verification plan :

a. Verification by testing the simulation.

b. All input combinations for A,B,C are applied.

c. Verify that outputs correspond to Full Adder Truth Table.

d. Input selected values of A,B and C .

e. Verify their respective outputs corresponding to the truth table.

Fig 2.5 : Verification of the truth table

These are the glitches The truth table is satisfied as A=0, B=0,

C=1 , F=0

Here A= 1 , B=0, C=1 therefore

we obtain F=0 . ( Setting

specific value for the test)

4-Bit Adders and 16-Bit Adders

I. Objective :

To build one bit adder, four but ripple carry adder and a 16 bit adder circuit using Verilog HDL ( structural

code ) .

II. Design Specification :

Inputs :

One bit adder : Two one bit vectors ( A , B) and a one bit carry- in( Cin).

4-bit ripple carry adder : Two 4-bit vectors ( A[3:0] and B[3:0]) and a one bit carry- in( Cin) which is

used to concatenate bit slices.

16 bit ripple carry adder : Two 16-bit vectors (A[15:0] and B[15:0]) and a one bit carry- in( Cin) which

is used to concatenate bit slices.

Outputs :

One bit adder : A 1- bit sum , S and a 1-bit carry out( used to concatenate bit slices and to indicate

overflow) .

4-bit ripple carry adder : A 4-bit sum, S[3:0] and a 1-bit carry out( used to concatenate bit slices and

to indicate overflow) .

16-bit ripple carry adder : A 16-bit sum , S[15:0] and a 1-bit carry out ( used to concatenate bit slices

and to indicate overflow) .


Forms S=A+B+Carry-in.

Generates carry-out as required.

Timing :

Operates asynchronously.

Generates stable sum and carry-out.

Other considerations :

None.

III. Design Structure :

Input Output

A B Cin SUM COUT

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Table 3.1 : 1-Bit full adder

Register Transfer level of the design

1bit adder :

• Sum = a’b’cin + a’bcin’ + ab’cin’ + abcin

Carry-out = a’bcin + ab’cin + abcin’ + abcin

Inputs – a,b,cin

Outputs – sum, cout

4 bit ripple carry adder :

• FA0—full adder for bit 0

Inputs– A[0], B[0], carry-in

Outputs– S[0], c0

• FA1– full adder for bit 1


Outputs– S[1], c1



Outputs– S[2], c2



Outputs– S[3], carry-out

16 bit ripple carry adder :

• SFA0

Inputs : A[3:0], B[3:0],cin

Outputs : Sum[3:0] , c0

• SFA1

Inputs: A[7:4] , B[7:4] , c0

Outputs: Sum [7:4],c1

• SFA2

Inputs : A[11:8], B[11:8] ,c1

Outputs: Sum [11:8] , c2

• SFA3

Inputs : A[15:12], B[15:12] , c2

Outputs: Sum[15:12],c3

Fig 3.1: Left – 1 bit full adder ; right -- 4-bit ripple carry adder

Fig 3.2 : 16-Bit ripple carry adder

IV. Design Entry :

1 BIT ADDER :

//1-bit full adder

// saved as fulladderonebit.v

module fulladderonebit(a,b,cin, sum, cout);

input a, b, cin;

output sum, cout;

assign sum = !a && !b && cin || !a && b && !cin || a && !b &&!cin || a && b && cin;

assign cout = !a &&b && cin || a && !b && cin || a && b&& !cin || a && b && cin;

endmodule

4- BIT RIPPLE CARRY ADDER:

//four-bit –ripple carry adder

//uses fulladderonebit.v

//saved as fourbitadder.v

module fourbitadder(A, B, cin, SUM, cout);

input [3:0] A,B;

input cin;

output [3:0] SUM;

output cout;

wire c0,c1,c2;

fulladderonebit FA3(A[3], B[3], c2, SUM[3], cout);

fulladderonebit FA2(A[2], B[2], c1, SUM[2], c2);

fulladder onebitFA1(A[1], B[1], c0, SUM[1], c1);

fulladder onebitFA0(A[0], B[0], cin, SUM[0], c0);

endmodule

16- BIT RIPPLE CARRY ADDER:

//16 bit ripple carry adder

//uses fourbitadder.v

//uses onebitadder.v

//saved as sixteenbitadder.v

module sixteenbitadder(A, B, cin, SUM, cout);

input [15:0] A,B;

input cin;

output [15:0] SUM;

output cout;

wire c0,c1,c2;

fourbitadder FA3(A[15:12], B[15:12], c2, SUM[15:12], cout);

fourbitadder FA2(A[11:8], B[11:8], c1, SUM[11:8], c2);

fourbitadder FA1(A[7:4], B[7:4], c0, SUM[7:4], c1);

fourbitadder FA0(A[3:0], B[3:0], cin, SUM[3:0], c0);

endmodule

The one bit adder is used in the four bit ripple carry adder and these two are further extended to

form a 16-bit ripple carry adder.

V. Reports :

A. Compilation report :

Fig 3.3 : 1-bit Full adder compilation result

Fig 3.4 : 4-bit ripple carry adder compilation result

Fig 3.5 : 16-Bit ripple carry adder

B. RTL report :

Fig 3.6 : 1-bit full adder

Fig 3.7 : 4-bit ripple carry full adder

Fig 3.8 : 16 bit ripple carry full adder

C. Simulation report :

These are glitches

Fig 3.9 : 1- bit full adder simulation

Fig 3.10: 4-bit ripple carry adder simulation result

Fig 3.11: 16-bit ripple carry adder simulation result

VI. Design Verification / Test Plan :

Test Plan

Considering a given truth table ( as of table 3.2 and table 3.3 )

Simulating the above Verilog codes for 4-bit and 16-bit ripple carry adder .

Input values are assigned as of the truth table in table 3.2 and table 3.3

Comparing the output values obtained from the simulation and the truth table.

Test Input Output

A(Hex) B(Hex) Carry-in Sum(Hex) Carry-out

1 A 5 0 F 0

2 A 5 1 0 1

3 B 5 0 0 1

Table 3.2 : 4-bit AND 16-bit ripple carry adder testing truth table

Test Simulation report :

Fig 3.10 : 4-bit ripple carry adder test simulation result

Fig 3.13: 16- bit ripple carry adder test simulation result 1

Its seen that A +5 = F. The

truth table in test plan

satisfies These are because the transition of A and B are so

quick that it forces into the adder

Here it can be

seen that 3+4 = 7 These are glitches

Fig 3.12: 16-bit ripple carry adder test simulation result 2

The truth table satisfies .

Finite state machine and Encoders PROBLEM 1:

Objective : To detect a 1110 pattern and output a one (1) with the help of a State transition graph and a verilog module

for a Moore type FSM .

Solution ,

Design Specification :

Inputs : - clk : Clock ; -rst: Rest ; - x : the binary number of the pattern

Outputs: - state : The state it is in during detection of the pattern ; -y : Output

Functional Behavior: To detect the pattern 1110 and give an output of one (1).

Fig 4.1 : Moore FSM

Design Structure :

Inputs :

Clk : clock

Rst : reset set to zero

X : binary digit

Outputs:

State : state of the system during detection. It’s a three bit . The states are mentioned as S0 to S7.

Y: Output of the system ( 0 or 1)

Functional behavior:

To detect the pattern of 1110 .

The different cases are used .

Cases are set according to the Register transfer language ( RTL )

State transition graph:

Fig 4.2 : 1110 Moore STG

ASM :

Fig 4.3 : ASM for 1110 moore fsm

Truth Table :

A B C INPUT A B C OUTPUT

0 0 0 0 0 0 0 0

0 0 0 1 0 0 1 0

0 0 1 0 0 0 0 0

0 0 1 1 0 1 0 0

0 1 0 0 0 0 0 0

0 1 0 1 0 1 1 0

0 1 1 0 1 0 0 0

0 1 1 1 0 1 1 0

1 0 0 0 0 0 0 1

1 0 0 1 0 0 1 1

1 0 1 0 0 0 0 0

1 0 1 1 0 0 0 0

1 1 0 0 0 0 0 0

1 1 0 1 0 0 0 0

1 1 1 0 0 0 0 0

1 1 1 1 0 0 0 0

Table 4.1 : 1110 moore fsm truth table

Next state Present state

Register Transfer Language :

State Output Next state

0 Y 0 (x,!x) /(1/0)

1 Y 0 (x,!x) /(2,0)

2 Y 0 (x,!x) /(3,0)

3 Y 0 (x,!x) /(3,4)

4 Y 1 (x,!x) /(1,0)

5 Y 0 (x,!x) /(0,0)

6 Y 0 (x,!x) /(0,0)

7 Y 0 (x,!x) /(0,0)

Table 4.2 : 1110 moore fsm rtl

Design entry :

Code :

Fig 4.4 : 1110 moore fsm Verilog code

Compilation report:

Fig 4.5 :1110 moore fsm compilation report

Simulation report:

Fig 4.6 : 1110 moore fsm simulation report

Design verification :

Test plan :

Simulation result:

0101

Fig 4.7 : Test 0101 on moore FSM

1110 detected, gives output as 1

1110 not detected gives output 0

Fig 4.8 : Test result of 0111 on moore FSM

PROBLEM 2 :

Objective: To detect a 00011 pattern and output a (1) with the help of a State transition graph and Verilog module for a

Mealy type FSM.


Inputs : - clk : Clock ; -rst: Rest ; - x : the binary number of the pattern

Outputs: - state : The state it is in during detection of the pattern ; -y : Output

Functional Behavior: To detect the pattern 00011 and give an output of one (1).

Fig 4.9: Mealy fsm

Design Structure :

Inputs :

Clk : clock

Rst : reset set to zero

X : binary digit

Outputs:

State : state of the system during detection. It’s a three bit . The states are mentioned as S0 to S7.

Y: Output of the system ( 0 or 1)


To detect the pattern of 00011 .

The different cases are used .

Cases are set according to the Register transfer language ( RTL )

STG :

1110 not detected gives output 0 1110 detected gives output 1

Fig 4.10 : 00011 Mealy fsm STG

ASM :

Fig 4.11 : 00011 Mealy fsm ASM

Truth table:

A B C INPUT A B C OUTPUT

0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0

0 0 1 0 0 1 0 0

0 0 1 1 0 0 0 0

0 1 0 0 0 1 1 0

0 1 0 1 0 0 0 0

0 1 1 0 0 1 1 0

0 1 1 1 1 0 0 0

1 0 0 0 0 0 1 1

Present state Next state

1 0 0 1 0 0 0 1

1 0 1 0 0 0 0 0

1 0 1 1 0 0 0 0

1 1 0 0 0 0 0 0

1 1 0 1 0 0 0 0

1 1 1 0 0 0 0 0

1 1 1 1 0 0 0 0

Table 4.3: 00011 Mealy fsm truth table

RTL :

Table 4.4 : 00011 Mealy fsm RTL

State Output Next state

0 Y 0 (x,!x) /(1/0)

1 Y 0 (x,!x) /(2,0)

2 Y 0 (x,!x) /(3,0)

3 Y 0 (x,!x) /(3,4)

4 Y 1 (x,!x) /(1,0)

5 Y 0 (x,!x) /(0,0)

6 Y 0 (x,!x) /(0,0)

7 Y 0 (x,!x) /(0,0)

Design entry :

Code :

Fig 4.12 : 00011 mealy fsm Verilog code

Compilation report:

Fig 4.13 : 00011 mealy FSM compilation report

Simulation report:

Fig 4.14 : 00011 Mealy simulation report O0011 is detected output is high


Test plan :

The design is tested for different patterns by changing the values assigned to x.

The first figure under simulation result shows the pattern 00100. It satisfies its RTL .

The second figure resembles the pattern 00001. Its satisfies its RTL .

Simulation result:

Fig 4.15 : mealy type test 00100

Fig 4.16: mealy type test 00001

Problem 3 :

Objective : To design a 3:5 bit encoder.


Inputs : - a : 3 bit binary digit

Outputs : - valid ; - Y: 5 bit binary digit

Functional Behavior : 3 bit to 5 bit encoder where output = (input*3)-2

Fig 4.17 : 3bit to 5 bit

Design Structure :

Inputs : A 3 bit binary input –a

Outputs:

O0011 is not detected output is low

O0011 is not detected output is low

A 5 bit binary output : Y

A valid


3bit input to 5 bit output encoder.

Output value=(input*3)-2

The cases in the program are written basing on the output obtained from the truth table considering

output value= (input*3)-2

Truth table:

INPUTS OUTPUTS Output

value

Table 4.5 : 3bit to 5 bit encoder truth table

Design entry :

Code :

Fig 4.18 : 3 bit to 5 bit encoder Verilog code

A0 A1 A2 Y0 Y1 Y2 Y3 Y4

1 0 0 1 0 0 0 0 1 1

2 0 1 0 0 0 1 0 0 4

3 0 1 1 0 0 1 1 1 7

4 1 0 0 0 1 0 1 0 10

5 1 0 1 0 1 1 0 1 13

6 1 1 0 1 0 0 0 0 16

7 1 1 1 1 0 0 1 1 19

Compilation report:

Fig 4.19 : 3bit to 5 bit compilation report


Test plan :

The a has input values (3 bit ) as 1,2,3,4,5,6,7. Corresponding output values are cross-checked with the truth

table given in table 4.5 and output is 5 bit value.

Simulation result:

4.20 : 3bit to 5bit encoder

Problem 4 :

Objective : To design a 3:8 bit encoder.


Inputs : - a : 3 bit binary digit

Outputs : - valid ; - Y: 8 bit binary digit

Functional Behavior : 3 bit to 8 bit encoder

Fig 4.21: 3bit to 8 bit encoder

For 3 , output = (3*3)-2= 4 For 7 , output = (7*3)-2= 19=10011

Design Structure :


Outputs:


A valid

Functional behavior: 3 bit to 8 bit encoder for the following truth table.

Truth table:

INPUTS OUTPUTS

Table 4.6 : 3bit

t 8 bit

encoder

truth table

Design entry :

Code :

Fig 4.22: 3bit to 8 bit encoder Verilog code

A0 A1 A2 Y0 Y1 Y3 Y4 Y5 Y6 Y7 Y8

0 0 0 0 0 0 0 0 0 0 0 0

1 0 0 1 0 0 0 1 0 0 0 1

2 0 1 0 0 0 0 1 0 0 1 0

3 0 1 1 0 0 1 0 0 0 1 0

4 1 0 0 0 0 1 0 0 1 0 0

5 1 0 1 0 1 0 0 0 1 0 0

6 1 1 0 0 1 0 0 1 0 0 0

7 1 1 1 1 0 0 0 1 0 0 0

Compilation report:

Fig 4.23: 3bit to 8 bit encoder compilation report


Test plan :

The input values of a (3 bits) are taken as 0,1,2,3,4,5,6,7. Their respective output values obtained from the

simulation are made to match with the table 4.6.

Simulation result:

Fig 4.24 : 3bit to 8 bit encoder simulation result

Problem 5:

Objective : To design a 8:1 bit decoder.


Inputs : -a: 8 bit input

Outputs: Y- 1 bit output

Functional Behavior : 8 bit input to 1 bit binary output decoder by setting output high if two adjacent bits in

the input are 1.

Decoder :

From truth table 4.6 input of 1

gives output of 00010001 From truth table 4.6 input of 7

gives output of 10001000

Fig 4.25 : 8 bit to 1 bit decoder

Design Structure :


Outputs:



8 bit to 1 bit decoder.

Set output high if two adjacent bits in the input are 1

Design entry :

Code :

Fig 4.26 : 8bit to 1 bit Verilog code

Compilation report:

Fig 4.27: 8bit to 1 bit compilation report


Test plan :

The input a : 8 bit is set according to the table below. The outputs are very verified with table look

up.

INPUT OUTPUT

01010010 0

01110101 1

01100110 1

10010101 0

Table 4.7: Test table for 8 bit to 1 bit decoder

Simulation result:

Fig 4.28 : 8 bit to 1 bit simulation result

a= 01010010 There are no adjacent

bits with 1. So output is 0

a= 01100110 There are adjacent

bits with 1. So output is high.

ALU

Objective : To develop and demonstrate good design discipline and techniques in the design of combinational logic

circuits using Verilog HDL . The ultimate goal in this report is to develop a Verilog HDL which supports 12-bit, two’s

complement Arithmetic Logic Unit(ALU) and which would also satisfy certain functional behavior as stated further in this

report.

Design Specifications :

Inputs : 12 bits A, 12 bits B and a ‘sel’ of 4 bits as selection operator

Outputs : Result of the operation- ‘result’ ; AgtB , AltB , AeqB – 1 bit

Functional behavior : According to the table 5.1

Timing: Maximum propagation delay for any function shall be less than 25 ns.

Design Structure :

Inputs :

A[11:0] – 12 bit, as signed decimal value

B[11:0] – 12 bit, as signed decimal value

Sel[3:0] – 4 bit selection , specifies the output to perform , Given From 0-F.

Outputs :

Result[11:0]- 12 bit (hexadecimal )result according to the selection- sel . Table look up

Agtb – 1 bit output if A value is greater than B, else output is ‘0’

Altb – 1 bit output if A is less than B, else output is ‘0’

Aeqb – 1bit output if A is equal to B , else output is ‘0’

Fig 5.1 : ALU Block diagram


The functional behavior of the ALU is as per the truth table given below in table 5.1

Table 5.1 : The functional behavior of the ALU .

als : Arithmetic left shift : shift left and fill zeros from right.

ars : Arithmetic right shift : shift right and fill zeros from left.

cls : circular shift left : All bits shits to the left by one place and the MSB moves to the LSB.

Timing requirements: Maximum propagation delay for any function shall be less than 25 ns.

Design Entry :

Verilog code:


Flowchart :

Structure Write up :

The inputs are taken as per the tables below. The cases are selected as 0 to F to perform specific tasks as per the

table in 5.1. The flow is given as in the flowchart. Respective to the “sel” , the operation is performed.

The a and b values are considered as signed decimals. They are also tested for greater, lesser and equal to.


Test Plan : The above code is tested for 4 tests . The case truth table is given below. The values of A and B are changed

such that the desired output is obtained by specifying the desired action to be performed by specifying the ‘sel’ input

value.

Test 1:

A(signed

decimal)

B(signed

decimal)

AGRTB(binary) ALTB(binary) AEQB(binary)

5 -4 1 0 0

-8 2 0 1 0

-4 -4 0 0 1

10 10 0 0 1

22 11 1 0 0

11 99 0 1 0

Table 5.2 : truth table to check if A>B, A<B ,A==B

Fig 5.2: Simulation report according to table 5.2

Propagation delay : 8 ns

Test 2:

A(Signed decimal) B(signed decimal) Result

Sel=0 20 -30 -20

Sel=2 -11 22 -11

Sel=3 -11 22 -11

Sel=4 20 10 30

Sel=5 20 30 -10

Sel=9 5 4 27

Sel=A 20 29 48

Sel=F 5 25 48

Table 5.3 : Truth table for the Sel bits – 0,2,3,4,5,9,A,F

A (=5 )> B (= -4)

A (=-4 )= B (= -4)

A (11 )< B (99)

glitch

Fig 5.3 : Simulation report according to truth table 5.3

Propagation delay : 10 ns

Test 3 :

A(Signed

decimal)

B(signed

decimal)

Result

Sel =1 0 0 1

1 0 0

Sel=3 1 0 1

Sel-6 1 1 1

0 0 0

Sel=7 1 1 1

1 0 0

Sel=8 0 1 1

1 1 0

Sel=B 1 1 0

Table 5.4: Truth table for the logical operations such as sel = 1,3,6,7,8,B

For sel= 2=( -(a+b) )= -11 For sel= F , value remain

unchanged from prev selection.

For sel= A = result =

11111111111= 48

Fig 5.4: Simulation report according to table 5.4

Propagation delay < 25 ns

Test 4:

A 1 2 3 4 5 6 7

Sel- C 2 4 6 8 10 12 14

Sel-D 0 1 2 3 4 5 6

Table 5.5: Truth table for the shift operations , sel= C

Fig 5.6: Left arithmetic shift using table 5.5

Propagation delay < 25 ns

A=1, b=1, !(a&b) =0 , sel =B A=1, b=1, A|B =1 , sel =6

LEFT SHIFT, 0000 0000 0001

shifts to 0000 0000 0010 LEFT SHIFT, 0000 00000100shifts

to 0000 0000 1000

Fig 5.7: Right arithmetic shift using table 5.5

Propagation delay <25 ns

Test 5:

A 1 2 3 4 5 6 7

Sel- C 2 3 4 5 6 7 0

Table 5.6 : Circular left shift truth table , sel=E

Fig 5.8 : Circular left arithmetic shift using table 5.6

Propagation delay <25 ns

RESULT :

The Verilog code has been designed to obtained the required operations for an ALU according to table 5.1. The

simulation reports are attached as fig 5.2-8. All are maintained with a maximum propagation delay of less than 25 ns.

LEFT SHIFT, 0000 0000 0010

shifts to 0000 0000 0001 LEFT SHIFT, 0000 0000 1000

shifts to 0000 0000 0100

LEFT SHIFT, 1110 0000

0000shifts to 1100 0000 0001

Shift Register

Objective : To design a 8-bit barrel shifter that shifts the amount specified in the input for each block in one clock cycle.

Also to develop its control unit which would instantiate the shifter along with some other considerations.


Inputs :

Data in – 8 bits

Clear 1 bit – high (1) when register is cleared

Load 1 bit – high (1) when data is to be loaded into the register

Clock 1 bit – continuous square wave with 40nS period

Amount 3 bits – the number of shifts to be taken

Shift type 2 bits – the type of shift to be made

0 – no shift

1 – left shift circular

2 – right shift logical

3 – left shift logical

Outputs :

Data out – 8 bits


Load data in parallel and then shift the number of positions specified by Amount in the direction and

manner specified by Shift Type

Stop shifting the data even if the clock continues.

Data, shift type, and amount will only be present while the load signal is present

Load will be high for one clock cycle

Complete the shift with one clock rising edge

Design Structure :

Inputs :

Datain – 8 bits data input at every 100ns.

AMT – 3 bits , specifying the amount the bits are to be shifted.

Amount – 3 bit register which saves the AMT value

SC- 2 bit , specifying the type of shifting to be performed.

Shifting_type- 2 bit register, stores the value of SC.

Clock – Clock is given at every 20 ns. ( high at every 20 ns )

Load – load signal is given for a clock period.

Clear- clear is given at the beginning to clear the registers.

Outputs :

R[ 7:0] – 8 bits data out


Clear data in register

Load data in register

Load data in parallel and then shift the number of positions specified by Amount in the direction and

manner specified by Shift Type

Stop shifting the data even if the clock continues. Shifts are sequential.

Data, shift type, and amount will only be present while the load signal is present

Load will be high for one clock cycle

Complete the shift with one clock rising edge

Shifts are sequential and complete their shift in one clock

The control inputs are srl, sll, and shc along with the number of bits to shift.

Fig 6.1 : design structure of the 8 bit barrel shifter , shifting in one clock period

Design Entry :

Verilog code :

Fig 6.2 : Verilog code for 8-bit barrel shifter

Fig 6.3: Control unit for 8-bit barrel shifter

Compilation report:

Fig 6.4: Compilation report ,left : Shift control , right: barrel shift register

Flowchart of control unit:

Fig 6.5: Flowchart


Test Plan :

The different input values are given to datain , shifting type is specified at SC, shifting amount is specified at

AMT. The data in is maintained at 100ns. The load is given at the rising edge of the clock. The clock goes high

for every 20ns.

Test 1: No shifting and left logical shift

Fig 6 .6: No shifting and left logical shift 8-bit barrel shifter

Test 2 : Left shift circular and right logical shift

Fig 6.6: Left circular and right logical shift shift 8-bit barrel shifter

Result :

Hence, the 8 bit barrel shift register has been designed with a control unit which would instantiate it and

complete the shifting process in one clock cycle. The Test simulation results are mentioned. The only

disadvantage in the barrel shift register of fig 6.2 encountered is that for AMT = 7 , the shift register sometimes

works and sometimes doesn’t. It should probably be the error of the software. Otherwise, the shifting process is

successfully achieved for the desired amount of bits and for the desired shifting type and is completed in one clock

cycle. The control unit stops the shifting process when the desired shift amount is reached.

D3 is loaded , no shift , so D3

stays Load high but negative clock, so

value D6 is loaded but noshifting.

D6 is loaded , shift type is sll with AMT =

4 . Ans = 10110000 = B0

Negative clock, one clock period is

complete, shift is complete,

therefore shift stops.

E6 is loaded , shift type is SRL with AMT =

3 . Ans = 00011100 = 1C E3 is loaded , shift type is SLC with AMT =

2 . Ans =10001111= 8F

I Clock Period I Clock Period

I Clock Period I Clock Period

STACK

Objective : To design a stack controller for a stack memory system this in turn uses the memory wizard of Altera to

generate the required memory. Also, to observe its performance level.


Inputs :

8 bit data input

1 bit push data

1 bit pop data

Clock

Output:

8 bit data output according to the push/ pop

1 bit overflow status


Control unit with two commands – push and pop

Push should load the data immediately on top of the stack and the other data moves down one location.

Pop should remove data from the top of the stack , and moves the data up by one position( if required).

A structure which supports the modular expansion.

Memory wizard has to be used to generate the required memory.

Design Structure:

Inputs :

8 bit data input

1 bit push data

1 bit pop data

Clock

Output:

8 bit data output according to the push/ pop

1 bit overflow status


Control unit with two commands – push and pop

Push should load the data immediately on top of the stack and the other data moves down one location.

Pop should remove data from the top of the stack , and moves the data up by one position( if required).

A structure which supports the modular expansion.

Memory wizard has to be used to generate the required memory.

Fig 7.1 : LIFO ( Last in first out ) STACK

Design Entry :

Verilog code :

Fig 7.2 : Verilog code


Fig 7.3 L Compilation report

RTL :

Stack Block diagram :

Fig 7. 5: Stack operation with memory

Push and pop operation :

Push Operation :

Fig 7. 6: push operation

POP operation :

Fig 7.7 : Pop operation

Design Verification :

Test Plan :

The first test is done to push 01 and 02 and pop it out in order, given in fig 7.8.

The second test is done to push 02, 03 and pop them all out, given in fig 7.9.

Its observed that initially the 00 is stored in the memory , because memory is initially stored with values 00 , so it tends

to take the default value first.

Simulation results :

Fig 7.8 : test 1

01 and 02 push in the stack 02 and 01 pop out of the stack

iFig 7.9: Test 2

Result :

Performance of the system :

Total CPU time 3 secs

Total no. of pins 5%

Failed paths 0

Clock period 238 MHz

Actual time 10.646 ns

Total logic units used Less than 1%

From the above table , its seen that the size this design uses is very less as the logic units totally used is less than

1%. With this it also provides a considerable fast process time of approximately 10 ns.

Overall Result :

Hence using less space and having a considerable good speed, the stack operation is almost accomplished.

A5, A4, A3 pop out of the stack in three pop

cycles

ALU TESTER

Objective : To design a system to test the ALU designed in the assignment 5 of this course. The testing is to be done using

the DE2 board. Such a test must hold multiple memories to hold test data and the output should be displayed on the 7

segment displayed .


Inputs :

A test memory – 12 bits wide contains data for the A input to the ALU

B test memory- 12 bits wide for the B input to the ALU

Function test memory- 4 bits wide contains the function to be executed

Results test memory- 15 bits wide , these are the expected results to be compared to the ALU results.

Output:

The 7 segment display for mux output, results, function and test number on the DE2 board.


Mux : This is a 2 to 1 multiplexer that selects which 12 bits of data to display

ALU used here is from the assignment 5.

Comparator : to compare the expected results to the ALU generated results, lights up the LEDS if a

difference between expected and generated results are observed.

HEX0,1,2 : MUX OUTPUT DISPLAY

HEX3,4,5 : RESULTS OF THE ALU

HEX 6: FUNCTION to be executed.

HEX7 : Test number

Design Structure:

Inputs :

Allmemories are 8 words of length . Memories are created for a, b, function, expected results.

Clock of 50 Mhz

A push button to change the test data

A switch sw0 is used to give the mux selections .

Mif files of all memories are linked in the main_ test program.

A test memory – 12 bits wide contains data for the A input to the ALU

B test memory- 12 bits wide for the B input to the ALU

Function test memory- 4 bits wide contains the function to be executed

Results test memory- 15 bits wide , these are the expected results to be compared to the ALU results.

Output:

The 7 segment display for mux output, results, function and test number on the DE2 board.

HEX0,1,2 : MUX OUTPUT DISPLAY

HEX3,4,5 : RESULTS OF THE ALU

HEX 6: FUNCTION to be executed.

HEX7 : Test number


Mux : This is a 2 to 1 multiplexer that selects which 12 bits of data to display

ALU used here is from the assignment 5.

Comparator : to compare the expected results to the ALU generated results, lights up the LEDS if a

difference between expected and generated results are observed.

The ALU follows a set of cases defined in assignment 5 .

A debounce program is used to count the number of pushes of the push button in a single clock and give

a single pulse.

The address counter code is used to increment the address locations for each test depending upon the

push button.

Fig 8.1 : Tester program overview

Design Entry :

Verilog code :

Fig 8.2: Main tester program to test the alu

Fig 8.3 : Debounce code

Fig 8.4 : address counter code

Fig 8.5 : Mux code

Fig 8.6 : Comparator code

Fig 8.7 : ALU from assignment 5

Fig 8.8 : Hex- to –7 segment display code


Fig 8.9 : ALU tester compilation report

Top level block diagram :

Fig 8.10: Top level block diagram

7 segment display block diagram :

Fig 8.11: 7-segment display block diagram

DE2 diagram :

Fig 8.12 : DE2 board

Design Verification :

Test Plan :

Fig 8.13 : the verification of the design is done using the values given in class

Simulation results :

Fig 8.14 : Simulation results from the above test data

Data_mux1, mux2, mux3 represents

the value in memory a = 064

Data_results1, 2, 3 = 001 represents

the values in table above

Data_results1, 2, 3 = 02d represents

the values in table above

Result :

Overall Result : The ALU test designed has been designed and is successfully tested on the ALU of the assignment 5.

From the reports available in the Altera Quartus it takes 10.8 ns for the process. The results are successfully seen on the

7 segment display of the DE2 Board. The debounce program used here , partially worked since it only took 5 counts per

clocks. The output was partially right using the debounce code. This code with the debounce code included needs more

future work.

logic design in verilog reports

Documents

b carry

abc abc abc abc f c

adder circuit

adder truth table

fa0full adder

function f

output f

b cin sum cout