Differential Amplifier

The Differential Amplifier has become a very useful circuit because of its compatibility with integrated circuit technology, also its ability to amplify differential signal. Its offering many useful properties, Differential operation has become the dominate choice in today’s high performance analog and mixed signal circuit.

1. Single-Ended and Differential Operation

A single-ended signal is defined as one that is measured with respect to a fixed potential usually the ground. On the other hand a Differential Amplifier is defined as one that is measured between two nodes that have equal and opposite signal excursion around a fixed potential. Note that the two nodes must also exhibit equal impedance to that potential. Figure shows two types of signal conceptually. The center potential in differential

signaling is called the “common mode” (CM) level.

figure:

An important advantage of differential operation over single ended signaling is higher immunity to environmental noise. Consider the example shown in figure, where to adjacent lines in a circuit carry a small sensitive signal and a large clock waveform. Due to capacitive couplings between the lines, transitions on line L2 corrupt the signal on line L1. Now suppose as shown in figure, the sensitive signal is distributed as two equal and opposite phases.

If the clock line is placed midway between the two, the transitions disturb the differential phase by equal amounts, leaving the difference intact. The common mode of the two phase is distributed but the differential output is not corrupted, we say this arrangements reject mode noise.

another example of common mode rejection occurs with noisy supply voltage. in figure, if V DD varies by ∆V , then V outchanges by approximately the same amount, that is the output is quite susceptible to noise on V DD affects V X and V Y but not V X−V Y=V out. Thus, the circuit of figure is much more robust to supply noise.

Another important property of differential signaling is the increase in maximum achievable voltage swings. For example, in the circuit of figure the maximum output swing at X or Y is equal toV DD−(V GS−V TH ), whereas for V X−V Y the peak to peak swing is equal to2(V ¿¿DD−(V GS−V TH ))¿.

2. Basic Differential Pair

A basic differential pair consists of two identical single ended signal paths to process two phase as shown in figure. Such a circuit indeed offers some of the advantage of the differential signaling high rejection of supply noise, higher output swings, etc. But what happens ifV ¿1and V ¿2experience a large common mode disturbance or simply do not have well-defined common dc level? As the input CM level,V inCM, changes, so do the bias current of M1 and M2, thus varying both the trans-conductance of the devices and the output common mode level the variation of the trans-conductance in turn leads to a change in the small signal gain while the departure of the output common mode level from its ideal value lowers the maximum allowable output swing. For example if the input CM level excessively low, the minimum value of V ¿1and V ¿2 may in fact off M1 and M2, leading to severe clipping at the output as shown in figure. Hence it is important that the bias current of the devices have minimal dependent on the input CM level.

A modification that can resolve the above issue is shown in figure. The differential pair employs a current source ISS to makeID1+ ID 2 independent of V inCM. Hence, ifV ¿1 ¿V ¿2, the bias current of each transistor equal I SS /2and the output common mode level is V DD−RD I SS /2.

Qualitative analysis: In figure, let us assume thatV ¿1−V ¿2, varies from −∞to∞. If V ¿1 is much more negative thanV ¿2, M 1is off, M 2 is on andID2=I SS. Hence V out 1=V DD andV out 2=V DD−RD I SS. As V ¿1 is brought closer toV ¿2, M 1 gradually turns on, driving a friction of I SSfrom RD1and hence loweringV out 1. SinceID1+ ID 2=I SS, the drain current ofM 2 decreases and V out 2 rises.

As shown in figure forV ¿1=V ¿2, we haveV ¿1=V ¿2=V DD−RD I SS /2 . As, V ¿1 becomes more positive thanV ¿2, M 1 carries a greater current than does M 2 and V out 1drops belowV out 2. For sufficiently largeV ¿1−V ¿2, M 1 “hogs” all ofI SS, turningM 2 off. As a result V out 1=V DD−RD I SSand V out 2=V DD.figure also plots V out 1−V out 2 versusV ¿1−V ¿2.

This analysis reveals two important attributes of the differential pair. First, the maximum and minimum levels at the output are well defined i.e.

V DD and V DD−RD I SS respectively and independent of the input CM level. Second, the small signal gain (the slope of V out 1−V out 2 versusV ¿1−V ¿2) is

maximum forV ¿1=V ¿2 gradually falling to zero as |V ¿ 1−V ¿2| increases.

Quantitative analysis:

For the differential pair in figure we have V out 1=V DD−RD 1 ID1andV out 2=V DD−RD 2 ID2 i.e., V out 1−V out 2=RD 2 ID 2−RD1 ID 1=RD ( I D2−ID 1) if RD1=RD2=RD. Hence we simply calculate ID1and ID2in terms of V ¿1 and V ¿2 assuming the circuit is symmetric,M 1and M 2 are saturated and λ=0. Since the voltage at node P is equal to V ¿1−V GS1 and V ¿2−V GS2,

V ¿1−V ¿2=V GS1−¿ V GS2(i)

For a square law device we have

(V GS−V TH )2=ID

12μnCox

WL

(ii)

and therefore , V GS=√ ID12μnCox

WL

+V TH (iii)

V ¿1−V ¿2=√ ID112μnCox

WL

−√ I D212μnCox

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(iv)

squaring both sides and recognizing ID1+ ID 2=I SS, we get

(V ¿ 1−V ¿2 )2= 2

μnCoxWL

( I SS−2√I D1 ID 2)

12μnCox

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(V ¿1−V ¿2 )2−I SS=−2√ ID1 I D2(vi)

z Differential pair

3. Common-Mode Response

4. Differential Pair with MOS Loads

5. Gilbert Cell.

6. References