Design of Approximate Subtractors and Dividers for ErrorTolerant Image Processing Applications

Anusha Gorantla1 & P. Deepa2

Received: 28 March 2019 /Accepted: 1 October 2019# Springer Science+Business Media, LLC, part of Springer Nature 2019

AbstractApproximate computing is a promising technique for energy-efficient Very Large Scale Integration (VLSI) systemdesign and best suited for error resilient applications, such as signal processing and multimedia. Approximate computingreduces accuracy, but still provides significant and faster results with low power consumption. It is attractive forarithmetic circuits. Four approximate subtractors are proposed based on the approximate computing at logic level usingKarnaugh map (K-map) simplification. This paper deals with the design approach of various approximate subtractorsand dividers for image processing to tolerate the minimal loss of quality. The proposed designs offer better error tolerantcapabilities for image processing

Keywords Approximate Computing;. Low Power . Approximate Subtractor . Image Processing

1 Introduction

Several computer arithmetic applications are implementedusing digital logic circuits, thus operating with a highdegree of accuracy. Humans have less perceptual abilitiesin identifying imprecision during an image or video pro-cessing [1]. Hence, algorithms and precise models areinefficient to use in these applications. This allows inac-curate computation by digital logic circuits or systems bydecreasing the logic complexity with an increase in per-formance [2]. Approximate computing allows optimizinglogic complexity and performance for the sake of accura-cy. Thus, an error in computation is tolerated as long as itis small enough to maintain an acceptable operation of thesystem [3].

The approximations are applicable at different levels ofabstraction corresponding to algorithm, architecture, logic,gate, and transistor levels [1, 4]. Approximate computing is

predominantly suitable for arithmetic circuits such as adders,subtractors, multipliers, and dividers.

Basically, computers handle a lot of numbers based onthe basic arithmetic operations of addition, subtraction,multiplication, and division. Compared to addition andmultiplication, subtraction and division are least signifi-cantly used operation. However, high-performance com-puting will experience performance degradation if sub-traction and division are ignored [5]. Maximum logic op-timization and accuracy is hard to obtained using approx-imate subtractors [6]. The array dividers based on approx-imate subtractors are hardware efficient with a trade-off inan area, delay, and power due to look up table utilization[7]. In discrete cosine transform (DCT), the subtraction isperformed using the inexact adders (INXA), causes moredelay and logic inaccuracy in implementation [8]. Toovercome these difficulties, approximate subtractors havebeen proposed in this paper. The main goal is to designapproximate subtractors (APSCs) which targets minimalerror, low power, and low delay than existing approximatesubtractors (AXSCs) [6].

The paper has organized as follows. AXSCs and ProposedAPSCs have discussed in Section II. Section III describes theapproximate restoring dividers. The Synthesized results of theapproximate subtractors, approximate dividers, and error met-rics of approximate subtractors, approximate dividers and im-age processing application have given in Section IV. Finally,Section V concludes the paper.

Responsible Editor: S. T. Chakradhar

* Anusha Gorantlaanushagorantla3@gmail.com

1 Department of Electronics and Communication Engineering,Government College of Technology, Coimbatore, India

2 Department of Electronics and Communication Engineering,Government College of Technology, Coimbatore, India

https://doi.org/10.1007/s10836-019-05837-5Journal of Electronic Testing (2019) 35:901–907

/Published online: 26 2019October

2 Exact Subtractor (EXSC) and ApproximateSubtractors (APSCS)

Recently the approximate subtractors have been developed bythe researchers and previous work in this area is fewer. Thecircuit implementations of an EXSC and three types ofAXSCs are named as AXSC1, AXSC2, and AXSC3. Theseapproximations have been developed by introducing the ap-proximations at logic level and simplifying the logic using K-Map. AXSC1 and AXSC3 have two errors and AXSC2 havefour errors [6]. The design approach of AXSCs is specified insubsection 2.1. Further to reduce the logic errors and improvethe performance, various APSCs have been proposed. Thedesign approach of various APSCs named APSC4, APSC5,APSC6 and APSC7 have described in sub section 2.2.

2.1 Existing Approximate Subtractors (AXSC1-AXSC3)

In this section, AXSCs namely AXSC1, AXSC2, and AXSC3were discussed basically. Two approaches have been involvedin AXSCs, one is approximation in D alone and exact in Bout.Second is an approximation in Bout and exact in D. AXSC1 andAXSC3 designs involve approximation in D. AXSC2 designinvolves approximation in Bout [6]. From [6], it is observed thatAXSC1 and AXSC3 produces two errors due to approximationin D. AXSC2 produces four errors because of approximation inBout. AXSC1 and AXSC3 have the same probability of error,but depends on the different combination of inputs.

2.2 Proposed APSCs (APSC4-APSC7)

In this section, four different APSCs namely APSC4, APSC5,APSC6, and APSC7 have been proposed.

Further logic optimization and minimal errors are possiblein AXSCs. Therefore, APSCs have been designed by K-maplogic simplification. In designing the proposed APSCs, Dalone has been approximated. Thus, proposed APSCs pro-duces less errors than AXSCs. Table 1 shows the D and Bout

for proposed APSCs.

2.2.1 Approximate Subtractor4 (APSC4)

The APSC4 given in Table 1 shows that difference D =X′Y+YBin + X′Bin + XY′Bin′ is correct for 7 out of 8 cases, exceptfor the case X = 0, Y = 1 and Bin = 1 and Bout = (X⊕Y)′Bin +X′Y is correct for 8 cases.

2.2.2 Approximate Subtractor5 (APSC5)

From Table 1, APSC5 difference D = XY′ + Y′Bin + X′YBin′ +XBin is correct for 7 out of 8 cases, except the caseX = 1, Y = 0 and Bin = 1 and Bout = (X⊕Y)′Bin + X′Y is cor-rect for 8 cases.

2.2.3 Approximate Subtractor6 (APSC6)

From Table 1, APSC6 difference D =XYBin + X′YBin′ +X′Y′Bin is correct for 7 out of 8 cases, except the case X = 1, Y = 0and Bin = 0 and Bout = (X⊕Y)′Bin +X′Y is correct for 8 cases.

2.2.4 Approximate Subtractor7 (APSC7)

From Table 1, it has been observed that APSC7 shows thatdifference D = XY′ Bin′ +X′Y′Bin + XYBin is correct for 7 outof 8 cases, except the case X = 0, Y = 1 and Bin = 0 andBout = (X⊕Y)′Bin + X′Y is correct for 8 cases.

As shown in Table 1, proposed APSCs have less errorcompared to AXSCs. In the proposed APSCs the approxima-tion is performed only in D not in Bout. But, in section 2.1, theAXSC2 is approximated in Bout. AXSC1 and AXSC3 areapproximated in D.

From section 2.1, it is observed that the number of errorsare high in AXSCs than proposed APSCs with a minimumtrade-off in an area for some cases. The proposed APSCs havethe same probability of error, but depends on the differentcombination of inputs.

3 Dividers

The processes of division includes subtraction, shift, and com-pare operations. The two categories of division methods fo-cussed by researchers are digit recurrent division and divisionby convergence. Restoring division is the simplest of threedigit recurrent division methods. The restoring division is di-vided into performing and non-performing versions.Compared to performing version, the delay in non-performing version is less [9].

Table 1 Truth table for proposed APSCs

Inputs Outputs

EXSC Proposed APSCs

X Y Bin

APSC4 APSC5 APSC6 APSC7

Bout D Bout4 D4 Bout5 D5 Bout6 D6 Bout7 D7

0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 1 1 1 1 1 1 1 1 1 1 1

0 1 0 1 1 1 1 1 1 1 1 1 0×

0 1 1 1 0 1 1× 1 0 1 0 1 0

1 0 0 0 1 0 1 0 1 0 0× 0 1

1 0 1 0 0 0 0 0 1× 0 0 0 0

1 1 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1

Note: × denotes erroneous output

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3.1 Exact Restoring Divider (non-performing)

In unsigned restoring division, the operands dividend (D),divisor (M), the quotient (Q) and the remainder (R) are repre-sented using eq. 1 where R <M.

D ¼ MQþ R ð1Þ

Once D and M enters into the divider, D performs left shiftand stores into a temporary register (Temp) to subtract fromM. These processes will generate the Temporary Partial (TP)remainder. The logic circuit determines whether TP is eitherpositive or negative. If TP is negative, quotient bit is set tozero, TP is used as the partial remainder for next iteration andremaining all procedures are exactly the same as theperforming version of restoring division. This algorithm iscalled ‘non-performing’ version since the addition to restoreTP is not performed.

3.1.1 Array Dividers

Recent researchers have focused on high speed arithmeticoperations based on cellular array circuits, for various arith-metic operations such as multiplication, division, square andsquare-root. The complexity of these arithmetic cells and theircorresponding arrays depends on design requirements [9].

3.1.2 Restoring Array Dividers

The restoring array divider is based on restoring non-performing division algorithm. In 8 to 4 restoring divider,dividend(X), divisor (Y), quotient (Q) is of 8-bits, 4-bits and4-bits respectively. An unsigned exact 8 to 4 restoring non-performing array divider is shown in Fig. 1a. The restoringcell consists of Controlled Subtractor (CS) cell which includesEXSC and multiplexer. P is a control signal used to performsubtraction. Borrow output (Bout) and difference (D) of CScell is computed using eq. 2 and 3. In eq. 4, subtraction be-tween previous partial remainder and divisor is performed ifmode P = 0, else divisor propagates to next stage.

Bout ¼ X0Y þ X 0Bin þ YBin ð2Þ

D ¼ XP þ XY0Bin

0 þ XYBin þ X0YB

0inP

0

þ XY0BinP

0 ð3Þ

D ¼ X⊕Y⊕Bin if P ¼ 0X if P ¼ 1

�ð4Þ

In eq. 4, EXSC is replaced with approximate subtractor todesign an approximate restoring divider. The 8 to 4 unsignedrestoring array dividers based on AXSC1, AXSC2 andAXSC3 are named as AXDr1, AXDr2 and AXDr3 respective-ly. Further, to improve accuracy and performance of approx-imate restoring dividers, proposed APSCs have been appliedat n/2 LSBs in the vertical direction. The approximate 8 to 4unsigned restoring array dividers based on proposed APSCs atLSB are shown in Fig. 1b and named as APDr1, APDr2,APDr3, and APDr4 respectively.

4 Results and Discussion

In this section, the design metrics of exact, existing, and pro-posed designs were evaluated. For analysing the design met-rics such as power, area, and delay of EXSC, AXSCs and

a

bFig. 1 Block Diagram of 8 to 4 Unsigned Restoring Array Divider. aEXDr, (b) Proposed APDrs

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proposed APSCs have been implemented in Verilog HDL andsynthesized in 180 nm, 90 nm and 45 nm technologies usingCadence RTL Compiler. The performance of proposed APDrshave been compared with AXDrs. The AXSCs, AXDrs, pro-posed APSCs, and APDrs are analysed for various error met-rics and applied for background subtraction and removal ofimage processing.

4.1 Approximate Subtractors

The power, delay, area, and the number of errors of EXSC,AXSCs and proposed APSCs are given in Table 2 for 180 nm,90 nm, and 45 nm. In AXSCs and proposed APSCs,

AXSC2, APSC4, and APSC6, APSC7 consumes low pow-er and operates at less delay respectively. The APSC4,APSC5, APSC6, and APSC7 has 76%, 68%, 60%, and 61%low power compared to EXSC.

Among four proposed APSC designs, the APSC4 designachieves significant improvement in power consumption. TheAPSC4, APSC5, APSC6, and APSC7 has 4%, 11%, 15%,and 14% lower delay and respectively than EXSC. From

Table 2, it is observed that APSC4, APSC5 and APSC7 has41%, 19%, and 4% less area as compared to EXSC exceptAPSC6. From inaccuracy point of view, all proposed APSCshave minimal error compared to AXSCs.

4.2 Approximate Restoring Array Dividers

Table 3 lists the power, delay, area, and the number of errors ofan EXDr, AXDrs, and Proposed APDrs. The APDr4, APDr5,APDr6, and APDr7 has 71%, 62%, 63%, and 60% low powercompared to EXDr. Among four proposed APDr designs, theAPDr4 design achieves significant improvement in powerconsumption.

The APDr4, APDr5, APDr6, and APDr7 has 15%, 23%,40%, and 39% lower delay and respectively than EXDr. FromTable 3, it is observed that APDr4, APDr5, APDr6, andAPDr7 has 29%, 27%, 18%, and 23% less area as comparedto EXDr. From inaccuracy point of view, all proposed APDrshave minimal error compared to AXDrs. As accuracy in ap-proximation is the major focus of this paper, proposed APDrsgives better performance than AXDrs.

Table 2 Comparison of approximate subtractors

Subtractor Power (nw) Delay (ps) Area (μm2) Power (nw) Delay (ps) Area (μm2) Power (nw) Delay (ps) Area (μm2) Numberof errors@180 nm @90 nm @45 nm

EXSC [6] 7530 476 90 3475 223 41 1587 106 19 0

AXSCs [6]

AXSC1 2960 508 77 1458 243 35 687 112 16 2

AXSC2 2391 544 50 1174 266 21 579 129 8 4

AXSC3 2858 544 70 1389 266 29 625 129 14 2

Proposed APSCs

APSC4 1835 455 53 891 217 23 436 101 9 1

APSC5 2439 425 73 1189 206 32 572 97 15 1

APSC6 2919 405 90 1437 189 41 691 89 19 1

APSC7 2950 407 86 1446 194 39 714 92 17 1

Table 3 Analysis of AXDrs and Proposed APDrs

Dividers Power (nw) Delay (ps) Area (μm2) Power (nw) Delay (ps) Area (μm2) Power (nw) Delay (ps) Area (μm2) Numberof errors@180 nm @90 nm @45 nm

EXDr [6] 132,518 8410 1254 50,142 4067 612 23,895 1924 289 0

AXDrs [6]

AXDr1 52,139 7613 985 26,076 4305 528 12,087 1976 252 32

AXDr2 44,386 9281 673 23,175 4712 426 10,784 2331 206 64

AXDr3 48,962 9394 748 24,912 4875 449 11,921 2362 219 32

Proposed APDrs

APDr4 38,192 7146 887 18,496 3497 432 9072 1734 204 10

APDr5 49,017 6473 913 23,076 3186 447 11,395 1569 216 10

APDr6 49,591 5072 1031 24,942 2514 496 12,343 1235 236 10

APDr7 53,598 5173 964 26,027 2548 475 12,903 1259 223 10

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4.3 Error Metrics

Several metrics such as Error Distance (ED), Error Rate (ER),Pass Rate (PR), Mean Error Distance (MED), and NormalizedError Distance (NED) [10] have computed to analyse the im-precision of approximate subtractors. Table 4 list the ED, ER,PR, MED and NED of AXSCs, AXDrs, proposed APSCs andAPDrs. The proposed APSCs have the minimal error com-pared to AXSCs [9]. Therefore, the proposed APSCs andAPDrs have significant improvement in ED, PR, ER, MEDand NED.

4.4 Application

In this section, the application of AXSCs, AXDrs, proposedAPSCs and APDrs in image processing is illustrated. A back-ground subtraction approach is considered to analyse imagequality using the AXSCs and proposed APSCs. MATLAB isused to process the grey scale image. The sample images aresize 225 × 225, 250 × 250, 512 × 512, 847 × 847 and 1024 ×1024. Image subtraction has an absolute difference betweenthe two input images using following eq. 5.

f x; yð Þ ¼ j f 1 x; yð Þ− f 2 x; yð Þj ð5Þ

Two input images f1(x,y) and f2(x,y) are subtracted usingthe AXSCs, and proposed APSCs. Figure 2a and b shows thetwo input images for subtraction. Figure 2c to 2j shows thebackground subtraction using EXSC, AXSCs, proposedAPSC4, APSC5, APSC6 and APSC7 in terms of PSNR.The output image of the proposed APSCs are compared withthe output image of EXSC. The APSCs have less probabilityand propagation of error. Therefore, the image quality for theproposed APSCs have high PSNR compared to AXSCs.

Figure 3 shows the unsigned integer division performedbetween X and Y image. Figure 3c to 3j shows the back-ground removal using EXDr, AXDrs and proposed APDrs

Table 4 Comparison the error metrics

Designs ED ER PR MED NED

AXSC1 2 0.25 0.75 0.125 0.02

AXSC2 4 0.5 0.5 0.25 0.03

AXSC3 2 0.25 0.75 0.125 0.02

Proposed APSCs 1 0.125 0.875 0.0625 0.01

AXDr1 20 0.25 0.75 1.284 0.368

AXDr2 40 0.5 0.5 1.326 0.632

AXDr3 20 0.25 0.75 1.284 0.368

Proposed APDrs 10 0.062 0.938 1.08 0.152

a b c d PSNR =30.2 dB

e PSNR=26.3 dB f PSNR =28.1dB g PSNR =35.5 dB h PSNR=34.6 dB

i PSNR =32.4 dB j PSNR =33.8 dB

Fig. 2 Background Subtractionof Image Size 512 × 512 (a) InputImage X (b) Input Image Y (c)EXSC (d) AXSC1 (e) AXSC2 (f)AXSC3 (g) APSC4 (h) APSC5(i) APSC6 (j) APSC7

J Electron Test (2019) 35:901–907 905

a b c d PSNR =22.7 dB

e PSNR =17.1dB f PSNR =20.2dB g PSNR =29.6 dB h PSNR =27.5 dB

i PSNR =26.2 dB j PSNR =24.8 dB

Fig. 3 Background Removal ofImage Size 512 × 512 (a) Inputimage X (b) Input image Y (c)EXDr (d) AXDr1 (e) AXDr2 (f)AXDr3 (g) APDr4 (h) APDr5 (i)APDr6 (j) APDr7

Table 5 PSNR and MSSIM of AXSCs, AXDrs, Proposed APSCs and and APDrs

S.No Input image 1 Input image 2 APSCs PSNR (dB) MSSIM APDrs PSNR (dB) MSSIM

1

225×225

AXSC1 30.3 0.053 AXDr1 13.2 0.014

AXSC2 26.8 0.046 AXDr2 11.4 0.08

AXSC3 32.4 0.057 AXDr3 15.7 0.016

APSC4 37.6 0.076 APDr4 28.3 0.029

APSC5 36.4 0.064 APDr5 24.6 0.023

APSC6 35.8 0.059 APDr6 20.2 0.021

APSC7 34.2 0.072 APDr7 17.8 0.019

2

512×512 512×512

AXSC1 28.4 0.047 AXDr1 14.7 0.012

AXSC2 24.1 0.032 AXDr2 12.1 0.08

AXSC3 30.3 0.049 AXDr3 16.1 0.017

APSC4 35.4 0.074 APDr4 26.2 0.029

APSC5 34.9 0.067 APDr5 22.4 0.024

APSC6 33.8 0.058 APDr6 19.8 0.012

APSC7 34.2 0.065 APDr7 17.5 0.05

3

847×847 847×847

AXSC1 25.6 0.037 AXDr1 17.9 0.012

AXSC2 19.9 0.024 AXDr2 14.5 0.08

AXSC3 28.4 0.043 AXDr3 19.2 0.18

APSC4 36.8 0.074 APDr4 29.6 0.034

APSC5 35.2 0.052 APDr5 26.4 0.029

APSC6 33.6 0.061 APDr6 23.2 0.025

APSC7 32.1 0.059 APDr7 21.5 0.021

4

AXSC1 22.4 0.031 AXDr1 15.6 0.011

AXSC2 18.1 0.026 AXDr2 12.3 0.07

AXSC3 27.8 0.045 AXDr3 16.5 0.09

APSC4 34.5 0.062 APDr4 27.8 0.025

1024×1024 1024×1024 APSC5 33.7 0.056 APDr5 24.6 0.023

APSC6 32.4 0.053 APDr6 21.5 0.018

APSC7 30.6 0.048 APDr7 17.8 0.013

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in terms of PSNR. The proposed APDrs achieves high PSNRdue to the approximation at the difference in proposed APSCsand approximation at LSBs only.

The PSNR and Mean Structural Similarity IndexMeasurement (MSSIM) [11] of the AXSCs and AXDrs, pro-posed APSCs and APDrs for sample two images using back-ground subtraction and removal have been computed and giv-en in Table 5. The PSNR and MSSIM of proposed APSCshave a higher value compared to AXSCs due to less error isinvolved in proposed APSCs as compared to AXSCs. Thisleads to marginal improvement of image quality in terms ofPSNR in background subtraction. The PSNR and MSSIM ofproposed APDrs have higher value Compared to AXDrs, asproposed APDrs involves proposed APSCs at LSBs only.

Background removal is illustrated with AXDrs, and pro-posed APDrs. The background removal is performed based onunsigned integer division and the output is rounded to nextlower integer value. Image background removal is the divisionof two input images using following eq. 6.

g x; yð Þ ¼ f 1 x; yð Þ= f 2 x; yð Þ ð6Þ

5 Conclusion

In this paper, four designs of APSCs and APDrs have beenproposed. Results are reported for existing and proposed de-signs and error metrics have been tabulated. For accuracy, theproposed APSCs and APDrs achieve significant improve-ment. The proposed APSC4 and APDr4 are efficient in termsof power consumption compared to approximate subtractorsand dividers, respectively. An improvement in delay is alsoobtained in the proposed APSCs and APDrs. The proposedAPSCs and APDrs have area overhead due to logic involvedin their design over AXSCs and AXDrs. An image processingapplication has been presented in detail. The proposed designsshow significant improvements in terms of accuracy, power,and latency at a cost of larger area. As an emerging paradigm,approximate computing shows great promise for energy effi-cient and error tolerant systems.

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Publisher’s Note Springer Nature remains neutral with regard tojurisdictional claims in published maps and institutional affiliations.

Anusha Gorantla received Bachelor's Degree in Electronics andCommunication Engineering in 2006 from JNTU Hyderabad, AndhraPradesh, India. She received M.Tech. in VLSI Design in the year 2008.Now she is pursuing Ph.D. at Anna University Chennai, Tamilnadu,India.

P. Deepa received Bachelor's Degree in Electronics and CommunicationEngineering in 2002 from Bharathiyar University, Coimbatore, TamilNadu, India. She received M.E. in VLSI Design in the year 2007 andthe Ph.D. degree in Information andCommunication Engineering in 2013from Anna University, Chennai, Tamil Nadu, India. She is working as anAssistant Professor, Department of Electronics and CommunicationEngineering, Government College of Technology, Coimbatore, TamilNadu, India.

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