Design of High Speed Error Tolerant Adder Using Gate DiffusionInput Technique

S. Geetha1 & P. Amritvalli1

Received: 3 September 2018 /Accepted: 7 May 2019 /Published online: 23 May 2019# Springer Science+Business Media, LLC, part of Springer Nature 2019

AbstractThis paper presents possible designs for high speed error tolerant adder using Gate Diffusion Input (GDI) technique. The 1-bitmodified full adder (MFA) proposed in [1] is implemented using GDI technique (GDI-MFA). The GDI-MFA is extended toimplement a 16-bit high speed error tolerant adder (GDI-HSETA). The performance of various configurations is studied based onmetrics such as delay, area and power dissipation. The circuits have been simulated using pSPICE software. From the results it isobserved that the proposed GDI-MFA has 52% less transistor count and consumes 33% less power compared to conventionaladders. Results of simulation of GDI-HSETA and other adders in pSpice indicate that the proposed adder has 21.6% powerreduction and 13% less transistor count. Also, based on the implementation of GDI-HSETA and existing 16-bit adders on FPGASpartan 6 platform, it is observed that GDI-HSETA achieved power reduction compared to 16-bit adders using conventionaldesign.

Keywords Error tolerant adder . CSLA . GDI . High speed .Modified full adder

1 Introduction

With the explosive growth of hand held devices, there is anurgent need for intensified research efforts in the field of lowpower microelectronics. Power dissipation depends upon theswitching activity, internal capacitances and circuit size. Oneof the commonly employed techniques for power reduction isreducing the supply voltage [2]. Drawback of using low sup-ply voltage includes increased circuit delay and degradation indrivability for cascaded structures. The other options includeclock frequency reduction, switching capacitance reduction,switching activity reduction and circuit size reduction. Severalalgorithmic techniques have been proposed in literature forcircuit size reduction [3]. Proper selection of logic styles canbe considered as one approach to obtain improved perfor-mance. Different logic styles tend to favor the realization ofone performance aspect at the expense of other.

Addition, subtraction, multiplication and multiply and ac-cumulate (MAC) are the building blocks of any signal pro-cessing system. A 1-bit full adder cell is the building block ofall of the above modules. The main parameters involved inoptimization of performance of adder cell are area, delay andpower consumption. Various 1 bit full adder performances areanalyzed in [4]. Several adder designs such as static CMOS,dynamic CMOS, transmission gate and pass transistor logichave been discussed in literature [4–6]. The common prob-lems reported in adders discussed in literature, include low-output swing and high noise particularly during operation withlow supply voltages. Two general approaches of design forimproved performance are circuit level and transistor levelapproach. Circuit level involves finding the longest criticalpath in the ripple adders and minimizing the path to reducedelay. In general for ripple adders, the longest critical path is inthe propagation of carry signal to generate the carry outbit. Transistor level approach includes design of highperformance full adder cell with reduced transistorcount. This approach results in reduced power dissipa-tion and improves the speed of operation. SeveralCMOS static structures have been proposed in literaturefor implementing low power adder cells [6, 7]. GDI meth-odology allows implementation of a wide range of complexlogic functions using only two transistors [7]. The efficiencyof the GDI method for both combinational and sequentiallogic has been demonstrated [8].

Responsible Editor: S. Sindia

* S. Geethageethaciteee@gmail.com

P. Amritvalliamritap46@gmail.com

1 Department of Electrical and Electronics Engineering, Coimbatore,Institute of Technology, Coimbatore, India

Journal of Electronic Testing (2019) 35:383–400https://doi.org/10.1007/s10836-019-05802-2

In conventional digital VLSI design, one usually assumesthat a usable circuit/system should always provide definite andaccurate results. But in fact, such perfect operations are sel-dom needed in our non-digital worldly experiences. Theworld accepts Banalog computation,^ which generates Bgoodenough^ results rather than totally accurate results [9]. Formany digital applications, the data that are processed containerrors. During the process of analog to digital conversion andvice versa, error may occur everywhere. For many DSP basedapplications speed and power are the main parameters andaccuracy is considered secondary [10]. Error tolerant addershelp in reduction of power consumption at the cost of accura-cy. Inexact circuits are smaller, faster and consume less power.Design criteria for full adder are usually multifold. Transistorcount is the primary concern which determines the system

complexity of arithmetic circuits. In a normal adder circuit,the delay is mainly due to the carry propagation chain alongthe critical path, from the LSB toMSB. A major proportion ofthe power consumption of an adder is due to the unwantedsignal component that is caused by the carry propagation.Therefore, if the carry propagation can be removed, a greatimprovement in speed performance and power consumptioncan be achieved.

This paper is an extension of our previous work [1], wherea detailed study of 1-bit modified full adder MFA is presentedand the performance metrics of the same has been demonstrat-ed in detail. The study of MFA in [1] in based on subjectingthe adder to random inputs and evaluating the performance.Transistor level implementation of MFA is not presented in

Fig. 1 Basic GDI cell

Table 1 Truth table of basic GDI cell

N P G Out Function

‘0’ B A AB F1

B ‘1’ A Aþ B F2

‘1’ B A A +B OR

B ‘0’ A AB AND

C B A ABþ AC MUX

‘0’ ‘1’ A A NOT

Fig. 2 Full-swing XOR gate using GDI

Fig. 3 Full swing MUX using GDI

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[1]. This paper focuses on proposing transistor level imple-mentation of possible designs of 1-bit error tolerant MFA ad-der cell using GDI technique, and evaluating performancemetrics such as area, transistor count and power dissipationusing pSPICE. In addition, comparison of performance met-rics with other existing error tolerant adders is presented. Also,16-bit error tolerant GDI-HSETA is proposed and the perfor-mance is studied by implementing the circuit on Spartan 6.

2 Related Work

2.1 Conventional Adder Design

Performance of digital logic circuits can be optimized by prop-er selection of logic style. The logic styles followed for addercells in literature include static CMOS [11], dynamic circuit,transmission gate design, Pass Transistor Logic (PTL) [5] andGDI technique. Hybrid full adder cells have been proposed in[2] which combine static and dynamic (S&D) entities in asingle full adder cell. Another hybrid-full adder cell has been

presented in [12] based on XOR-XNOR circuit. The advan-tage of the proposed design is full-swing output in addition toimproved power delay product (PDP) compared to conven-tional adders. A 16-T hybrid full adder using XOR-XNORgates, pass transistors and transmission gates has been present-ed in [13–15]. The key to the design is the elimination ofinverter from the critical path of the circuit, which results inhigh speed. Authors have presented new XOR function withtransmission gate which has a superior performance comparedto other full adders in [16]. Realization of full adders usingmajority function implementation has been widely studied inliterature [17–19]. Two Full adder designs using majorityNOT gates implementation with 6-T, 12-T in [18] and 8-T[17] has been presented. Based on the simulation results au-thors have observed reduced power consumption and PDPwhen compared to state-of-art full adder cells. Multiplexerbased design of full adders has been presented in [20].Authors have presented a low-power 12 T multiplexer basedfull-adder which has desirable performance compared to con-ventional CMOS, and 10 T adders.

2.1.1 GDI Based Adder Cells

Gate Diffusion Input (GDI) technique for full adder design hasbeen proposed by [7], and has been used in a wide variety ofadders [8]. The GDI approach allows implementation of awide range of complex logic functions using only two transis-tors. Circuits designed using this approach is suitable for fast,low-power applications with reduced number of transistors. In[7], the characteristic of GDI based full adder is comparedwith existing adder structures namely CMOS, PTL and TGtechniques. Several adder circuits based on GDI techniqueshave been presented in [5, 6, 21]. The circuits differ in thelogic expression used to obtain the sum and carry terms. Theauthors have suggested that the basic GDI cell proposed in [7]suffers from threshold voltage problems which results in re-duction of output voltage for cascaded adders. To overcome

Table 3 List of Boolean expressions to implement the designs

Type Sum Carry

Conventional Adder Design 1 Sum ¼ Cin A XOR Bð Þ þ Cin A XNOR Bð Þ ) Cout ¼ A XOR Bð ÞCin þ A XOR B� �

A

Design 2 Sum = A XOR B XOR Cin Cout ¼ Cin A AND Bð Þ þ Cin A OR Bð ÞDesign 3 Sum = A XOR B XOR Cin Cout = A AND B + (A XOR B)Cin

AFA Design 1 Sum = not(Cout) Cout ¼ A XOR Bð ÞCin þ A XOR B� �

A

Design 2 Cout ¼ Cin A AND Bð Þ þ Cin A OR Bð ÞDesign 3 Cout = A AND B + (A XOR B)Cin

MFA Design 1 Sum ¼ Cin A XOR Bð Þ þ Cin A XNOR Bð Þ Cout = A

Design 2 Sum = A XOR B XOR Cin Cout = A

Table 2 List of proposed error tolerant designs

Inputs Accurate output Adder [32] Adder [1]

AFA MFA

A B C S C S C S C

0 0 0 0 0 1 X 0√ 0√ 0√0 0 1 1 0 1√ 0√ 1√ 0√0 1 0 1 0 1√ 0√ 1√ 0√0 1 1 0 1 0√ 1√ 0√ 0 X

1 0 0 1 0 1√ 0√ 1√ 1 X

1 0 1 0 1 0√ 1√ 0√ 1√1 1 0 0 1 0√ 1√ 0√ 1√1 1 1 1 1 0 X 1√ 1√ 1√

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the above problem, three GDI adders with full swing outputhave been presented in [5]. In [6] adders with ultra low-powerdiode (UPLD) have been presented to obtain full-swing output

voltage. Another approach, namely full-swing gate diffusionlogic (FS-GDI) to obtain full swing output is presented in [8].An FS-GDI cell utilizes a swing restoration (SR) transistor to

Table 4 Implementation of AFA and MFA 1-bit adder cell

GDI

AFA

GDI AFA Design 2

GDI AFA Design 3

GDI-

MFA

GDI MFA Design 1 GDI MFA Design 2

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obtain full swing output. The FS-GDI cell is used in 16-bitCarry Look ahead Adder and the performance is comparedwith existing structures such as CMOS and the basicGDI. A variation of basic GDI technique, namely mod-ified GDI is presented in [21]. Five different approachesfor full adders based on modified GDI are presentedand the performance is compared with existing GDItechnique, CMOS and PTL [22].

2.1.2 Approximate Adders

Applications such as speech processing and multimedia,involve human senses such as hearing, sight, smell andtouch may not require accurate adders. Due to percep-tual limitations of human beings, some errors do notmake obvious difference in the interpretation of the re-sults of applications. Approximate adders have been

considered as a potential alternative for error-tolerantapplications to trade off accuracy for gains in othercircuit parameters such as power, area and delay [9].Various approaches have been suggested to realize ap-proximate adders. Truncation of carry propagation chainfor speed improvement has been proposed in [3, 9, 23,24], speculative approach is presented in [24] and seg-mented adders are presented in [25, 26]. In [9], authorshave suggested an Error Tolerant adder (ETA) mecha-nism involves splitting the input operands into twoparts: an accurate part that includes several higher orderbits and the inaccurate part that is made up of the re-maining lower order bits. The addition process startsfrom the middle (joining point of the two parts) towardthe two opposite directions simultaneously. Performanceimprovement in terms of delay and power dissipation isachieved. Two energy efficient low area error tolerantadders (ELAETA-I and ELAETA-II) which could caterthe needs of most signal processing application has beenpresented in [5]. A simple approach of reducing powerwith the use of SQRT CSLA is presented in [27].Conventional CSLA and Binary to Excess 1 Converteris analyzed and redundancy logic has been eliminatedby computing the carry select operation [28]. Carry se-lect adder using single ripple carry adder and add onecircuit is given in [29].

Three different approximation circuits are suggested in [30]and the performance is compared. Ripple carry adder structureis used to implement the approximate adders. The perfor-mance of the approximate adders is studied for image com-pression and video compression applications. Since, four ormore errors are assumed in the approximation circuits,the accuracy of the output is affected. Very few papershave been presented for GDI implementation of errortolerant adders [17]. The adder presented in [31] hasbeen designed using GDI technique to obtain powerreduction. Authors have shown that CMOS based 32-

ACCURATE 8 – BIT CSLA INACCURATE 8 – BIT ADDER

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MFA MFAMFAMFAMFAMFA MFAMFA

FA: Conventional Full Adder MFA: Modified Full Adder

Fig. 5 Detailed block diagram ofGDI-HSETA

B15-B8 A15-A8 B7 – B0 A7 – A0

C8

S15 – S8COUT S7 – S0

ACCURATE PART

8 – BIT CSLA INACCURATE PART

16 BIT GDI-HSETA

Fig. 4 Block diagram of Proposed GDI-HSETA

J Electron Test (2019) 35:383–400 387

Bit ETA requires 1036 transistors, whereas GDI basedtechnique requires only 544 transistors. In [1], highspeed error tolerant carry select adder (HSET-CSLA)has been proposed. The adder is constructed using amodified 1-bit full adder cell (MFA). The 1 bit fulladder cell assumed errors in carry bit to result in sim-plified expression for carry. The efficiency of MFA interms of power dissipation, transistor count and delayhas been demonstrated in [1]. The performance evalua-tion of MFA in [1] has been carried out using randominputs and calculation of performance metrics.

In this paper, the GDI technique is used to design the MFApresented in [1]. The GDI cell is used as a building block torealize the 16-bit error tolerant adder (GDI-HSETA).

Implementations of MFA cell based on different logic func-tions are studied and the performance is compared based onsimulations using pSpice.

3 Existing Methodology

3.1 Introduction to GDI and FS-GDI

The GDI method is based on the use of a simple cell asshown in Fig. 1 [7]. The cell consists of three inputs: G(common gate input of both the nMOS and the pMOS),P (input to the source / drain of the pMOS), and N(input to the source / drain of the nMOS). Multiple

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CONVENTIONAL 1 BIT ADDER DESIGN 1Fig. 6 pSpice Implementation ofconventional adder design 1

388 J Electron Test (2019) 35:383–400

Boolean functions can be implemented by a simple GDIcell as shown in Table 1.

The drawback of the basic GDI cell is that it suffers due tothreshold voltage drop which reduces current drive and there-fore performance of the gate is affected. To overcome theproblem, full-swing GDI cells have been proposed in [8].

The technique proposed includes swing restoration (SR) tran-sistor to improve the output swing. SR transistors have beenused to realize F1 and F2 in [5, 8]. Figures 2 and 3 shows theimplementation of full swing GDI XOR gate and GDI MUXrespectively. In this paper, the full swing GDI gates have beenused to implement the proposed error tolerant adders.

GDI MFA 1 BIT ADDER DESIGN 1

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Fig. 7 pSPICE implementation of GDI-MFA design1

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3.2 Error Tolerant Adders

Many approximation schemes have been proposed by de-creasing the critical path and hardware complexity of the con-ventional adder. In a conventional adder circuit, the delay ismainly attributed to the carry propagation chain along the

critical path, from the least significant bit (LSB) to the mostsignificant bit (MSB). If the carry propagation is curtailed, agreat improvement in speed performance and power con-sumption can be achieved. Table 2 presents the truth table ofapproximate full adder (AFA) and modified full adder (MFA).From the truth table, it is observed that authors in [32] have

GDI MFA 1 BIT ADDER DESIGN 2

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Fig. 8 pSPICE implementation of GDI-MFA design 2

390 J Electron Test (2019) 35:383–400

introduced 2 errors in sum and no error in carry term(AFA). Though this arrangement reduces error, thespeed of operation and power dissipation is compara-tively higher. Another drawback of the above adders isthat, even though the circuit is simplified due to theassumption of error, a carry generator circuitry is need-ed to generate the carry term [1]. Hence, in this paperMFA proposed in [1] is used as 1-bit adder cell.

Table 3 lists the Boolean expressions for realizing thesum and carry terms based on different design ap-proaches. In this paper, performance of various designsis compared in terms of number of transistors used,power dissipation and speed of operation. AFA andMFA Design 1 uses XOR gate output as an intermediateresult for computing Sum and Carry expressions. ForAFA design, Sum expression is obtained by invertingthe Carry term as per Table 2.

Similarly, for MFA designs Carry expression is obtainedfromA input of the adder. The transistor level realization of allthe Boolean expressions is performed using full swing GDI

gates. Full swing XOR gate proposed in [5] is used in thedesign of the adders. The results are presented in Section 5.

4 Proposed Methodology

This section presents the implementation of MFA and AFAusing GDI technique.

4.1 Proposed GDI-MFA

In MFA design, two errors are assumed in the carry term andno error assumed in the sum term so as to avoid the additionalcarry generator circuit. Hence the performance is improvedwhen compared to AFA [1]. From the implementations, it isseen that MFA design 2 requires minimum number of transis-tors. Table 4 shows the GDI implementation of AFA andMFA1-bit adder cell for the Boolean expressions listed inTable 3.GDI implementation of conventional adders is pre-sented in [5].

Fig. 9 Simulation result of 1-bitconventional adder Design 1 forvarious input combinations

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4.2 Proposed GDI-HSETA

The 1-bit GDI-MFA presented in Section 4.1 is used to con-struct 16-bit high speed error tolerant adder termed as GDI-HSETA. The proposed GDI-HSETA is based on the blockdiagram shown in Fig. 4. The addition is divided into accurate(MSB) part and inaccurate (LSB) part. The accurate part isimplemented using CSLAwith conventional full adder (FA).The inaccurate part (LSB) is implemented using GDI-MFA.Figure 5 shows the detailed block diagram of GDI-HSETA.

The carry input to each MFA cell in the inaccurate part isgiven by

C0 ¼ 0 ð1Þ

Ci ¼ ai−1 for i ¼ 1 to 8: ð2Þ

and the sum term is calculated as

si ¼ ai−1⊕ai⊕bi ð3Þ

Fig. 10 Simulation result of 1-bitMFA Design 2 for various inputcombinations

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5 Results and Discussion

Simulation of the proposed adders has been performed inORCAD pSPICE 16.6 tools. The parameters considered forcomparison are transistor count and power dissipation.

5.1 Simulation Results of 1-Bit Full Adder

Full adder cells based on conventional design, AFA designsare compared with the proposed designs. pSpice circuits havebeen constructed for evaluation of performance metrics.Figures 6, 7 and 8 present the pSpice implementation ofConventional adder design 1, GDI-MFA design 1 and 2respectively.

Figures 9 and 10 show the result of 1-bit adder cells forvarious input combinations. The propagation delay for gener-ating the sum term is calculated from the simulation results asshown in Figs. 11 and 12.

Table 5 shows the simulation results of 1-bit full addercells. The average power consumption and delay are mea-sured for all possible input combinations

5.1.1 Power Consumption

Power consumed by adder is computed through simulation.Among conventional designs, Design 1 consumes low powerand has reduced transistor count because of the imple-mentation of XOR gate using GDI technique. Design1has 33% reduced power consumption compared toDesign 3 and 16% less power compared to Design 2.Among AFA, Design 2 has less power consumptioncompared to other designs, though transistor count ismore compared to Design 1. The reason is, simplifiedimplementation using GDI XOR gate. AFA design 2 has22% less power consumption compared to AFA Design1 and 67% less compared to AFA Design 3. AFA

Fig. 11 Calculation ofpropagation delay for 1-bit AFADesign 1

J Electron Test (2019) 35:383–400 393

Fig. 12 Calculation ofpropagation delay for 1-bit AFADesign 2

Table 5 Simulation results of 1-bit full adder cells

Sl. no Type Power dissipation(μW)

Delay(pS)

No. oftransistors

1 Conventional Design 1 649.96589 750.649 18

2 Conventional Design 2 811.49126 983.811 22

3 Conventional Design 3 988.81574 992.583 23

4 AFA Design 1 812.44982 850.435 14

5 AFA Design 2 632.27591 780.870 16

6 AFA Design 3 1057.88 810.526 21

7 MFA Design 1 649.96579 724.348 14

8 MFA Design 2 612.57155 662.609 12Fig. 13 Comparison of transistor count of 1-bit adder cells

394 J Electron Test (2019) 35:383–400

Design 3 has largest power consumption due to com-plexity of the circuit and increased number of transis-tors. Among the MFA, Design 2 has 5.7% less powerconsumption compared to MFA Design 1. Also, com-paring the performance of Conventional, AFA andMFA, it is observed that MFA based designs has mini-mum power consumptions.

5.1.2 Delay

Delay is measured by accounting the time taken for theoutput to fall from 90% of HIGH value to 10% ofLOW value. The method of computing delay is shownin Figs. 11 and 12. Based on the observations, amongthe conventional adders, Design 1 has 23% and 24.3%less delay compared to Design 2 and 3. Among the

AFA adders, Design 3 has the least delay which amountto 4.7% less compared to Design 1 and 4.8% comparedto Design 2. Among the MFA, design 2 has 8.5% lessdelay compared to Design 1.

From Table 5 it is clear that MFA Design 2 con-sumed least power because the number of transistorsused is minimum. Also, it should be noted that thereduction in power dissipation and delay in MFA addersis at the cost of accuracy. Two out of the eight possiblecombinations of input to MFA produces erroneous re-sult, which can be tolerated by less critical applications.Figures 13, 14 and 15 shows a comparison of transistorcount, delay and power dissipation for various configu-rations of 1-bit adder cells.

5.2 Performance Evaluation of GDI-HSETA

Simulation is performed using pSPICE 16.6 tool and the pa-rameters considered are power consumption and area. Basedon the study of 1-bit adder cells, various combinations areproposed for 16-bit error tolerant adders. 16-bit error tolerantadder consists of two parts, namely MSB 8-bit accurate partand LSB 8-bit inaccurate part. Based on the study of GDIadders in Section 5.1, it is observed that performance ofConventional Adder Design 1 is better compared toConventional Adder Design 2 and Conventional AdderDesign 3. Hence, Conventional Adder Design1 is used toconstruct the MSB 8-bit part of the 16-bit adder. Accurate

Fig. 14 Comparison of delay of 1-bit adder cells

Fig. 15 Comparison of power dissipation of 1-bit adder cells

Table 6 16 Bit adder types

Sl.No Type 16 bit adders

MSB 8 BIT LSB 8 BIT

1 Type 1 Accurate Conventional Design 1(CLSA)

Inaccurate Conventional Design 1

2 Type 2 Accurate Conventional Design 2 CLSA)

Inaccurate Conventional Design 2

3 Type 3 Accurate Conventional Design 3 CLSA)

Inaccurate Conventional Design 3

4 Type 4 Accurate Conventional Design 1 (CLSA)

Inaccurate AFA Design 1

5 Type 5 Accurate Conventional Design 1(CLSA)

Inaccurate AFA Design 2

6 Type 6 Accurate Conventional Design 1(CLSA)

Inaccurate AFA Design 3

7 Type 7 Accurate Conventional Design 1(CLSA)

Inaccurate MFA Design1

8 Type 8(GDI-HSETA)

Accurate Conventional Design 1(CLSA)

Inaccurate MFA Design 2

J Electron Test (2019) 35:383–400 395

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Y

VD

DA B

Cin

GN

D

conv _design1

SU

M

CA

RR

Y

VD

DA B

Cin

GN

D

conv _d1_bit13

conv _design1

SU

M

CA

RR

Y VD

DA B

Cin

GN

D

conv _d1_bit14

conv _design1

SU

M

CA

RR

Y VD

DA B

Cin

GN

D

conv _d1_bit15

conv _design1

SU

M

CA

RR

Y VD

DA B

Cin

GN

D

conv _d1_bit16

conv _design1

SU

M

CA

RR

Y VD

DA B

Cin

GN

D

GDI_MUX2 gdi_mux

outp

ut

VD

D

GN

D A B

SEL

SB1

SB1

GDI_MUX3 gdi_mux

outp

ut

VD

D

GN

D A B

SEL

Fig. 17 pSpice simulation of 8-bit CSLA using Conventional Design 1 (Transistor count: 348)

396 J Electron Test (2019) 35:383–400

Table 7 Comparison of power dissipation and transistor count of 16-bit adder

Sl. No 16 bitadderstype

PowerDissipation(mW)

Adders Multiplexers Total

Transistor peradder cell

Numberof cells

Total number oftransistors (1)

Number of 2:1multiplexers

Transistor permultiplexer

Total number oftransistors (2)

1 + 2

1 Type 1 24.8 18 16 432 10 6 60 49218 8

2 Type 2 74.4 22 16 528 10 6 60 58822 8

3 Type 3 121.4 23 16 552 10 6 60 61223 8

4 Type 4 15.95 18 16 400 10 6 60 46014 8

5 Type 5 14.7 18 16 416 10 6 60 47616 8

6 Type 6 16.54 18 16 456 10 6 60 51621 8

7 Type 7 14.0 18 16 400 10 6 60 46014 8

8 Type 8 12.8 18 16 384 10 6 60 44412 8

af a_d1_1bit

d1

DD

V GN

D BA

Cin

SU

M

CA

RR

Y

af a_d1_1bit2

d1

VD

D

GN

D BA

Cin

SU

M

CA

RR

Y

af a_d1_1bit3

d1

VD

D

GN

D BA

Cin

SU

M

CA

RR

Y

af a_d1_1bit4

d1

VD

D

GN

D BA

Cin

SU

M

CA

RR

Y

af a_d1_1bit5

d1

VD

D

GN

D BA

Cin

SU

M

CA

RR

Y

af a_d1_1bit6

d1

VD

D

GN

D BA

Cin

SU

M

CA

RR

Y

af a_d1_1bit7

d1

VD

D

GN

D BA

Cin

SU

M

CA

RR

Y

af a_d1_1bit8

d1

VD

D

GN

D BA

Cin

SU

M

CA

RR

Y

conv _d1_bit1

conv _design1

DD

V A B Cin

GN

D

SU

M

CA

RR

Y

conv _d1_bit2

conv _design1

VD

D

A B Cin

GN

D

SU

M

CA

RR

Y

conv _d1_bit3

conv _design1

VD

D

A B Cin

GN

D

SU

M

CA

RR

Y

conv _d1_bit4

conv _design1

VD

D

A B Cin

GN

D

SU

M

CA

RR

Y

conv _d1_bit5

conv _design1

VD

D

A B Cin

GN

D

SU

M

CA

RR

Y

conv _d1_bit6

conv _design1

VD

D

A B Cin

GN

D

SU

M

CA

RR

Y

conv _d1_bit7

conv _design1

VD

D

A B Cin

GN

D

SU

M

CA

RR

Y

conv _d1_bit8

conv _design1

VD

D

A B Cin

GN

D

SU

M

CA

RR

Y

ACCURATE 8 BIT CSLA USING CONVENTIONAL DESIGN 1

Cin5Vdc

B0Vdc

VDD5Vdc

0

A0Vdc

INACCURATE 8 BIT ADDER USING AFA DESIGN 1

Fig. 18 Implementation of Type 4 adder in pSpice (Transistor count: 460)

J Electron Test (2019) 35:383–400 397

MSB part is implemented as CSLA structure because CSLAcan achieve high speed with increased hardware complexity.The LSB inaccurate part is constructed using various designsof AFA and MFA. The resulting combinations considered for

study are listed in Table 6. pSpice 16.6 is used to simulate thebehavior of various types of 16-bit adders. Conventional adder

mf a_d2_bit8

d2

CA

RR

Y

SU

M

VD

D A B

Cin

GN

D

conv _d1_bit1

conv _design1

DD

V A B Cin

GN

D

SU

M

CA

RR

Y

conv _d1_bit3

conv _design1

VD

D

A B Cin

GN

D

SU

M

CA

RR

Y

conv _d1_bit2

conv _design1

VD

D

A B Cin

GN

D

SU

M

CA

RR

Y

conv _d1_bit4

conv _design1

VD

D

A B Cin

GN

D

SU

M

CA

RR

Y

conv _d1_bit5

conv _design1

VD

D

A B Cin

GN

D

SU

M

CA

RR

Y

conv _d1_bit6

conv _design1

VD

D

A B Cin

GN

D

SU

M

CA

RR

Y

conv _d1_bit7

conv _design1

VD

D

A B Cin

GN

D

SU

M

CA

RR

Y

conv _d1_bit8

conv _design1

VD

D

A B Cin

GN

D

SU

M

CA

RR

Y

ACCURATE 8 BIT CSLA USING CONVENTIONAL DESIGN 1

Cin5Vdc

-4.998mW

B0Vdc

0W

VDD5Vdc

-3.524nW

0

A0Vdc

0W

INACCURATE 8 BIT ADDER USING MFA DESIGN 2

mf a_d2_bit1

d2

CA

RR

Y

SU

M

DD

V

A B

Cin

GN

D

mf a_d2_bit2

d2

CA

RR

Y

SU

M

VD

D A B

Cin

GN

D

mf a_d2_bit3

d2

CA

RR

Y

SU

M

VD

D A B

Cin

GN

D

mf a_d2_bit4

d2C

AR

RY

SU

M

VD

D A B

Cin

GN

D

mf a_d2_bit5

d2

CA

RR

Y

SU

M

VD

D A B

Cin

GN

D

mf a_d2_bit6

d2

CA

RR

Y

SU

M

VD

D A B

Cin

GN

D

mf a_d2_bit7

d2

CA

RR

Y

SU

M

VD

D A B

Cin

GN

D

Fig. 19 Implementation of Type 8 (GDI-HSETA) adder (Transistor count: 444)

Fig. 20 Comparison of transistor count of 16-bit approximate adders Fig. 21 Comparison of power dissipation of 16-bit adder cells

398 J Electron Test (2019) 35:383–400

Design 1 is used to implement the CSLA because of reducedpower consumption and transistor count as shown in Table 5.GDI-MUX is used to implement the multiplexer used in the 8-bit CSLA. The pSpice model of the GDI MUX is shown inFig. 16.

A GDI multiplexer requires 6 transistors for implementa-tion. 10 multiplexers are required to realize 8-bit CSLA adder.Also, 8 1-bit Conventional Design 1 adder cells are required.Each 1-bit adder cell requires 18 transistors as shown inTable 5. Hence total number of transistors to realize 8-bitCSLA is (18*16) + (10*6) =348. Based on the studyof the circuit shown in Fig. 17 it is observed that thepower consumption is 12.3 mW. The 8-bit CSLA blockis used as the MSB portion of various 16-bit addersshown in Table 7. The pSpice implementation of Type4 and Type 8 is shown in Figs. 18 and 19. Powerdissipation of Type-1 to Type-8 adders is studied andthe results of simulation are tabulated in Table 7.

The comparison of power dissipation and transistor countfor Type-1 to Type-8 adders is shown in Figs. 20 and 21.

From the results it is observed that Type-3 has maximumpower dissipation. The reason is Type-3 is implemented usingConventional Design 3 for both accurate and inaccurate part.Since the number of transistors required for ConventionalDesign 3 is high, there is a corresponding increase in powerdissipation. Also, for all types there is an additional overheadof power dissipation due to the use of multiplexers in thedesign.

Further, the adders are implemented on FPGA Spartan 6platform to evaluate the hardware performance and the results

are presented. GDI-HSETA requires 26% less number of tran-sistors and 45% less power compared to 16-bit adders usingconventional design as shown in Table 8. Also, based onhardware implementation, it is observed that GDI-HSETAutilizes fewer amount of resource compared to other adderdesigns as shown in Table 9. From the results obtained it canbe concluded that the proposed designs operate with less pow-er consumptions at the cost of accuracy. These designs can beconsidered as suitable candidates for realizing energy efficienterror tolerant applications.

6 Conclusion

GDI-HSETA is applicable to general purpose circuit, with afew exceptions. The demand for portable electronic devicesacts as a driving force for the designers to strive for smallerarea, lower power consumption and longer battery life. In thisproposed adder consumes less power and less delay whencompared to the AFA structure and conventional structure.The error tolerant adder is designed at transistor level withreduced complexity in the 8 bit LSB part. The proposedGDI-MFA has 52% less transistor count and consumes 33%less power compared to conventional adders. Results of sim-ulation of GDI-HSETA and other adders in pSpice indicatethat the proposed adder has 21.6% power reduction and 13%less transistor count. The speed of the circuit is 37% fasterthan the existing adder. Further the proposed adder can beused for error tolerant applications such as real time imageprocessing.

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Adderscheme

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Slices(Available:600) used

BondedIOB(Available:132) used

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16 bit Adder Transistor count Power (μw)

Conventional Adder – Design2 706 815.67

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Publisher’s Note Springer Nature remains neutral with regard tojurisdictional claims in published maps and institutional affiliations.

S. Geetha received her B.E degree in electronics and communicationengineering and M.E degree in embedded and real time systems fromCoimbatore Institute of Technology, Coimbatore, India in 1995 and 2005respectively. She received her Ph.D degree in information and communi-cation engineering from Anna University. She is working in Coimbatoreinstitute of technology from 2007 onwards.

P. Amritvalli received her B.E degree in electronics and communicationengineering. She is currently pursuing her M.E degree in Applied elec-tronics in Coimbatore Institute of Technology.

400 J Electron Test (2019) 35:383–400