Journal of Electronic Testing (2019) 35:441–457https://doi.org/10.1007/s10836-019-05811-1

Test Generation for Bridging Faults in Reversible Circuits UsingPath-Level Expressions

Mousum Handique1 · Santosh Biswas2 · Jantindra Kumar Deka1

Received: 31 October 2018 / Accepted: 10 June 2019 / Published online: 22 June 2019© Springer Science+Business Media, LLC, part of Springer Nature 2019

AbstractRecently there has been a growing interest in the applicability of reversible circuits. Reversible circuits are designed usingreversible gates, which can efficiently reconstruct the previous state of the computation from the current state. These circuitsmay find potential applications to the future generation of optical and quantum computers. To ensure the reliability of thesecircuits, testing is a mandatory phase of the design cycle. Several fault models have been introduced for reversible circuitsamong which some of them have been taken from the conventional circuits. In this paper, we consider the problem oftesting bridging faults (such as single and multiple input bridging faults, single and multiple intra-level bridging faults) ina reversible circuit designed with the NOT, CNOT, Toffoli gates (NCT library) and generalized (n-bit) Toffoli gates (GTlibrary). We propose an Automatic Test Pattern Generation (ATPG) method using the Path-Level expression for generatingthe minimal complete test set to detect the faults mentioned above. The analysis of the experimental results shows that theproposed method has 100% fault coverage, and test set size is smaller than the existing methods.

Keywords Reversible computing · Reversible circuit · Bridging faults · Complete minimal test set · Path-Level expression

1 Introduction

Reversible computing involves operations that can be easilyand exactly reversed or undone [7, 8]. This unconventionalmethod of computing can be classified as (i) logicalreversibility if the input and output of any deterministicdevice are uniquely retrievable from each other; (ii)physically reversibility, where a device can run backward.

Responsible Editor: B. B. Bhattacharya

� Santosh Biswassantoshbiswas402@yahoo.com

Mousum Handiquemousum@iitg.ac.in

Jantindra Kumar Dekajatin@iitg.ac.in

1 Department of CSE, Indian Institute of Technology,Guwahati (IITG), Guwahati 781039, Assam, India

2 Department of EECS, Indian Institute of Technology,Chhattisgarh, Bhilai, India

According to Moore’s law [30], the number of transistorsdoubles every 18 months. As a result, today’s circuittechnologies have large power dissipation. R. Landauer [13]showed that energy dissipation is lower if the operationsare logically reversible. The amount of energy required tochange one bit of information, known as Landauer limitis kT ln2 Joules, where k is the Boltzmann constant andT is the temperature of the system. Charles Bennett [2]showed that the information is lossless if the operationsare performed reversibly. As reversible circuits satisfy boththese conditions, they are gaining popularity in the recenttimes.

To assure the correct functionality and durability of anintegrated circuit, testing is essential during as well asafter design and manufacturing. Fault detection and faultlocalization are two important phases in the field of circuittesting. The first phase involves detecting the presenceof faults in the circuit and later on finding the exactlocation of these faults. Therefore, fault detection is thebasic requirement of fault localization. The fault modelhelps to describe the physical defects in the circuit suchthat the designer can easily predict the occurrence of aparticular fault in the circuit. Hence, different types of fault

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models are used to evaluate the faults in both conventionaland reversible circuits. Various fault models for reversiblelogic circuits have been proposed, where some of them arecommon to the conventional logic circuits [27].

The test generation process for detecting the faults inreversible circuits is relatively simpler than conventionallogic circuits because the property of reversibility ensureshigh controllability and observability [22]. An input testvector is capable to detect the fault if the input test vectorproduces different primary outputs for the faulty and fault-free circuits. In general, a test set is complete if all thepossible faults are covered in a given reversible circuit. Sucha test set is called minimal complete test set if it contains theminimum number of test vectors [22]. Effort for generatinga test vector is directly affected by the two essentialproperties i.e., controllability and observability. To brieflyillustrate these two properties, we consider the NCT-basedreversible circuit as shown in Fig. 1. The controllabilityproperty provides the information to set the binary values tothe input lines at any level and backtracking is applied to thebinary values (considered as a vector) for finding the uniqueinput vector at the initial level in the reversible circuit. Asshown in Fig. 1, the vector 0101 is present at level L3 basedon the gate operation. Suppose, backtracking is applied tolevel L3 and L2. As a result, 1101 vector is present at levelL2. The same backtracking process is applied on level L2

and L1 using the vector 1101, and it gives the resultantvector 1101 at level L1. Finally, one more backtrackinggenerates the input vector 0101 at the input level L0. Fromthis observation, it is evident that for any particular level ina given reversible circuit, it is always possible to extract theunique vector at the input-level. The observability propertyguarantees that if there is any changes in the intermediatelevel, then the primary output of the circuit is also changed.As an example, the vector 1101 at level L2 generates theprimary output vector 0111, as shown in Fig. 1. It may be

Fig. 1 Illustration of a Reversible circuit for controllability andobservability property

noted that any other vector at level L2 produces differentprimary output.

There are various works that have been reported in theliterature for efficient test set generation for detecting thefaults based on the different fault models in the reversiblecircuits [3, 12, 25, 35]. In this work, we focus on generatingthe complete test set with minimal test set size for thebridging fault model in reversible circuits. For this purpose,we propose an ATPG method to find the complete testset for detecting the Single Input Bridging Faults (SIBF),Multiple Input bridging faults (MIBF), Single Intra-levelBridging Faults (SIRBF) and Multiple Intra-level BridgingFaults (MIRBF). Our proposed ATPG scheme is developedwith the concept of reversible property– “for every vectorat the output of a reversible gate; there exists a uniquevector at the input.” Moreover, we are using the path-levelexpression for generating the complete test, which is also aminimal test set. This approach has been implemented andevaluated on various benchmark circuits with NCT and GTlibrary.

The rest of the paper is organized as follows. Section 2provides some basic background of reversible logic, basicreversible gates, fault models and discussion on bridgingfault models. The related work on bridging fault detection inthe reversible circuits is given in Section 3. In Section 4, wedescribe our proposed method for generating the minimalcomplete test set to detect the bridging faults with the help ofdetailed illustrations. The experimental results and analysisof comparison with existing test pattern generation methodsare presented in Section 5. Finally, concluding remarks withsome possible directions for future works are presented inSection 6.

2 Background

2.1 Reversible Logic

Reversible logic is one of the highly promising areas oflow-power CMOS design technologies. The reversible logictheory is built by the reversible function. A function is calleda reversible function if the number of outputs is equal tothe number of inputs and inputs always produce a uniqueoutput, i.e., bijective in nature. In circuit design technology,these reversible logic functions are implemented by thereversible logic operations, which are called reversiblegates. Thus, the reversible circuit should satisfy certainconditions: n-input and n-output bijective function, and nofan-out and feedback connections [21]. These conditionsleave the reversible circuit as a linear cascade networkstructure of reversible gates [15], i.e., if i is the ithgate

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(Gi) in a reversible circuit, then the gate Gi is activeif and only if the gate G(i−1) has produced an outputand an output of G(i−1) is considered as an input ofgate Gi .

2.2 Reversible Gates

The logic gates in a conventional circuit other than the NOTgate are not reversible. The NOT gate for both conventionaland reversible circuits satisfies the equal number of inputsand outputs with a bijective mapping between them. Usingthe NOT gate operation, the output is easily extracted fromthe input and vice versa. Suppose if we consider the classicalAND gate for any conventional circuit and consider thatAND gate produces the output bit as 0, then from an outputbit 0, we are unable to tell which input bits (0,1) or (1,0) areassociated with the corresponding output bit. Therefore, aset of reversible gates is required to implement the reversiblecircuits. In reversible circuit design, several gates have beenproposed in the literature. Some of the basic reversible gatesare NOT gate, controlled-not (CNOT) or FEYNMAN gate[6], TOFFOLI gate [33], FREDKIN gate [9], PERES gate[23] and SWAP gate [14]. The symbolic representation ofthese gates are shown in Fig. 2. The NOT gate is a singleinput gate that simply inverts the input. The behavior ofthe CNOT gate passes the first input as it is (P = A) andinverts the second input (Q = A ⊕ B) if the first inputis 1. The reversible gate with k-input and k-output lines(wires) is called a k×k gate or a gate on k wires [31]. TheTOFFOLI gate has 3-input lines, 3-output lines and if thefirst two input lines (A, B) are set as 1 then it inverts thethird output line (R = C ⊕AB). The family of NOT, CNOTand TOFFOLI gate is called NCT library. Moreover, if thenumber of input lines is more than 3 then it is called asgeneralized multiple-control TOFFOLI gate and family ofthese type of gates is called GT library. FREDKIN gate has3 × 3 gates with inputs (A, B, C) and outputs P = A,Q = AB ⊕ AC and R = AB ⊕ AC. The PERES gate has3 × 3 gates having inputs (A, B, C) and outputs P = A,

Q = A ⊕ B and R = C ⊕ AB. The SWAP gate has 2 × 2gate which exchanges the inputs, i.e., P = B and Q = A.

2.3 Fault Models in Reversible Circuit

In a circuit design domain, there is a massive number ofphysical defects in a chip, and also it is impossible tocount and analyze the all possible faults. For evaluatingthe physical defects, we can not directly apply themathematical treatment of testing. Thus, we need someabstract representations of these physical defects. Theseabstract representations have been formulated based onthe mathematical model called a fault model. Moreprecisely, a fault model is a mathematical model thatdescribes the different level of abstraction of physicalfault in a system. The level of abstraction can be definedas behavioral, functional, structural, and geometric [11].Based on the process of developing the mathematicalmechanisms, the fault model can be applied to evaluatethe faults and also helps to reduce the complexity ofdetecting the faults. Therefore, the fault model is anabstract representation of the physical defects in thesystem.

Let us assume that FM is the fault model that abstractsthe faults in a way such that gates are assumed to be fault-free; however, the interconnection of gate netlist is faulty.Let Z(x) be the logic function of a circuit C, where x

represents an input vector assigned by the input lines of thecircuit. Here, fault f denotes the faulty interconnection ofthe gate netlist. Due to the presence of fault f , the functionZ(x) of the circuit C transforms to the new function Zf (x)

which is realized by the new circuit Cf . More precisely

: FM={Z(x)f=⇒ Zf (x) | Z(x) ∈ C and Zf (x) ∈ Cf ,

∃ x where, Z(x) �= Zf (x)} represents the faults f in thecircuit.

Depending on the reversible gate operations and structureof the circuit, few more fault models are required in additionto traditional fault models for detecting all faults of these

Fig. 2 Basic Reversible Gates aNOT b CNOT c TOFFOLI dFREDKIN e PERES f SWAP;and their Gate Operation [32]

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circuits. In the literature, we observed that several faultmodels are applied to the NCT library. Some of them areStuck-at Fault (SAF) [4, 10, 19, 20, 22],Bridging Fault (BF)[3, 4, 18, 25, 28], Missing-Gate Fault (MGF) [5, 12, 19, 24,26], Crosspoint Fault [35], Cell Fault [22], etc.

In this work, we consider the bridging faults in thereversible circuit. In the following subsection, we discussthe bridging faults in details with the help of a reversiblebenchmark circuit nth P rime3 inc as shown in Fig. 4(a).

2.3.1 Bridging Fault Model in Reversible Circuit:

The bridging fault is considered as a structural fault modelin the reversible circuit similar to the conventional circuit. Abridging fault occurs when two or more signal lines (wires)in the circuit are unintentionally or accidentally shortedtogether to create a wired logic that gives a faulty output ofthe circuit [17]. More precisely, the logic value on a signalline can be affected by the logic value of the other signallines which are coupled or shorted together. According tothe bridging fault property, the short between two or moresignal lines creates a new wired logic function. This newlyformed logic function can be classified into two types.

1. AND-Bridging: If the logic value of the two or morelines establishes the connection in the form of wired-AND logic operation, then the fault is considered asAND-Bridging Fault. Consider a circuit C with n inputlines (x1, x2, . . . , xn) and the output function Z thatis realized by the circuit C is Z=g(x1, x2, . . . , xn).Consider a bridging fault between two independentlines xi and xj . If the fault is AND-Bridging,then xi=xj=xi .xj and the faulty output Zf is Zf =gAND(x1, x2, . . . , xi .xj , . . . , xn). In case of multiplebridging faults between k lines, for AND-Bridgingx1=x2= . . .=xk=x1 . x2. . . . .xk .

2. OR-Bridging: If the logic value of the two or more linesestablishes the connection in the form of wired-ORoperation, then the fault is considered as OR-BridgingFault. In fault-free condition, the output function Z

Fig. 3 Illustration of Bridging Fault: a AND-Bridging Fault b OR-Bridging Fault

that is realized by the circuit C is g(x1, x2, . . . , xn).Consider a bridging fault between two independentlines xi and xj . If the fault is OR-Bridging, thenxi=xj=xi + xj and the faulty output Zf is Zf =gOR(x1, x2, . . . , xi + xj , . . . , xn). In case of multiplebridging faults between k lines, for OR-Bridgingx1=x2= . . .=xk=x1 + x2 + . . . + xk .

The structural behavior and logical effect of wired-ANDand wired-OR bridging faults on a reversible circuit aredepicted in Fig. 3. Here, the reversible circuit consists of oneTOFFOLI gate with 3-input lines a, b and c. The reversiblefunctions realized at output are Z(a′)=a, Z(b′)=ac ⊕ b, andZ(c′)=c. In Fig. 3a, we notice that the two lines a and c

are wired-AND at level L0, i.e., ∗(a ←→ c); due to thiseffect, the logic value of signal line c changes from logicvalue 1 to 0, which is marked as bold at line c in level L0

of Fig. 3a. After the gate operation, the faulty logic valueof the signal line c at level L0 is propagated to the signalline c′ at level L1. As a result, the logic value in line c′ atlevel L1 is 0 (marked as bold) which is faulty, i.e., 1/0 (fault-free/faulty). In Fig. 3b, the wired-OR bridging fault appearsbetween the line a and c i.e., +(a ←→ c) at level L0. Dueto the presence of this fault, the logic value of the signalline a changes from logic value 0 to 1 at level L0, whichaffects the output after the gate operation. The faulty outputat signal lines a′ and b′ in level L1 are 1 and 1 respectively,i.e., 0/1 (fault-free/faulty).

The general property for detecting the bridging faultsis that opposite logic values drive the two affected linesat the same level [1]. Given the network structure [15] ofthe reversible circuit, the bridging faults occur at differentlocations of the same level or maybe at different levels.The intra-level bridging faults occur when the two or moreconnected lines are at the same level, and if two or moreconnected lines are involved at different levels, then it isconsidered as inter-level bridging faults. The single bridgingfault refers to the case when only two lines are involved inthe fault. If more than two lines are involved in generatingthe bridging fault, then it is referred to as a multiple bridgingfault.

1. Single input bridging Faults: If the bridging faultoccurs between the two input lines at the initial level(input level), then it is called a single Input BridgingFault (SIBF). The number of single input bridging faultsis C(N, 2), where N is the number of input lines ina given reversible circuit. If we consider both AND-Bridging Fault and OR-Bridging Fault then the totalnumber of single input bridging faults is {2×C(N, 2)}.Fig. 4b shows the single input bridging faults.

2. Multiple input bridging Faults: If the bridging faultoccurs between more than two input lines at the inputlevel then, it is considered as a Multiple Input Bridging

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Fig. 4 Demonstration ofReversible circuitnth P rime3 inc for variousbridging fault conditions

Fault (MIBF), which is shown in Fig. 4c. The numberof multiple inputs bridging faults is {NC3 +N C4 +. . . +N Ci + . . . +N CN }, where 3 < i < N . The totalnumber of multiple input bridging faults (consideringboth AND-Bridging Fault and OR-Bridging Fault) is{2 × (NC3 +N C4 + . . . +N Ci + . . . +N CN)}.

3. Single intra-level bridging Faults: The Single Intra-Level Bridging Fault (SIRBF ) occurs when the twoshorted lines are at the same level in a given reversiblecircuit. However, the single input bridging faults are thesubset of single intra-level bridging faults. The numberof intra-level bridging faults is |LS | × C(N, 2), whereLS is the set of levels, excluding the input level. Thesingle intra-level bridging fault is shown in Fig. 4d.

4. Multiple intra-level bridging Faults: The MultipleIntra-Level Bridging Fault (MIRBF) is represented bymore than two lines getting shorted at the same level inthe given reversible circuit, which is shown in Fig. 4e.Here, the multiple input bridging faults are the subsetof multiple intra-level bridging faults. The number ofmultiple intra-level bridging faults is {|LS | × (NC3 +N

C4 + . . . +N Ci + . . . +N CN)}. If we consider both

AND-Bridging and OR-Bridging faults, then multipleintra-level bridging faults are just the double.

We have used the nth P rime3 inc reversible benchmarkcircuit as depicted in Fig. 4a and shown the various bridgingfaults with the help of AND-Bridging fault model. Figure 4bshows that an input line ‘a’ is shorted with the input line ‘b’at the input level L0. The effect of this fault is representedby the truth table as shown in Table 1. We have extractedthe test vectors by comparing the fault-free output with thefaulty output. Therefore, the test vector 010 or 011 or 100 or101 is required to test this fault. Similarly, for multiple inputbridging fault, the input lines ‘a’, ‘b’ and ‘c’ are shorted witheach other at the input level L0. As shown in Table 1, thepossible test vectors are 001, 010, 011, 100, 101, and 110and any one of these test vectors is capable of detecting themultiple input bridging fault as shown in Fig. 4c.

For single intra-level bridging faults, the input line ’a’ isshorted with the input line ’c’ at the 3rd level L3 as depictedin Fig. 4d. As mentioned in Table 1, the test vectors 001 or011 or 101 or 111 is capable of detecting the single intra-level bridging faults, which is shown in Fig. 4d. Figure 4e

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shows the multiple intra-level bridging faults. For detectingthese faults, the test vector 001 or 010 or 011 or 101 or 110or 111 is needed.

3 RelatedWork on Bridging Faults

Some of the existing works on testing of Bridging Faultsthat is briefly reviewed in this section. In 2007, the authorsin [3] have proposed a Design-For-Test (DFT) methodologyfor detecting the single intra-level bridging faults in areversible circuit with n-bit TOFFOLI gates. The proposedDFT method generates the test set of size (�log2N�)+3 andit is sufficient to detect single intra-level bridging and singlestuck-at fault. However, this scheme requires an additionalinput wire to the n-bit TOFFOLI gates (as the DFT circuit.)In 2008, Rahaman et al. [25] showed that a test set ofcardinality (d log2 n) is sufficient for detecting all intra-level bridging faults in an n-input and n-output reversiblecircuit with d levels. In 2008, Sarkar et al. [28] presenteda polynomial time algorithm, which generates a set of testvectors of size n for detecting all single and multiple inputbridging faults and all input stuck-at faults in any n-inputand n-output reversible circuit. In 2011, the authors in [29]have proposed a universal test set generation method of areversible logic circuit based on the shift operation on theunitary matrix. The test set size by this scheme involves(�n/2�) test vectors, which is sufficient to detect all singleand multiple input bridging faults. In 2015, Nagamani et al.[18] proposed a deterministic ATPG algorithm to generatethe complete test set for single and multiple intra-levelbridging faults in a reversible circuit designed with thefamily of Toffoli, Peres and Fredkin gates. The complexityof the ATPG algorithm is O(2n), where n is the number ofinputs in the reversible circuit.

From the literature review, we have found the followingdrawbacks of the existing test methodologies:

1. While trying to reduce the number of test vectors forcomplete bridging fault coverage, there is an additionalburden of extra circuitry (i.e, DFT circuitry).

2. The heuristic approaches for ATPG provide thecomplete test set but that may not give a minimalsolution.

3. By applying exact methods, ATPG technique canproduce a minimal test set, but computational cost ishigh.

The main contributions of this work are as follows:

(a) An ATPG algorithm is proposed to generate theminimal complete test set for detecting the bridgingfaults of type SIBF, SIRBF, MIBF and MIRBF.

(b) The scheme does not require any additional hardwarefor DFT.

(c) The test patterns are able to achieve 100% coverage forthe bridging faults.

(d) The computational complexity of the scheme isanalyzed and found to be in the logarithmic order inthe number of inputs.

4 ProposedMethod

In this section, we first present a method to find theminimum set of test vectors to detect all the single inputbridging faults at the initial level in a given reversible circuit.After that, this test set is applied as local test patternsto all the levels (excluding the initial level) of a givenreversible circuit. Next, we generate the paths betweenthe levels of the circuit using a local test pattern withthe help of backtracking. After generating all the possiblepaths, some paths are selected by the path-level expression.Here, the path-level expression is capable of producingthe unique path for each level in the reversible circuit.Finally, generated path-level expressions are matched to

Table 1 The Truth table for nth P rime3 inc reversible circuit (as mentioned in Fig. 4) with fault-free and faulty outputs

Inputs Fault-Free output Faulty outputs

SIBF MIBF SIRBF MIRBF

a b c a′ b′ c′ a′ b′ c′ a′ b′ c′ a′ b′ c′ a′ b′ c′

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 1 1 1 1 1 1 1 0 0 0 1 1 0 0 0 0

0 1 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0

0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0

1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0

1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0

1 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 0 0

1 1 1 0 1 1 0 1 1 0 1 1 1 1 0 1 0 0

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obtain the minimal complete test set for detecting allthe possible bridging faults in the reversible circuit. Thedetailed discussion of the proposed method is given inthe following subsections. Before discussing the proposedmethod, we present some definitions, which are used insubsequent discussions.

Definition 1 A test vector T V is a set of binary inputs〈b1 b2 . . . bN 〉 that provides test inputs to the input lines{l1, l2, . . . lN } for1 ≤ i ≤ N , where bi ∈ {0, 1} and N isthe number of input lines. The test vector (TV) is applied toa reversible circuit for testing.

Definition 2 A test set T S is the collection of all possibletest vectors that detect the faults in F , where F is the faultset in a given reversible circuit. Let the test set TS = {T V1,T V2..., T Vl}, for 1 ≤ j ≤ l, T Vj = 〈b1j b2j . . . bNj 〉,where bij is the ith bit of j th test vector. In the binary inputsfor the test vector T Vj , at least one-bit bij must be differentfrom some other bit bkj to detect the bridging fault betweenline i and k, where i �= k. Let the test set T SLi

be the set ofall local test patterns that are applied at level Li during testpattern generation.

Definition 3 A test set T S is called a complete test set inn-input reversible circuit that detects all the faults in F . Acomplete test set that contains the minimum possible testvectors, which are capable of detecting all the faults in F , iscalled a minimal complete test set.

4.1 Local Test Pattern GenerationMethod

If a test is capable of applying opposite logic values to everypair of lines lying at the same level, it is capable of detectingall the bridging faults in that level. Based on this concept,we generate the minimal complete test set at the initiallevel and later on, these test vectors of the minimal test setare considered as local test patterns, which are applied tothe other levels of the reversible circuit. The basic idea forgenerating the local test patterns for detecting the singleinput bridging faults in the reversible circuits is explainedbelow.

Here, we assume that the test set is denoted by T S andthe test vector by T Vi , where i ∈ N. Let us consider thetest set T S={T V1, T V2, . . . , T V�log2N�}, where N is thenumber of input lines in a given reversible circuit. Let thefirst test vector T V1 consist of alternating 0’s and 1’s. Thesecond test vector T V2 consists of an alternating sequenceof two consecutive 0’s and two consecutive 1’s. Similarly,the nth test vector consists of 2n−1 consecutive 0’s followedby 2n−1 consecutive 1’s at the N-input lines, where 1 ≤ n ≤�log2N�. This process continues until we get the last testvector T V�log2N�. Figure 5 illustrates the above process.

Example 1 : If we consider N=5, the test set T S consists ofthree test vectors, viz., T V1=〈0 1 0 1 0〉, T V2=〈0 0 1 1 0〉,and T V3=〈0 0 0 0 1〉. We observe that due to the presence ofopposite logic values of each test vector, the test set T S iscapable of detecting all the bridging faults at the initial level(L0) in a reversible circuit.

4.2 Path GenerationMethod

After generating the set T S, it is applied as a local testpattern to all the levels in a reversible circuit. A reversiblecircuit with N gates has (N+1) levels. Input to the circuitis termed as level L0, and the final output of the circuit istermed as level LN . Level Li lies between the gates Gi andGi+1. Faults basically occur in the signal wire at any leveland gates are assumed to be fault free. So the distinctionof level from the gate is necessary. Some definitionsare presented, which are used in the path generationmethod.

Definition 4 A level set LS is a set of all the levels in areversible circuit to maintain the linear cascade structure.Let the level set be LS={L0, L1, L2, . . . , LGC}, where eachgateGi lies between (i−1)th and ith level, for 1 ≤ i ≤ GC.Gi ∈ {NCT or GT library} and GC is the total number ofgates present in the reversible circuit.

Definition 5 We define a path Pk , which is generated bythe interaction of levels (Lj , Lj−1), where k ∈ N. Thepath Pk is derived using the concept of backtracking. Thebacktracking is applied on local test pattern from level Lj

to Lj−1. In other words, Pk={〈 T Vi(Lj ), T Vi−1(Lj−1 〉} |T Vi ∈ T SLj

and T Vi−1 ∈ T SLj−1}. T Vi(Lj ) means testvector T Vi ∈ T SLj

is applied at level Lj . Here, the totalnumber of Pk is equal to the total number of test vectorspresent at the input level L0.

Fig. 5 Test set generation for detecting input bridging faults

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The path Pk is generated between the two contiguouslevels of the circuit. Initially, we apply all the local testpatterns T Vi ∈ T S in each level (excluding the initiallevel L0) of the circuit. Let gate Gj lies between L(j−1)

and Lj level and the local test pattern T Vi is applied atlevel Lj that contains the gate Gj . We back propagate(say also backtracking) T Vi to obtain the correspondinginput test vector T Vj ∈ T SLj

at the input of the gate Gj ,i.e., T Vj is generated at level Lj−1. Since the reversiblegate is bijective, for a given T Vi , the corresponding T Vj

is unique. Here, the path Pk is created between the twolevels Lj and Lj−1 through the test vector T Vi and T Vj ,respectively.

Definition 6 The path is said to be a complete path ina reversible circuit if T Vi(LGC) is capable of tracing theT Vj (L0). The path may start at any level Lp, where0 < p < GC and formulate this path to be completewhen T Vi(Lp) traces the T Vj (LGC) using the forwardsimulation.

The detail illustration of the above definitions is asrepresented in Fig. 6. Here, the set of levels LS ={L1, L2, L3, L4} (excluding the initial level L0) and thetotal number of gates GC = 4 as per Definition 4. Let usconsider the gate G3, which lies between level L2 and L3.According to Definition 5, if we consider the path P1 at levelL3, then this path is derived from level L3 to L2 by applyingthe local test pattern ’010’ and the derived path P1 generatesthe test vector ’010’ at level L2. Using the backtracking,the path P1 at level L3 generates the test vector ’010’ atthe input level L0. The derived paths are P1, P2, P3 andP4. Therefore, four test vectors {010, 001, 011, 100} aregenerated at the initial level L0 as shown in Fig. 6. In thiscase, the path P1 is not derived from the primary outputlevel L4, so it is not the complete path. For the path P1 to becomplete, we use the forward simulation from level L3 toL4. As mentioned in Definition 6, the paths P3 and P4 arecomplete.

Now, we present the algorithm for the path generationmethod in Algorithm 1.

Example 2 : We illustrate the path generation algorithmwith an example in Fig. 6. At first, we extract therequired parameters LS={L1, L2, L3, L4}, T S={010, 001}and consider a fault-free truth table as FaultF ree T able

for the nth P rime3 inc reversible circuit as shown inTable 1. As mentioned in the algorithm, we initialize the

Fig. 6 Illustration of pathgeneration of nth P rime3 inc

reversible circuit usingbacktracking

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variable L0 and Pk to empty values. Here, Pk provides theinformation of tracing a path between level L4 and L0,where L0 is the input level of a given circuit and storesthe test vectors which are generated by the derived pathPk . Initially, Lj=L1 and Lj−1=L0 and the variable j isincremented to 4 ( i.e., GC=4). We consider the test vector〈 0 1 0 〉 in T S and apply it to the first level L1. Usingthe backtracking method (called as BackT racing), the testvector 〈 0 1 0 〉 at level L1 extracts the test vector 〈 0 1 0 〉at level L0 with the help of FaultF ree T able. Therefore,level L0 is updated with the newly assigned test vector(010), which is generated by the path P1 and it is derivedfrom L1 to L0. Again, we consider the next test vector〈 0 0 1 〉 in T S and apply it to the first level L1. Using theBackT racing function, the test vector 〈 0 0 1 〉 extracts thesame test vector 〈 0 0 1 〉 at level L0 and produces the newpath P2, which is also derived from level L1 to L0. The nextiteration is level L2 and the test vector 〈 0 1 0 〉 extractsthe test vector 〈 0 1 0 〉 at level L1. In this case, the samepath P1 is considered from level L2 to L1 due to the sametest vector 〈 0 1 0 〉 being available in level L1. There is noneed to update the input level L0 if the same path exists inthe previous iteration. But, when we apply the test vector〈 0 0 1 〉 at levelL2, then new test vector 〈 0 1 1 〉 is generatedat level L1 with the help of FaultF ree T able. Thus, thenew path P3 is created, which is derived from L2 to L0 andwe update the input level L0 with the test vector 〈 0 1 1 〉.It is observed that the level L0 is only updated when a newpath is formed, otherwise we create the path between thecurrent pair of levels. The same process is continued up tolevel L4. In Fig. 6, we have observed that four test vectorsviz. 〈 0 1 0 〉, 〈 0 0 1 〉, 〈 0 1 1 〉 and 〈 1 0 0 〉 are availableat the input level L0 and these test vectors are generated bythe paths P1, P2, P3, and P4, respectively. Moreover, the testvector 〈 0 1 0 〉 and 〈 0 0 1 〉 at level L4 produce the completepaths P3 and P4, which are shown in Fig. 6.

4.3 Complete Test Set GenerationMethod

In this section, the proposed method is described to generatea complete test set for detecting all bridging faults in a givenreversible circuit. The path generation method provides thelevel-wise interaction with the help of backtracking, and allthe paths that are associated with the test vectors at theirrespective levels. The path-level expression is introduced forselecting a path Pk such that it covers the maximum numberof bridging faults.

The validity of a path Pk in between the levels impliesthat there must exist derivation paths in a reversible circuitfrom the initial level L0 to the last level LGC and vice versa.Derivation paths can be expressed as an expression, termedas a path-level expression. A path-level expression consistsof test vectors and metacharacters are used to describe some

of the characteristics. Table 2 shows the metacharactersconsidered in this work.

Definition 7 The path level expression PKE relatedto path Pk is defined as Pk

∑0i=GC [T Vi(Li).{1} ∨

T Vj (Li–Lj ).{|i − j + 1|}], where j < i, T Vj (Li–Lj )

indicates the presence of same test vector from level Li tolevel Lj .

The path-level expressions are used for selecting theproper paths such that selected paths provide the completetest set for detecting all the bridging faults. Let us considerthe complete paths generated by the path-level expressionPlE and PmE , which are described as follows:

PlE :Pl[T Vi(LGC–Lk).{|GC − k + 1|} + T Vj (Lk−1–L0).{|k|}]PmE :Pm[T Vj (LGC–Lk+1).{|GC − k|} + T Vi(Lk).{1} + T Vi

(Lk−1–L0).{|k|}]

Consider two complete paths from the level LGC , whichare defined by the path-level expression PlE and PmE .These two path-level expressions are matched to validate thederived path.

The path-level expression stores the unique test vectoralong with the corresponding level and repetition of thetest vector to the previous levels. The path-level expressionsPlE and PmE have GC + 1 levels, where LGC is theprimary output level, and L0 is the input level. The path-level expression PlE indicates that the test vector T Vi ispresent from LGC to Lk and the number of occurrences ofT Vi is |GC − k + 1|. Also, the test vector T Vj is associatedwith level Lk−1 to L0 and number of occurrence is |k|.Similarly, in path-level expression PmE , the test vector T Vj

is associated with levels LGC to Lk+1, the test vector T Vi isassociated with levelLk and the test vector T Vi is associatedwith level Lk−1 to L0. The occurrences of the test vectorsT Vj , T Vi and T Vi are |GC − k|, 1 and |k|, respectively.If the path-level expression PlE is matched with PmE , it isobserved that the test vector T Vi is the complement form atlevel Lk . To cover all the faults at level Lk , we need another

Table 2 Meta characters and interpretation

Meta Character Meaning

Pk[ ] Set of test vectors, char-acters and metacharac-ters used in path Pk

{n} Repetition of n times

(Lj ) Specify the particular level Lj

(Lk – Lj ) Specify the level Lk to Lj

. Specify the connection

+ Proceed to the previous level

450 J Electron Test (2019) 35:441–457

path-level expression which is generated from the samelevel Lk . Suppose, the new form of path-level expressionPPE is derived from level Lk , which is expressed as:

PPE : PP [T Vj (Lk–L1).{|k|} + T Vi(L0).{1}]A complete path is required to cover all the levels of a

given reversible circuit according to Property 1 and Property2. The path-level expression PPE does not generate acomplete path because the process starts from level Lk . Forextracting the complete path from the path-level expressionPPE , the test vector T Vj (Lk) traces the test vector ofprimary output level LGC with forward simulation. Thefollowing path-level expression is generated from the path-level expression PPE which eventually gives a completepath.

P ′PE :P ′

P [T Vi(LGC).{1} + T Vk(LGC−1–Lk+1).

{|GC − k − 1|} + T Vj (Lk–L1).{|k|} + T Vi(L0).{1}]This path-level expression P ′

PE is matched with the path-level expression PlE and PmE . The path-level expressionP ′

PE assures that the test vector T Vj is present at levelLk . If we consider the path-level expression PmE and P ′

PE ,then generated test vectors T Vi and T Vi fail to detectthe faults at the initial level L0. Similarly, the path-levelexpression PlE and P ′

PE generate the test vector T Vi andT Vi respectively, which are unable to detect the faults atlevel LGC . Therefore, for detecting all the faults at eachlevel along with satisfying Property 1 and Property 2,all the three path-level expressions are needed. The testvectors T Vj , T Vi , and T Vi are produced by the path-levelexpressions PlE , PmE and P ′

PE , respectively at the inputlevel L0.

Selection and matching of the path-level expressions arebased on the following properties:

Property 1 Each level present in the level set LS producesthe unique test vectors which are generated by the derivationpath. As a result, the same test vector cannot be present atthe same level.

Proof According to the controllability property ofreversibility, any test vector of a particular level generatesthe unique test vector at the previous level using backtrack-ing. The derivation path for each level is the interactionbetween the two test vectors of their corresponding levels.Therefore, each derivation path generates an unique testvector at a given level. Hence, same test vector cannotoccur at the same level, which is generated by the derivationpath.

Property 2 The generated test vectors for each level mustbe capable of producing opposite logic values to capture all

possible bridging faults. So, some test vectors must exist torepresent all the bridging faults in each level.

Proof The local test patterns are applied for each levelin LS for extracting the test vector at the previous levelusing backtracking. These local test patterns are capablefor producing the opposite logic values for each level asdepicted in Fig. 5. Furthermore, the derived path is createdbased on these local test patterns which are applied foreach individual level in a given reversible circuit. Therefore,each level contains the local test patterns along with the testvectors which are generated by the derived paths. Hence,there exist some test vectors in each level which are capableof detecting all the bridging faults in a given reversiblecircuit.

Example 3 The complete test generation process isillustrated with an example. Consider the reversiblebenchmark circuit nth P rime3 inc as shown in Fig. 7.

Consider the complete paths which occur at level L4. Thefollowing path-level expressions express the complete path.

P4E :P4[010.(L4).{1}+110.(L3).{1}+111.(L2).{1}+101.(L1).{1} + 100.(L0).{1}]

P3E :P3[001.(L4–L2).{3} + 011.(L1–L0).{2}]

After matching the two expressions, it is observed thattest vectors 001 and 110 are complement to each otherat level L3 and as a result it is not possible to detectthe bridging faults at level L3. According to the proposed

Fig. 7 Demonstration of Complete Test Set generation ofnth P rime3 inc reversible circuit

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method, the other path at level L3 is considered as shown inFig. 7. The new path-level expression is

P1E :P1[010.(L3–L0).{4}]The backtracking process of the path-level expression

P1E starts at level L3. Therefore, the generated path by thepath-level expression P1E is not complete. For constructingthe complete path from the path-level expression P1E , themethod of the forward simulation at level L3 is used. Thecomplete path generated by the path-level expression P ′

1E is

P ′1E :P ′

1[110.(L4).{1} + 010.(L3–L0).{4}]After matching the path-level expressions P3E and P ′

1E ,it is observed that the generated test vector 001 and 110 arenot capable of detecting the bridging faults at levelL4 due tocomplement form of each other. For detecting the bridgingfaults at level L4, we need the path-level expressions P4E

and P3E . If we consider the path-level expressions P4E

and P ′1E then the generated test vectors 010 and 111 are

not able to detect the faults at level L2, because the testvector 111 does not consist of opposite logic values. So, itis essential to consider all the path-level expressions P4E ,P3E and P ′

1E to generate the test vectors 100, 011 and010 at L0, respectively. Moreover, by matching these pathexpressions Property 1 and Property 2 are satisfied. Hence,the test set {100, 011, 010} is the complete test set to detectall the bridging faults at each level in the nth P rime3 inc

reversible circuit.

As explained in Example 3, three test vectors are suffi-cient for detecting all the bridging faults in nth P rime3 inc

benchmark circuit according to the proposed path-levelexpression method. As an empirical study, we consider allthe possible test sets with size 2 and apply to the circuit. Thetotal number of single bridging faults for nth P rime3 inc

benchmark circuit is 15. The fault coverage for all possi-ble test sets with two test vectors is reported in Table 3. Itis observed that two test vectors are not sufficient to detectall the possible bridging faults. As per path-level expressionmethod, 3 test vectors are generated which are sufficientto detect all the single bridging faults in nth P rime3 inc

reversible circuit.

Lemma 1 Proposed path-level expression method gener-ates the minimal complete test set for detecting the bridgingfaults with 100% fault coverage in a given NCT or GT basedreversible circuit.

Proof Let us assume that the path-level expression PlE

and PmE are capable of generating the complete minimaltest set at the initial level L0 in a given reversible circuit.Hence, as per our proposed method, these expressionsgenerate the complete path from level LGC and are also

Table 3 Fault coverage table for nth P rime3 inc reversible circuitwith 2 test vectors

Test set size=2 Faults covered % faults coverage

(000, 001) 08 53.33

(000, 010) 10 66.66

(000, 011) 10 66.66

(000, 100) 08 53.33

(000, 101) 10 66.66

(000, 110) 08 53.33

(000, 111) 06 40.00

(001, 010) 14 93.33

(001, 011) 14 93.33

(001, 100) 13 86.66

(001, 101) 13 86.66

(001, 110) 12 80.00

(001, 111) 12 80.00

(010, 011) 14 93.33

(010, 100) 13 86.66

(010, 101) 14 93.33

(010, 110) 12 80.00

(010, 111) 13 86.66

(011, 100) 13 86.66

(011, 101) 14 93.33

(011, 110) 14 93.33

(011, 111) 12 80.00

(100, 101) 14 93.33

(100, 110) 12 80.00

(100, 111) 12 80.00

(101, 110) 14 93.33

(101, 111) 12 80.00

(110, 111) 12 80.00

able to satisfy Property 1 and Property 2. For proving thislemma, a counter example is considered. Let us considerthat the path-level expressions PlE and PmE are not capableof generating the complete minimal test set. Then, wehave to choose another path, which is expressed by thepath-level expression PPE at level LGC−1 to the initiallevel L0. Therefore, path-level expression PPE is unableto generate the complete path. To construct the completepath, we have derived the path-level expression PPE fromlevel LGC−1 to level LGC using the forward simulation.The newly derived path-level expression is named as P ′

PE .Now, we have three path-level expressions as PlE , PmE ,and P ′

PE . Each pair of path-level expressions are matchedto validate the derived path. The matching of the path-level expressions appear based on the occurrence of thegenerated path. Suppose we consider that all the pairs ofpath-level expressions satisfy both the properties and, each

452 J Electron Test (2019) 35:441–457

Table 4 Complete test set for detection of bridging faults with Simulation CPU time (sec) for the benchmark Circuits

Benchmark circuit No. of inputs No. of outputs No. of gates No. of total detectable faults No. of test vectors CPU time (sec)

N + C m + g SIBF+MIBF+SIRBF+MIRBF

Peres 9 3 + 0 3 + 0 2 24 2 0.034

Fredkin 6 3 + 0 3 + 0 3 32 2 0.166

nth prime3 3 + 0 3 + 0 4 40 3 0.203

Miller 11 3 + 0 3 + 0 5 48 2 0.213

ham3d1 3 + 0 3 + 0 5 48 2 0.234

3 17 13 3 + 0 3 + 0 6 56 2 0.257

3 17 14 3 + 0 3 + 0 6 56 3 0.283

Toffoli double 4 4 + 0 4 + 0 2 66 2 0.302

rd32d1 3 + 1 2 + 2 4 110 3 1.223

mini-alu 167 4 + 0 2 + 2 6 154 2 2.167

decode24 v0 38 2 + 2 4 + 0 6 154 4 3.834

mod10 171 4 + 0 4 + 0 10 242 4 4.157

hwb4-11-23 4 + 0 4 + 0 11 264 4 4.333

mspk hwb4 12 4 + 0 4 + 0 12 286 4 4.712

4 49d3 4 + 0 4 + 0 12 286 4 4.017

mspk 4 49 13 4 + 0 4 + 0 13 308 4 3.477

mspk 4b15g 1 4 + 0 4 + 0 15 352 4 5.197

4 49d1 4 + 0 4 + 0 16 374 4 5.364

hwb4d1 4 + 0 4 + 0 17 396 3 5.002

4gt11 84 4 + 1 1 + 4 3 208 3 2.839

4gt11-v1 85 4 + 1 1 + 4 4 260 4 4.156

xor5d1 5 + 0 1 + 4 4 260 3 3.821

mod5d4 4 + 1 1 + 4 5 312 3 4.528

alu-v0 26 5 + 0 4 + 1 6 364 4 6.001

mod5d1 63 5 + 0 5 + 0 7 416 4 6.226

4mod7-v1 96 4 + 1 3 + 2 7 416 4 6.283

mod5d1 4 + 1 1 + 4 8 468 3 6.828

mod5d2 4 + 1 1 + 4 9 520 4 7.139

hwb5d1 5 + 0 5 + 0 55 2912 5 22.410

graycode6 47 6 + 0 6 + 0 5 684 3 6.936

ex3 229 5 + 1 6 + 0 7 912 4 8.036

mod5adder 128 6 + 0 6 + 0 15 1824 4 16.822

hwb6d3 6 + 0 6 + 0 42 4902 4 28.023

hw6d1 6 + 0 6 + 0 126 14478 7 61.044

ham7d1 7 + 0 7 + 0 23 5760 4 66.331

hwb7d1 7 + 0 7 + 0 289 69600 3 43.871

hwb8 614 8 + 0 8 + 0 614 303810 7 403.412

hwb9 1544 9 + 0 9 + 0 1544 780610 7 867.318

rd73d2 7 + 3 7 + 3 20 42546 4 215.971

6symd2 6 + 4 1 + 9 20 42546 3 314.909

hwb10-3631 10 + 0 10 + 0 3631 7358432 7 1197.964

hwb11-9314 11 + 0 11 + 0 9314 37930680 7 2960.651

cycle10 2d1 12 + 0 12 + 0 19 163320 5 128.948

9symd2 9 + 3 1 + 11 28 236814 5 717.283

rd84d1 8 + 7 4 + 11 28 1899616 4 2351.187

ham15d1 15 + 0 15 + 0 132 8712032 8 4547.57

cycle17 3d1 20 + 0 20 + 0 48 102758390 8 7002.426

mod1024adder1 20 + 0 20 + 0 55 117438160 7 9161.228

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path-level expression is capable of generating the completepath. It means that any pair of path-level expressions iscapable of generating the complete test set at the initial levelL0. However, according to the proposed method, path-levelexpressions PlE and PmE are matched before the matchingof the path-level expressions PlE and P ′

PE or PmE and P ′PE .

Hence, the path-level expressions PlE and PmE are capableof generating the complete minimal test set. So, there is acontradiction.

4.4 Complexity of the ProposedMethod

Consider an N-input reversible circuit with a totalnumber of levels L + 1. According to the local testpattern generation method explained, we need O(�log2 N�)number of test vectors at the initial level. Therefore, thetotal number of test vectors required for L + 1 levels isO((L + 1)�log2 N�). According to the proposed method,the maximum number of paths that is generated usingbacktracking is �log2 N� and the complexity for generatingthese paths is O(�log2 N�(L+1)�log2 N�). To evaluate thetest vectors at each level, we generates the path expressionfor (L + 1) levels. For constructing the path expression, thetime complexity is O(L + 1) because each path expressiondirectly depends on the levels in the path. Hence, thetotal time complexity of our proposed method is O((L +1)2(�log2 N�)2).

5 Experimental Results and Discussions

The algorithm of the proposed complete test set generationmethod has been implemented and applied to variousbenchmark circuits based on NCT and GT gate libraries[16] and [34]. A tool is implemented to generate thecomplete test set for fault models such as Stuck-at faultmodel, Bridging fault model, Missing gate fault model andCrosspoint fault model. The experimental result in Table 4shows the total number of test vectors that is required forthe detection of bridging faults (SIBF , MIBF , SIRBF ,and MIRBF ) with the CPU simulation time in seconds.The first five columns in Table 4 provide the benchmarkcircuit name, number of inputs: N + C (inputs + constantinputs), number of outputs: m + g (outputs + garbageoutputs), number of gates, and the total number of bridgingfaults, respectively. Column 6 and 7 in Table 4 present thetotal number of test vectors that are required for detectingall possible bridging faults and the CPU simulation time,respectively.

Based on the experimental results as shown in Table 4,the analysis is provided for three parameter such as (i)CPU time vs. Input lines, (ii) CPU time vs. Gate countand (iii) CPU time vs. Number of faults. It is observed

that the proposed method can handle reasonably largecircuits.

(i) CPU time vs. Input lines: In Fig. 8, it is observedthat the variation in CPU time against the input linesis similar for some of the benchmark circuits, whichis noticed by the persistent straight line in the initialpart of the graph. For the circuits considered in thispart of the graph, the number of gates and the numberof total faults in those circuits are less and so theCPU time taken is also significantly low. Considerthe circuits hwb8 614, hwb9 1544, and rd73d2 withnumber of input lines 8, 9 and 10, respectively. Itis observed that the circuit hwb9 1544 with 9-inputlines takes significantly higher time (867.318secs) togenerate the test vectors with reference to the circuitshwb8 614 (403.412secs) and rd73d2 (215.971secs).For the circuit hwb9 1544, the number of gates and anumber of faults are relatively large, and so the time istaken to generate the test vectors is also more. Similarrelationships between the number of gates and thenumber of faults of the circuits are observed wherethere is a transient response in the graph of Fig. 8(e.g., hwb10-3631, hwb11-9314 and cycle10 2d1).

(ii) CPU time vs. Gate count: In Fig. 9, we can perceivethat there is a random increase and decrease inCPU time in the graph. High escalations can beobserved for benchmark circuits cycle17 3d1 andmod1024adder1 with gate counts of 48 and 55, andtake 7002.426 secs and 9161.228 secs CPU timeto generate the test vector, respectively. The circuithwb11-9314 has 9314 gates, but the CPU time takento generate the test vectors is 2960.651secs. The gatecount of the circuit mod1024adder1 is 55, whichtakes more CPU time to generate the test vectors

Fig. 8 Plot of CPU time vs. Number of input lines

454 J Electron Test (2019) 35:441–457

Fig. 9 Plot of CPU time vs. Number of gates

compared to the circuit hwb11-9314 with 9314 gates.This happens due to more number of inputs inmod1024adder1 (20 input lines) than hwb11-9314(11 input lines).Therefore, the impact of the numberof input lines is more significant than the number ofgates present in the circuit.

(iii) CPU time vs. Number of faults: In Fig. 10, weobserve that there is an escalation in CPU time withthe increase in the total number of faults for mostof the benchmark circuits, but there is a reductionof CPU time for some circuits with more numberof faults. Consider the circuit hwb11-9314 with totalnumber of faults 37930680 and the circuit ham15d1

Fig. 10 Plot of CPU time vs. Number of Faults

with total number of faults 8712032. The CPU timerequired to generate the test vectors are 2960.651secsand 4547.57secs, respectively. Though the number offaults in ham15d1 is less than the number of faultsin hwb11-9314, but to generate the test vectors, thecircuit ham15d1 takes more CPU time compared tothe circuit hwb11-9314. This effect is due to thepresence of more number of input lines in ham15d1(15 input lines) compared to hwb11-9314 (11 inputlines). It is also observed that ham15d1 has lessnumber of gates (132 gates) than hwb11-9314 (9314gates). Similar pattern is also observed in the graphfor the circuit hwb10-3631 (10 inputs, 3631 gates,7358432 faults, 1197.964 secs CPU time) and rd84d1(15 inputs, 28 gates, 1899616 faults, 2351.187 CPUtime).

Our experimental results are compared with [3, 25,29] and these are reported in Table 5, Tables 6 and 7,respectively. The authors in [25] proposed an optimal testset generation method for all possible SIBF and SIRBF. Inthe proposed work, the SIBF, MIBF, SIRBF and MIRBFare considered. The total number of faults detected by theproposed scheme for AND and OR bridging faults are givenin Column 4 in the tables. It is observed that the requirednumber of test vectors to detect all the bridging faults bythe proposed scheme is less compared to other techniques[3, 25, 29] for all the benchmark circuits. The maximumreduction of test vector size is 81.82% for Ham7 benchmarkreversible circuit when compared to technique proposed in[25]. The authors in [3] used the DFT method for generatingthe test vectors to detect the SIRBF and single stuck-atfaults. In contrast, our proposed method generates the testvectors for detecting SIRBF with additional bridging faultssuch as SIBF, MIBF, andMIRBF. It is found that the numberof test vectors required in case of our proposed methodis almost similar to [3], however, with no extra circuitoverhead due to the non-adaptation of DFT method. Thecomparison of the proposed work with [3] is reported inTable 6. The work in [29] specifically targets generatingthe universal test set for both SIBF and MIBF and alsofor input stuck-at faults based on the shift operation onunitary matrix. It is found that the number of test vectorsgenerated by our proposed method is equal when comparedto the method of Sarkar et al. [29], but the proposedmethod covers more types of fault, which is clearly visiblein Table 7.

Finally, according to the experimental results reported, itis evident that the number of test vectors generated by ourproposed method is less or equal to the existing methods.Moreover, the proposed method covers more types of faultas compared to existing methods and achieves 100% faultcoverage.

J Electron Test (2019) 35:441–457 455

Table 5 Comparison of the complete test set with [25]

Benchmarkcircuit

No. ofInputs/Outputs

No. of totaldetectable faults[25]

No. of total detectablefaults [Proposed]

No. of testvectors [25]

No. of test vectors[Proposed]

SIBF+SIRBF

Ham3\Design#1 3/3 18 48 3 2

Graycode6 6/6 90 684 9 3

4 49\design#3 4/4 78 286 5 4

Ham7\Design#1 7/7 504 5760 22 4

rd32\design#1 4/4 30 110 6 3

Xor\Design#1 5/5 50 260 8 3

Table 6 Comparison of the complete test set with [3]

Benchmarkcircuit

No. ofinputs/Gates

No. of totaldetectable faults [3]

No. of total detectablefaults [Proposed]

No. of testvectors [3]

No. of test Vectors[Proposed]

SIBF+SIRBF

ham3tc 3/5 24 48 4 2

graycode6 6/5 126 684 5 4

hwb4-11-23 4/11 120 264 4 4

4 49-12-32 4/12 130 286 4 4

mod5adder-15 6/15 336 1824 5 4

ham7tc 7/23 672 5760 5 4

cycle17-3 20/48 10290 102758390 7 8

mod1024adder 20/55 11760 117438160 7 7

ham15tc1 15/132 15960 8712032 6 8

hwb9-1544 9/1544 69525 780610 6 7

hwb10-3631 10/3631 199760 7358432 6 7

hwb11-9314 11/9314 614790 614790 6 6

Table 7 Comparison of the complete test set with [29]

Benchmarkcircuit

No. ofinputs/Outputs

No. of totaldetectable faults[29]

No. of total detectablefaults [Proposed]

No. of testvectors [29]

No. of test vec-tors [Proposed]

SIBF+MIBF

6symd2 6/1 90 42456 3 3

9symd2 9/1 352 236814 5 5

hwb7 7/7 152 69600 4 3

hwb8 8/8 238 303810 4 7

hwb6 6/6 90 21736 3 3

rd73 7/3 152 42546 4 4

rd84 8/4 238 1899616 4 4

ham7 7/7 152 5760 4 4

ham15 15/15 1848 8712032 8 8

mod1024adder 20/20 4598 117438160 10 7

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6 Conclusion

In this paper, we discussed a scheme for minimal completetest set generation to detect all the bridging faults whichincludes SIBF, SIRBF, MIBF, and MIRBF in reversiblecircuits. The concept of path-level expression is introducedin the work to generate the complete test set. The path-level expression has the ability to capture the level-wiseinformation on a given reversible circuit. After collecting allthe path-level expression, a matching process is applied tocollect the required paths only which are used to generatethe test set. It is also established that the generated testis the minimal one. The reversible circuits that consist ofNCT and GT gate libraries are used in this work to carryout the experiments. The generated test set is capable for100% fault coverage, which is shown with experimentalresults.

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Mousum Handique is a PhD student in the Dept. of CSE, IITGuwahati. His research interests include VLSI Testing and Reversiblecomputing. He has published 4 research papers. He is the member ofIEEE.

Santosh Biswas received the B.E. degree from the National Instituteof Technology Durgapur in the year 2001. He has completed hisMS from the Department of Electrical Engineering, Indian Instituteof Technology Kharagpur with highest institute CGPA in the year2004. He obtained his PhD from the Department of Computer Scienceand Engineering, Indian Institute of Technology Kharagpur in theyear 2008. He joined the Department of Computer Science andEngineering, Indian Institute of Technology Guwahati in 2009 andis currently an Associate Professor. At present he in on deputationas HoD EECS dept. in IIT Bhilai. He has been involved in severalResearch Projects sponsored by Industry and Government agencies.He is engaged with academic as well as industry-sponsored researchrelated to VLSI Testing and Design for Testability. His researchinterests include VLSI Testing and Design for Testability, FaultTolerance, Network Security, Discrete-event systems and EmbeddedSystems. He has published about 150 research papers. He is a memberof IEEE.

Jantindra Kumar Deka received the B.E. degree in Electronics fromthe Motilal Nehru National Institute of Technology Allahabad in theyear 1988. He has completed his M.Tech in Computer Science andInformation Technology from the Department of Computer Scienceand Engineering, Indian Institute of Technology Kharagpur in theyear 1993. He obtained his PhD from the Department of ComputerScience and Engineering, Indian Institute of Technology Kharagpur inthe year 2001. He then joined the Department of Computer Scienceand Engineering, Indian Institute of Technology Guwahati and iscurrently a Professor. He is engaged with academic as well as industry-sponsored research related to VLSI Testing and Design for Testability.His research interests include Formal Modeling and Verification, CADfor VLSI and Embedded Systems (Design, Testing and Verification),Data Mining. He has published more than 40 research papers. He is amember of IEEE.