design and evaluation of an ultra-low power low...
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Design and Evaluation of an Ultra-Low Power
Low Noise Amplifier LNA
Master thesis performed in
Electronic Devices by
Saeed Yasami
Report number: LiTH-ISY-EX--09/4257--SE
Linköping Date: August 2009
Department of Electrical Engineering
Linköping University, SE-581 83 Linköping, Sweden
Linköping 2009
Master’s Thesis
Design and Evaluation of an Ultra-Low Power
Low Noise Amplifier LNA
Saeed Yasami
LiTH-ISY-EX--09/4257--SE
Supervisor: Professor Atila Alvandpour
Linköpings Universitet
Examiner: Professor Atila Alvandpour
Linköpings Universitet
Linköping, August 2009
Presentation Date 2009-08-24
Publishing Date (Electronic version) 2009-08-24
Department and Division
Department of Electrical Engineering Division of electronic devises
URL, Electronic Version http://www.ep.liu.se
Publication Title
Design and Evaluation of an Ultra-Low Power Low Noise Amplifier LNA Author(s) Saeed Yasami
Abstract
This master thesis deals with the study of ultra low power Low Noise Amplifier (LNA) for use in
medical implant device. Usually, low power consumption is required for a long battery lifetime and
longer operation. The target technology is 90nm CMOS process.
First basic principle of LNA is discussed. Then based on a literature review of LNA design, the
proposed LNA is presented in sub-threshold region which reduce power consumption through scaling
the supply voltage and through scaling current.
The circuit implementation and simulations is presented to testify the performance of LNA .Besides the
power consumption simulated under the typical supply voltage (1V), it is also measured under some
other low supply voltages (down to 0.5V) to investigate the minimum power consumption and the
minimum noise figure. Evaluation results show that at a supply voltage of 1V the LNA performs a total
power consumption of 20mW and a noise of 1dB. Proper performance is achieved with a current of
down to 200uA and supply voltage of down to 0.45V, and a total power consumption of 200uW.
Keywords CMOS, Low Noise Amplifier (LNA), Ultra Low Power, Sub-threshold region, Radio
Frequency Integrated Circuit (RFIC)
Language √ English Other (specify below)
Number of Pages 50
Type of Publication Licentiate thesis √ Degree thesis
Thesis C-level Thesis D-level
Report
Other (specify below)
ISBN (Licentiate thesis)
ISRN: LiTH-ISY-EX—09/4257--SE
Title of series (Licentiate thesis)
Series number/ISSN (Licentiate thesis)
Abstract
Abstract
This master thesis deals with the study of ultra low power Low Noise Amplifier
(LNA) for use in medical implant device. Usually, low power consumption is required
for a long battery lifetime and longer operation. The target technology is 90nm CMOS
process.
First basic principle of LNA is discussed. Then based on a literature review of LNA
design, the proposed LNA is presented in sub-threshold region which reduce power
consumption through scaling the supply voltage and through scaling current.
The circuit implementation and simulations is presented to testify the performance of
LNA .Besides the power consumption simulated under the typical supply voltage
(1V), it is also measured under some other low supply voltages (down to 0.5V) to
investigate the minimum power consumption and the minimum noise figure.
Evaluation results show that at a supply voltage of 1V the LNA performs a total
power consumption of 20mW and a noise of 1dB. Proper performance is achieved
with a current of down to 200uA and supply voltage of down to 0.45V, and a total
power consumption of 200uW.
Keywords: CMOS, Low Noise Amplifier (LNA), Ultra Low Power,
Subthreshold region, Radio Frequency Integrated Circuit (RFIC)
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Acknowledgement
This thesis couldn’t have been completed without the help of many people. First of
all, I would like to thank to my supervisor to Professor Atila Alvandpour for offering
me this opportunity and giving me valuable guidance and encouragement throughout
this work.
I would like to thank to Mr. Rashad M.Ramzan for his suggestions and his help. I
would like to thank all Electronic Devices staff for their kind help and open
discussions. I can’t imagine where I would be without their help.
Finally, this thesis is dedicated to my parents who supported me unconditionally
throughout of my life.
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IV
Abbreviations
CMOS Complementary Metal-Oxide Semiconductor
F Noise Factor
Gm Tran-conductance
IC Integrated Circuit
IF Intermediate Frequency
IIP3 Third Order Intercept Point
IMD Implantable Medical Devices
K Stability Factor
L Gate Length,
LNA Low Noise Amplifier
MICS Medical Implant Communication Service
NF Noise Figure
NMOS N Type CMOS Transistor
P1dB 1 dB Compression Point
Q Quality Factor
RF Radio Frequency
RFIC Radio Frequency Integrated Circuit
W Gate Width
Wt Cut-off Frequency
Content
1.Introduction 1
1.1Thesis Organization 1
1.2 Background 2
1.3.Objective 4
2. Basic principle of CMOS LNA 6 2.1 Introduction of LNA 6
2.2 Introduction of CMOS LNA 7
2.3 High frequency Effect in CMOS 8
2.3.1 Physical Origin 8
2.3.2 First Order Model 8
2.4 Noise Sources in CMOS 9
2.4.1 Drain Current Noise in CMOS 10
2.4.2 Induced Gate Noise in CMOS 11
2.4.3 Flicker Noise in CMOS 11
2.4.4 Other Noise Sources in CMOS 12
2.5 Introduction to Two-Port Networks of LNA 13
2.5.1 Representation of Two-Port Networks 14
2.6 Scattering Parameters of LNA 14
2.7 Gain of Two-Port Networks 17
2.7.1 Maximum Power Transfer Theorem 17
2.7.2 Different Gain Expressions 18
2.8 Noise Theory in Two-Port network 19
2.8.1 Noise Figure Definitions 19
2.8.2 Noise Figure Calculations for Cascaded Blocks 21
2.9 Linearity in Two-Port network 22
2.9.1 Harmonic Distortion 22
2.9.2 1dB Compression Point 23
2.9.3 Intermodulation distortion 23
2.9.4 3rd Order Intercept Point 24
2.10 Stability in Two-Port network 25
3. Implementation and Performance Evaluation of CMOS LNA 27
3.1 Impedance Matching in LNA Design 27
3.2 LNA Input Matching Topologies28
3.2.1 Resistive matching 28
3.2.2 Shunt-Series Feedback 29
3.2.3 Common-Gate input matching 30
3.2.4 CMOS Inductive Source Degeneration LNA 32
3.3 Inductive Source Degeneration CMOS LNA 32
3.4 Design Procedure 37
3.5 Simulation Result 38
3.5.1 S21 and S12 of LNA 38
3.5.2 S11 and S22 of LNA39
3.5.3 NF and NFmin using S-parameter 40
3.5.4 Voltage Gain 41
3.5.51dB Compression Point 42
3.5.6 Input Referred IIP3 43
3.5.7 Harmonic Distortion 44
3.5.8 GT and GP 45
3.5.9. Stern stability factor and Delta of LNA 46
3.6 comparisons with previous works 47
4. Conclusion and Future Work 48
4.1 Conclusion 48
4.2 Future Work 49
5. Reference 50
1
Chapter 1
Introduction
1.1 Thesis Organization
The first chapter of this thesis discusses the introduction and need of low power LNA.
The rest chapters are organized as follows:
Chapter 2 illustrates the performance metrics of LNA and two port network theory of
RF (LNA) circuits.
Chapter 3 discusses different LNA architectures and a comparison of the popular LNA
architectures in terms of power, noise and gain is presented. Then implementation of
the proposed LNA in transistor level and the LNA performance by cadence
simulations and subsequent calculations is presented.
Chapter 4 draws conclusions on this work and gives a short discussion on future
works.
Chapter 5 is dedicated the references for interested reader.
2
1.2 Background
Implantable medical devices (IMD) can be used in diagnosis, therapy and rehabilitation
of many diseases, including deafness, heart diseases, and neurological disorders and
many more. Nowadays with the development of healthcare technology there is huge
demand for more-advanced healthcare treatments, including wireless implant devices that
can deliver ongoing and cost-effective monitoring of a patient's condition. Pacemakers,
Neuro-stimulators, Implantable Insulin Pumps, Bladder Control Devices, implantable
physiological monitors are some examples. New ultra-low-power radio-frequency
integrated circuit (RFIC) technologies help the development of innovative medical tools
such as implanted devices that wirelessly transmit patient health data. Communication
links between base stations and medical implants are critical to the operation of IMDs
and enables to reprogram therapy and obtain useful diagnostic information [1].
Low-power systems with Low-frequency inductive links (1970s) have been the most
prevalent method of communication which usually operates in the tens to hundreds of
kilohertz range, with data rates of 1–30 Kb/sec. They can accommodate a small coiled
antenna in the IMD and have proven to be robust and suitably reliable but antenna size
and power limitations in implants result in a very low magnetic field strength which
result in short range and often require the external programmer to have contact with the
skin of the patient directly over the implant. To overcome these operating-range and low-
data-rate limitations, new ultra-low-power RF technologies are being developed that
operate at much higher frequencies, such as in the 433 and 915 MHz industrial, scientific,
and medical (ISM) bands. RF technology can now offer low power, reduced external
component count, and higher levels of integration, which will open new markets for
medical device manufacturers. The allocation of this band supports the use of longer-
range (typically 2 m), high-speed wireless links and overcomes the limitations of dated
inductive systems and facilitates the development of next-generation medical devices
supporting improved patient healthcare. This is especially important, as escalating
medical costs drive the growth of remote health monitoring.
Signal propagation characteristics in the human body, compatibility with the incumbent
users of the band and its international availability make ISM band well suited for such
remote monitoring.
These implantable devices mainly consist of two parts: an integrated circuit, which has a
high capability for communication and signal processing and a battery, which keeps the
3
integrated circuit to work for many years. Typically the battery gives an operation of only
for more than 10 years .Therefore low power consumption is critical for medical implant
devices to allow longer battery lifetime.
Figure 1.1 shows an example of a pacemaker system which contains a pacemaker
device and pacing leads.
Figure 1.1An implanted pacemaker communicates patient health and operating data
to a base station and transmits information to a physician's remote office
A simplified block diagram of the pacemaker system is shown in Figure 1.2. Within
the whole system, there are four main blocks: 1) Input Block: a sensing system,
followed by filtering amplifiers and analog-to-digital converter, 2) Logic Block:
digital programmable logic, control and algorithms for therapy, 3) Output Block:
high voltage multiplier and output pulse generator, and 4) Housekeeping Block:
battery power management, voltage and current reference generators [1].
4
Figure 1.2.Highly integrated ultra-low-power transceiver.
As it can bee seen from the figure above, LNA in the input block is to amplify signal,
and as one of critical component it is also important to design LNA with ultra-low-
power for medical implant devices.
1.3 Objective
In this work, the primary goal is to minimize the power consumption of LNA into the
range of micro-watt. Using ST’s 90nm CMOS process technology, the proposed
LNA is designed at transistor level. Based on the simulation, the LNA achieves a
total power consumption of 420 µ W with a 1V power supply. By decreasing the
supply voltage and decreasing current, the LNA can still have satisfactory result a
supply voltage of 0.5V, achieving power total consumption of 200u µ W.
5
6
.
Chapter 2
Basic Principles of
CMOS LNA
2.1 Introduction of LNA
This chapter focuses on the basic principles of Low-noise amplifier LNA. Some general
considerations and specifications of LNA such as noise, gain and power are presented.
LNA serves as the first amplification block in a RF receiver whose main function is to
provide enough gain to overcome the noise of the following stages (for example, in the
mixer or IF amplifier). While providing enough gain and adding as little noise as possible,
an LNA should offer a large dynamic range and accommodate large signals without
distortion. Usually a passive band-select filter and image-reject filter precedes and
succeeds the LNA. Since the transfer characteristics of these filters are quite sensitive to
the quality of the termination, it is also extremely important that LNA present good
matching to its input and output.
7
Figure2.1 Basic signal receiver system
Figure 2.1 shows an LNA which is used in a heterodyne receiver. While band-select filter
before the LNA suppress the out-of-band interferers, the image reject filter after the LNA
rejects the image which is 2 IFω away from the desired band.
2.2 Introduction of CMOS LNA Even though CMOS technology has been used in digital circuits and low-frequency
analog circuits for many years, it is only within the early nineties that CMOS is capable
of being used in RF circuits. With the backend transceivers already being implemented in
CMOS, it is attractive to use CMOS in front-end in order to integrate the whole receiver
on a single chip.
Next section introduces concepts and design considerations associated with CMOS LNA
and the basic properties of them will be investigated. Starting from high frequency effects
and noises analysis in CMOS transistors in section 2.3 and 2.4, we will the go through a
classic two-port network theory of LNA in section 2.5.Finally, Scattering parameter, gain,
linearity ,stability will be discussed in following sections.
8
2.3 High Frequency Effect in CMOS An important issue that needs to be taken into account in the design of narrowband
CMOS LNA is the high frequency effect. This effect worsens the noise and gain
performance of the LNA as will be presented later in this section.
2.3.1 Physical Origin
In order to understand the high frequency effect, first consider a model of MOS
transistors operating at low frequencies (ω << ωΤ) as shown in figure 2.2.
Figure 2.2 Simple small signal models for MOS at low frequencies
This model works well at low frequencies because speed of the build-up of the inversion
layer channel charge is fast enough and is also relative to the frequency of the signal
applied to a terminal. However, at radio frequency this assumption is not valid due to the
finite channel conductance which limits the speed of the build-up of the inversion layer.
Hence, the channel requires more time to get into equilibrium with the source and drain
voltages. This high frequency effect is also called non-quasi static effect.
2.3.2 First Order Model
Figure 2.3 shows a small signal high frequency equivalent circuit model proposed in [6]
for a CMOS transistor which operate in the strong inversion region.
9
Figure 2.3 first order small signal model including high frequency effect.
This model uses an extra resistance in series with the gate to source capacitance for high
frequency effect. This resistance is known as the non quasi static gate resistance, and it is
the effective resistance seen by the gate to source capacitance which is given by equation:
m
NQSgg
r5
1, = (2.1)
Note that the above equation is derived for long channel transistors without considering
short-channel effects. As mentioned previously, this effect occurs when a high frequency
signal is applied to the input gate. Hence it can be neglected for most practical transistor
when the frequency is low enough such that the imaginary part of the impedance due
to gsC is much greater than the real part.
However, when an inductor is placed in series with gsC which is the case in LNA
designing, the impedance of the inductor will cancel out the impedance of the capacitor at
the resonance frequency. Therefore, the input impedance in this case is determined only
by rg,NQS.
2.4 Noise Sources in CMOS Before embarking on analysis of how to design for low noise amplifier, the origins of
noise must be presented. This section discusses the most important noise source in MOS
transistors such as drain current noise, induced gate noise, and flicker noise and
etc[3],[5].
10
2.4.1 Drain Current Noise in CMOS
In addition to the extrinsic physical resistances in a MOSFET transistor (rg, rs, rd), the
channel material is also resistive and therefore contributes thermal noise known as Drain
Current Noise [6]. This noise can be presented by a current noise connecting from drain
to source in the small signal model of CMOS as shown in figure 2.4. The expression for
drain current noise can be expressed as:
fgkTi dnd ∆= 0
24 γ (2.2)
Where gd0 is the drain to source conductance at zero-bias Vds. The parameter γ holds a
value of unity at zero Vds and a value of 2/3 in saturation for long channel device.
However, in the short channel device the value of γ can be considerably higher depending
on bias condition, tpically 2 to 3 or even larger due to carrier heating by the large electric
field in short channel transistors.
Figure 2.4 Drain Current Noises and Induced Gate Noise
11
2.4.2 Induced Gate Noise in CMOS
In addition to drain current noise, the thermal agitation of channel charge result in
induced gate noise. This noise is caused by high frequency effect which discussed earlier
in this chapter. If the CMOS transistor is biased so that the channel is inverted, fluctuating
in the channel charge due to capacitive couples induce a noisy gate current. Although the
coupling effect is small and this noise can be ignored at low frequencies but it is not
negligible at very high frequencies. This noise is modeled as a current noise connecting
from gate to source in the small signal model of CMOS (see figure 2.4 and is given by
equation:
fgkTi gng ∆= δ42
(2.3)
Where
0
22
5 d
gs
gg
Cg
ω= (2.4)
The parameter δ is a gate noise coefficient and although for short channel transistor is
not accurately known yet, for long-channel devices is equal to 4/3 which is twice more
than γ. Therefore, this means that for γ around 2 to 3 for the short-channel transistor, δ
should be around 4 to 6 [4].Also note that the gate noise and the drain noise are related to
each other.
2.4.3 Flicker Noise in CMOS
Flicker noise is the other important noise source in MOS devices. This noise also can be
presented by a current noise connecting from drain to source in the small signal model of
CMOS as shown in figure 2.4 and is given by equation [4]:
fWLC
g
f
Ki
ox
m
nf ∆=2
2
2
(2.5)
Where K is a constant which is varied from technology to technology and Cox is the gate
oxide capacitance per unit area.
12
2.4.4 Other Noise Sources in CMOS
The distributed gate resistance of the MOS devices also results in the noise in low noise
amplifiers. This noise sources can be presented by a series resistance at the gate and the
noise power can be expressed by [4]:
g
f
gKTR
v4
2
=∆
(2.6)
Where
Ln
WRR
sq
g 23= (2.7)
Where gR is the gate resistance, W is total gate width, L is the gate length, sqR is the
sheet resistance of poly-silicon, and n is the number of fingers. By increasing the number
of fingers which is used to make a transistor, gate resistance noise source can be reduced.
The resistance of the substrate also generates thermal noise.
The resistance due to the lightly doped drain diffusion regions results in the noise and
expressed by equation:
W
RR LDS
drainsource =, (2.8)
where RLDS is the resistance of a unit width transistor. Note that even by proper layout this
resistance cannot be mitigated.
13
2.5 Introduction to Two-Port Networks of LNA
RF and analog circuit can be characterized in many ways. To simplify analysis and
explain important design criteria, it is useful to abstract circuit blocks into two-port
networks which preserve input-output behavior but discard detail of internal structure. In
this section property of two-port network theory is discussed. Parameters that are used to
characterize two-port networks such as gain, noise, linearity, and stability is presented.
These figures of metric are important in the design of low noise amplifiers [3], [4].
2.5.1 Two-Port Networks Representation A two-port network with four terminals and two ports is shown in figure 2.1 to define the
input and output of a circuit. Two terminals constitute a port if they satisfy the essential
requirement known as the port condition: the same current must enter and leave a port.
There are two variables (voltage and current) at each port. While one of this voltage or
current will be independent, the other one will dependent on the two-port network and the
independent variables.
At low frequencies, three most common representations are the impedance matrix (Z-
parameters) and the admittance matrix (Y-parameters) or a mixture of this two hybrid
matrix (h-parameters).
Figure 2.5 representation of a two-port network
=
2
1
2221
1211
2
1
I
I
ZZ
ZZ
V
V (2.9)
=
2
1
2221
1211
2
1
V
V
YY
YY
I
I (2.10)
At very low frequencies, Z parameters and Y parameters can be measured by applying
14
either a test current or test voltage to the input port and connecting either the output port
to short or open circuit. Therefore, they can be useful at low frequency.
However, voltages and currents are difficult to measure directly at microwave
frequencies. The Z matrix requires “opens,” and it is hard to create an ideal open due to
parasitic capacitance and radiation. Likewise, a Y matrix requires “shorts,” again ideal
shorts are impossible at high frequency due to the finite inductance. Hence, there is a
need to establish well-defined termination condition in order to find the network
description for Z, Y and two-port network. In addition, an active two-port network might
oscillate if one of its ports is short or open circuited. Therefore, a different representation
of the two-port network, scattering parameters or S-parameters, is needed at RF and
microwave frequencies. S-parameters are widely used to describe the property of
network and devices at RF and microwave frequency. They are the topic of the next
section.
2.6 Scattering Parameters
S parameters are equivalent to Z, Y of two ports popular in analog circuit theory.
However, S-parameters are different in a sense that they don’t use open or short circuit.
To characterize the circuit, they can be measured by matching the source and load
impedances to the reference impedance (termination are much easier at RF frequencies).
Figure 2.2 shows a diagram of an S-parameter representation of a two-port network
which is connected to the source through a lossless transmission line with characteristic
impedance Z0.
Figure 2.6 representation of a two-port network by S parameter
The basic idea behind S parameter representation is to measure the normalized incident
voltage wave ia entering the system at port i, in addition to the corresponding reflected
15
voltage wave ib leaving port i. The normalized incident and reflected voltage waves
ia and ib can be related to the terminal voltage and currents at port I and expressed by the
equations:
o
ioi
iZ
iZva
2
+= (2.11)
o
ioi
iZ
iZvb
2
−= (2.12)
where Zo is the reference impedance which is usually real and equal to 50 Ω. For the two
port network in figure 2.6, s-parameter in matrix can be shown by following equation:
=
2
1
2221
1211
2
1
a
a
SS
SS
b
b (2.13)
where S11, S12, S21, S22 are the scattering parameters which are measured across ports 1
and 2. By expanding the scattering matrix, the following equations can be derived:
021
1
11=
=aa
bS (2.14)
012
1
12=
=aa
bS (2.15)
021
2
21=
=aa
bS (2.16)
022
2
22=
=aa
bS (2.17)
If the output port properly terminated, S11 is interpreted as the ratio between the reflected
voltage wave and the incident voltage wave at port 1 that is reflection coefficient at input.
16
Likewise, definitions for the rest of the S parameters can be derived. Therefore s-
parameter related to familiar measurement such as gain, loss, reflection coefficient and
etc.
Note that the output or input impedance of the two-port network does not need to match
the characteristic impedance and if port load impedance matches the characteristic
impedance, port is properly terminated.
Although, s-parameters are inherently complex and linear quantity, usually they are
expressed in a log magnitude format and they are relatively easy to obtain at radio
frequency.
S-parameter can be transforms to h,Y, Z parameter and it is also important to realize that,
although S parameters associate with high frequency and wave propagation, the concept
can be valid for any frequency.
2.7 Gain of Two-Port Networks Although, in analog circuit design gain usually expresses in terms of voltage gain, in RF
and high frequency design it is often more helpful to express the gain of a two-port
network as power gain. In this section first the maximum power transfer theorem is
introduced and then a discussion of power gain is presented [4].
2.7.1 Maximum Power Transfer Theorem
In RF and microwave design often refer to a source and load as being “power matched.”
“Power match,” means that for a given source impedance, the load impedance is such that
the maximum available power is transferred to the load from the source.
17
Figure 2.7 Simple networks for maximum power transfer theorem
As shown in figure 2.7, the power delivered to the load is entirely due to RL, and can be
expressed by:
2
22
SL
SL
L
RL
L
ZZ
VR
R
VP
+== (2.18)
separating the real and imaginary parts of the impedances result in following equation:
22
22
)()( SLSL
SL
L
RL
LXXRR
VR
R
VP
+++== (2.19)
From above equation, it can be inferred that the power to the load is maximized when
)0( =+ SL XX and RL is equal to RS, or in other words, when ZL and ZS are complex
conjugates.
Note that the maximum amount of power the source which can be transferred to the load
is only half of the amount available power.
2.7.2 Different Gain Expressions
Consider the two-port network shown in figure 2.8, some useful gain expressions can be
defined in terms of the different reflection coefficients and the two-port network s-
parameters.
18
Figure 2.8 Reflection coefficients of two port network
The ratio between the reflected voltage waves from a port and the incident voltage wave
entering the port is the reflection coefficient, and can be expressed by equation:
o
o
ZZ
ZZ
+
−=Γ (2.20)
Power gains of two-port networks can be defined by equations [3]:
AVS
L
TP
PG = (2.21)
in
L
PP
PG = (2.22)
AVS
AVN
AP
PG = (2.23)
GT is probably the most meaningful gain metric, and is defined as the transducer power
gain which is the power delivered to the load (load mismatch) given the power available
from the source (source mismatch). GP is the power gain, and is the power delivered to
the load (load mismatch) from the power input to the network. GA is the available power
gain, and it represents the power available from the network (matched load) given the
power available from the source (source mismatch). From these above definitions, it is
worthwhile to notice that GT will always be less than or equal to GP, and GT will always
be less than or equal to GA. However, if the source and load are both conjugate matched
19
to the input and output impedance of the two-port network, then all the power gains will
be equal.
Using the definitions introduced in equations [3] the different gain expressions can be
derived where the different reflection coefficients are used. Note that if input and output
impedance are not known, then it is necessary to use the suitable and alternate
expressions for reflection coefficients in input and output.
2.8 Noise Theory in Two-Port Network Before embarking to analysis of noise, it is useful to first introduces the definition of the
noise factor and noise figure (noise figure is noise factor expressed in dB).
2.8.1 Noise Figure Definitions
The overall sensitivity is directly related to the noise figure of the receiver, which is
impacted by noise from individual blocks in the receiver as well as gain distribution of
the receiver chain. The noise figure is a measure of the SNR degradation and defined as a
ratio between the input SNR and the output SNR of the circuit.
out
in
SNR
SNRF = (2.24)
)log(10 FNF = (dB) (2.25)
Where F is called a noise factor and NF is the noise figure of the system. Noise figure is
usually calculated or measured by specifying a standard input noise level through the
source impedance and the noise temperature. The typical values in standard
communication systems are Rs=50Ω and T=293 K. For a circuit building block such as an
amplifier, the total noise figure can be derived in terms of added output noise and the gain
of the system. The amplifier with power gain G with the input signal power Pin and input
noise power Nin will have the output signal power GPin and output noise power
GNin+Namp,o. Therefore the noise figure of the amplifier can be calculated:
20
oampin
in
inin
NGN
GP
NPF
,
)/(
+
= (2.26)
in
iamp
in
oamp
N
N
GN
NF
,,11 +=+= (2.27)
For an ideal noiseless system which contributes no noise, the noise factor is equal to one.
For analysis of noise in two-port systems, first consider a noisy two-port network driven
by a noisy source as shown in figure 2.9a. The noise of the two-port network can be input
referred as a noise voltage and noise current as well as noiseless system form the
equivalent circuit as shown in figure 2.9b.
a)
b)
Figure 2.9 noises in two port network
21
2.8.2 Noise Figure Calculations for Cascaded Blocks
In the previous section, the definition of the noise figure for a single circuit block
discussed. In a receiver, however, the overall system noise figure that is resulted form
cascaded circuit blocks in the receiver chain which must be calculated. The cascaded
noise figure depends strongly on the noise figures of individual blocks in addition to gain
distribution of the receiver chain. If there are two blocks cascaded to each other, as shown
in figure2.10, and the matching is done properly, the total noise figure according to Friis
formula is then given by:
Figure 2.10 Cascaded blocks
1
21
)1(
G
FF
SNR
SNRF
out
in −+== (2.28)
where G1 and G2 are the power gains for each block in the given matching condition and
F1 and F2 are the noise figures for each block.
As can be seen from above equation the total noise figure of the cascaded blocks depends
on the noise figures of both stages and on the gain of the first stage. The noise
contribution of each successive stage is smaller and smaller. Therefore, every
communication system employs a low noise amplifier (LNA) at the front-end to relax the
noise requirements.
22
2.9 Linearity in two port network In the previous section, noise theory in two-port systems was presented. In this section,
another non-ideality, linearity, is discussed. Two port networks are assumed to be linear in
many analyses because the input signal is small enough such that the non-linear effects of
the two-port network can be neglected. In LNA design, however, linearity is an important
issue because the LNA even in the condition of large input signals must keep linear
operation [4].
2.9.1 Harmonic Distortion
Consider a memory less nonlinear system, then the output and input can be related by a
polynomial power series given by equation:
...3
3
2
210 +++= iii SaSaSaS (2.29)
where a1, a2, a3, are independent of input signal si (a1 is the small signal gain) and they
depend on bias, temperature and other factors. Therefore, if a sine wave drive is applied
to the input, as shown by equation
)cos()( 11 tStS i ω= (2.30)
then the output will be equal to:
[ ] [ ])cos(3)3cos(4
1)2cos(2
)cos()( 11
3
13
1
2
121110 tt
Sat
SatSatS ωωωω ++++= (2.31)
The first term in equation above is the linear and wanted term. The rest of the terms are
due to non-linearity. They result in harmonic distortion terms at 2ω1, 3ω1, … as well as a
DC shift, and depend on the sign of the third order term ,either gain compression or gain
expansion .
23
2.9.2 1 dB Compression Point
Gain compression or saturation occurs because eventually the output signal (voltage,
current, power) limits due to supply voltage or bias current. The 1 dB compression point
(P-1dB) is the input signal level that causes the small signal gain drop by 1 dB.
As it was mentioned previous section, the third order term in the power series depending
on its sign can either result in gain compression or gain expansion. If we assume that the
sign between a1 and a3 are different, then gain compression or saturation will occur, and
the 1dB compression point can be measured and expressed mathematically by equations:
dBSa
a1)
4
31log(20
2
1
1
3 −=+ (2.32)
and
11.03
4
3
11
a
aP dB =− (2.33)
2.9.3 Intermodulation distortion
Harmonic distortion was characterized in previous section as the result of non-linearity
due to a single sine wave input. If two sine waves with different frequency are applied to
the input of a nonlinear two port network, output exhibit 12 tones and a DC term as
shown in figure 2.11.This component which aren’t harmonic of input frequency are
known as intermodulation distortion.
Third-order intermodulation distortion are the interferer and product at (2ω1 ± ω2), and
(2ω2 ± ω1) which can appear in vicinity of ω1 and ω2 .In reality, these interfere (third-
order intermodulation distortion) are adjacent and alternative channel.
24
Figure 2.11 Output frequencies
2.9.4 3rd Order Intercept Point
The other measure of the amount of 3rd order non-linearity in a two-port network is the 3rd
order intercept point. Since the 3rd order non-linearity is proportional to the input signal
cubed, while the fundamental is increasing only linearly with input signal, there will be a
point at which the amplitudes of the fundamental and the 3rd intermodulation meet. The
input signal, S1, at which this occurs is defined as the input-referred 3rd order intercept
point (IIP3), and is equal to when IM3 equals 1. Solving for S1, the following equation for
IIP3 is obtained.
3
13
3
4
a
aIIP = (2.34)
For cascaded nonlinear stages like the one in figure 2.2, the overall IIP3 is affected by the
nonlinearity of each block and gain distribution. As shown in figure[2.5], the overall IIP3
is given by:
...11
2
3,3
2
2
2
1
2
2,3
2
1
2
1,3
2
,3
+++=IIP
GG
IIP
G
IIPIIP total
(2.35)
25
Where IIP3,k and Gk are the voltage IIP3 and voltage gain for the block k.In fact, the
LNA has little impact on the overall of the system, as is obvious from the equations
derived.
2.10 Stability in two port network
In addition to above parameter, two-port networks must not be susceptible to unwanted
oscillation. This means that in the presence of feedback path, two-port network may not
be stable for certain combination the source and load impedance. The stability condition
of a two port network can be defined in terms of S-parameter and the load and source
impedances. If the following equations hold, a two-port network is unconditionally
stable:
1<ΓS (2.36)
1<ΓL (2.37)
1<Γin (2.38)
1<Γout (2.39)
A metric that charactraize the stability of a two-port network is the Stern stability factor
K and defined as following equation:
2211
2
22
2
11
2
1
SS
SSK
∆+−−= (2.40)
where
21122211 SSSS −=∆ (2.41)
26
If K>1 and ∆ <1 unconditional stability is satisfied and it may not oscillate with any
combination of source and load impedance. However, a transistor can still be
conditionally stable with K < 1 and |∆| <1 [3].
From control theory we know that too large loop gain can prevent stable operation.
Therefore, a large value of 2112SS result in the stability factor k<1 and ∆ >1.
A common way to avoid instability is to limit reverse gain 12S by using neutralization
technique (AC coupling).The other common way as used in this design is to separate of
input and output by an extra (cascade) transistor.
.
27
Chapter 3
Implementation and
Performance Evaluations of CMOS LNA
3.1 Impedance Matching in LNA Design
Impedance matching is necessary in LNA design because the system performance can be
strongly affected by the quality of the termination path from the antenna to the amplifier
which usually go through a transmission line (either a cable or through PCB traces,
before reaching the LNA). If the LNA input is not matched, the impedance seen by the
antenna depends on the length of this transmission line which is not good situation
because it cannot predict how much power will reach the LNA. For Example, the
frequency response of the antenna filter that precedes the LNA will deviate from its
normal operation if there are reflections from the LNA back to the filter. Furthermore,
undesirable reflections from the LNA back to the antenna must also be avoided.
There is a subtle difference between impedance matching and power matching. The
condition for impedance matching occurs when the load impedance is equal to the
characteristic impedance. However, the condition for power matching occurs when the
load impedance is the complex conjugate of the characteristic impedance. When the
impedances are real, the conditions for power matching and impedance matching are the
same [4].
28
3.2 LNA Input Matching Topologies As mentioned in the previous section, impedance matching is very important in LNA
designs. In most cases, the source impedance of the LNA is 50Ω in a wireless system.
Since the input impedance of the MOS transistor is almost purely capacitive, providing a
good match to the source without degrading noise performance is a challenge. In this
section, we will investigate a number of circuit topologies that can be used for matching.
3.2.1 Resistive matching
Resistive matching is the most straightforward approach to achieve the broadband 50Ω
matching at the input. As shown in figure 3.1 the 50Ω-resistor (R1) is placed across the
input terminal of the LNA and hence providing a broadband input matching. However,
the resistor R1 adds its own thermal noise to the circuit while attenuates the incoming
signal by a factor of two before it reaches the gate of the transistor. These two effects
make an unacceptably high noise figure of the circuit [4, 5] and therefore it is not
practical in many applications.
In the most optimistic situation where ignoring all the MOSFET noise, the lower bound
of the noise factor is two. The noise figure due to the input termination resistor is
bounded as follow:
212
2
=+>s
eq
v
vF (3.1)
The termination adds at least 3 dB of noise figure which is totally intolerable in sub- dB
applications. However in other applications, resistive termination matching can be a
cheap and simple solution.
29
Figure 3.1 Resistive termination matching
3.2.2 Shunt-Series Feedback
The other method used for getting a good input matching is the shunt-series feedback
amplifier as shown in figure 3.2[4]. Unlike in the resistive termination matching, it does
not attenuate the signal by a noisy resistance before hitting the gate of the amplifying
device and hence the noise figure is expected to be much lower. However, the feedback
resistor continues to generate thermal noise of its own. These make the relatively high
noise figure, which is usually a few decibels higher than the optimal number.
30
Figure 3.2 Resistive termination matching
3.2.3 Common-Gate input matching
Common-gate configuration is another method for realizing a resistive input matching. A
common-gate transistor can match the impedance by choosing gm equal to 1/Rs. As can
be seen in the figure 3.3, the source terminal is used as an input terminal. Since the
impedance seeing from source of transistor is equal to 1/gm, by proper transistor sizing
and by adjusting the bias current of the circuit, desired input impedance can be achieved.
However due to lower gm, for a MOSFET transistor this requires a high current for Rs =
50 Ω which in turn result in high power consumption. Another drawback of common-
gate matching topology is that when source resistance is known, it will have constant gm.
31
Figure 3.3 Common-gate input matching
Because of broadband mg of the transistor, common-gate input matching technique can be
broadband matching. Since the impedance changes with gm of the transistor, we can
expect that the matching bandwidth is approximately equal to the tω of the device.
Ignoring gate and flicker noises and assuming a perfect match, we can express the lower
bound of the noise figure for the amplifier by:
do
m
g
gF
γ+≥ 1 (3.2)
Numerical value for the lower bound of nose figure for long-channel devices is about
2.2dB and for short channel devices is about 4.8dB [4].In addition ,as it was already
mentioned, common-gate matching consume more power due to higher value of bias
current.
32
3. 2.4 CMOS Inductive Source Degeneration LNA
Inductive source degeneration matching topology provides a perfect match without
adding any noise to the system ( resistive matching) or giving any restrictions on the
device mg (common-gate matching)[4].
Since this topology was used in this work, it will be discussed in detail in next section.
3. 3 CMOS Inductive Source Degeneration LNA
As it was mentioned already this matching topology techniques provides a perfect match
without adding any noise to the system or giving any restrictions on the devicemg . It uses
an inductor as a source degeneration device and has another inductor connecting to the
gate as shown in figure 3.4.
Figure 3.4 CMOS Inductive Source Degeneration LNA
33
Using the small signal analysis and neglecting NOQgr , as well as the gdc of M1, the
impedance looking through the gate inductor can be expressed as:
sTCjsgin LLLjZgs
ωω ω +++= 1)( (3.3)
where
gs
m
TC
g=ω (3.4)
Note that the maximum operation frequency or cut-off frequency tω is the frequency
at which the FET no longer amplifies the input signal.
At the resonance frequency where the inductor impedance and the capacitor impedance
are canceled out, the input impedance is then just the last term equation (3.3). If the tuned
frequency oω and the NOQgr , are taken into consideration, the total tuned impedance will
be :
NQSgsTin rLZ ,0 )( += ωω (3.5)
where
gssg
oCLL )(
1
+=ω (3.6)
Since all the inductors are reactive, they do not add any noise into the circuit. In fact, the
LC resonating mechanism improves noise and gain performance of the amplifier. Starting
from the equivalent model of the input matching (figure 3.5), the quality factor of the
circuit given by:
eq
gs
R
CQ
ω= (3.7)
At the resonance, the voltage amplitude across the gsC is Q times more than the voltage
across the input terminal from the source given matched condition. This effectively
increases the transconductance of the input transistor by a factor of Q.
34
mm QgG = (3.8)
Figure 3.5 CMOS Inductive Source Degeneration LNA
In typical narrow-band matching, this factor is usually around 3 to 5. Assuming that the
matching network is lossless, this effect helps to reduce the input-referred added noise by
a factor of Q as well as increasing the voltage gain of the circuit by the same factor.
Therefore, this topology is preferred in most narrow-band applications. One major
limitation of this topology is that the matching is narrow-band. As can directly derive, it
is a series RLC network with finite Q. However, since most wireless receivers are
narrow-band, this is usually not a big concern.
35
3.4 Design Procedure Having established the backgrounds in LNA design, now we will turn our focus into the
circuit implementation and simulations. Figure 3.6 shows a circuit that is commonly used
in the design of CMOS low noise amplifiers. This circuit uses the input stage described
previously to provide an input match and current gain at the resonant frequency. A
cascode is added to the input stage to reduce the interaction between the input tank and
output tank and to reduce the reverse gain from output to the input. This reverse gain
reduction effectively increases the stability of the amplifier. In addition, the cascode
reduces the effect of the gdC of M1 by presenting a low impedance node at the drain of
M1 hence the miller-effect of gdC is mitigated. The output inductor, LL , is designed to
resonate at oω with the node capacitance at the output. The input and output tank can be
aligned to provide a narrowband gain, but can also be offset from each other to provide a
broader and flatter frequency response. Traditionally, CMOS LNAs have been designed with MOS transistors operating in strong
inversion since current MOS transistor noise models predict that the noise in subthreshold
regime increases significantly with decreasing drain current. The weak inversion region
seems to have a worse noise performance when compared to the strong inversion region.
Thus the noise figure of a subthreshold CMOS LNA is expected to be worse than the
usual CMOS LNA.
However, unlike common belief, the minimum noise figure of advanced deep sub-micron
MOS transistors in subthreshold regime remains constant. Therefore, the noise figure of
the amplifier with CMOS transistors biased in subthreshold does not degrade drastically
as DC power dissipation is reduced. Also note that Philips MOS11 model [8] predicts
almost a zero Fmin in subthreshold region. In addition, the gain to DC power
consumption ratio of LNAs in subthreshold regime is higher than that of saturation, since
in subthreshold regime, drain current has an exponential dependence to the gate-source
voltage. By increasing the width of the transistors operating in subthreshold, the high gain
can still be maintained, while DC power consumption is substantially reduced.
36
Figure 3.6 CMOS Inductive Source Degeneration LNA
A deep sub-micron MOS device operating in subthreshold inversion region can provide
sufficient transconductance. In this design, transconductance is increased by using with
larger width and minimum length devices. The effect of the capacitances associated with
such devices of large widths is reduced by using on-chip tuning networks so that adequate
transconductance is obtained at 900 MHz. A high impedance load, obtained by parallel
resonance of the load inductor with the total output node capacitance at the operating
frequency.
The 600 µ m/100nm NMOS devices labeled M1 and M2 are biased in weak region .With
threshold voltage thV equal to 0.45V and supply voltage DDV reduced to about 0.5V ,M1
has a transconductance of 19.3 mS at 220 µ A. The bias point and devices size are
selected to obtain sufficient transconductance at minimal associated capacitances. The
37
source degeneration inductor sL and the inductor gL provide input matching 50 ohm, and
provides good linearity and high reverse-isolation, which improve with the amplifier
stability. Inductor LL is used as a high impedance resonant load. As alreadymentioned,
the subtheshould region also has a worse noise performance when compared to the strong
inversion region. Thus the noise figure of a subthreshold CMOS LNA is expected to be
worse than the usual CMOS LNA. This effect is partially mitigated by having a voltage
gain in the passive input matching network .Finally, circuits operating at very low bias
currents are expected to have poor linearity. In next section the simulation results from
cadence is presented.
38
3.5 Simulation Result Based on the above discussion, the simulation result from cadence is presented.
3.5.1 S21 and S12 of LNA
Figure 3.7 S21 and S12 of LNA
The SP and Noise analyses can be used for small-signal and linear noise analyses, where
the circuits are linearized around the DC operating point. To characterize the circuit, s-
parameter can be measured by matching the source and load impedances to the reference
impedance oZ .
S21 is the ratio between the reflected voltage wave at output and the incident voltage
wave at input which can be interpreted as transmission coefficient or gain .The value of
6 dB for S21 is acceptable in low power LNA design. In addition, S21 is the
transmission coefficient or reverse gain which should be zero.
39
3.5.2 S11 and S22 of LNA
Figure 3.8 S11 and S22 of LNA
If the output port properly terminated, S11 is interpreted as the ratio between the
reflected voltage wave and the incident voltage wave at port 1 which is reflection
coefficient at input. Likewise, S22 is the reflection coefficient at output.
Note that the Z-parameters Z11 and Z22 can also be measured which might help in the
input and output impedance matching of the LNA design.
From the equation, S11 or input matching can be improved by changing the source
degeneration inductor ( sL ).
40
3.5.3 NF and NFmin using S-parameter
Figure 3.9 NF and NFmin using S-parameter
The noise factor is a measure of the SNR degradation and defined as a ratio between the
input and the output SNR of the circuit (SNR degradation).For an ideal noiseless system
the noise factor is equal to one and in this design the noise figure of 1.8 dB in
subthreshould region was achieved.
Note that capacitor can be added in parallel with the LL to make the gain and NF
response more selective and more narrow.
41
3.5.4 Voltage Gain
Figure 3.10 Voltage Gain
The main goal of this project was to reduce power consumption. Although for this
purpose, the LNA circuit was biased in subthreshold region but by increasing the gm,
the LNA achieved 18 dB of voltage gain.
In this design tranconductance gm was increased by choosing proper sizing of
transistors (using transistor with large width and minimum length).
42
3.5.5 1dB Compression Point
Figure 3.11 1dB Compression Point
Gain compression or saturation occurs because eventually the output signal (voltage,
current, power) limits due to supply voltage or bias current.
The 1 dB compression point (P-1dB) is the input signal level that causes the small signal
gain drop by 1 dB.
43
3.5.6 Input Referred IIP3
Figure 3.12 Input Referred IIP3
A two-tone test is used to measure an IP3 curve where the two input tones are 1ω and
2ω .Since the first-order components grow linearly and third-order components grow
cubically, they eventually intercept as the input power level increases as shown in
Fig3.12. The IP3 is defined as the cross point of the power for the 1st order tones, ω1
and ω2, and the power for the 3rd order tones, 2 1ω - 2ω and 2 2ω - 1ω , on the load
side.
Although the IIP3 is inversely proportional to the gain at the first stage (LNA) but total
overall IIP3 is decided by Mixer and the following stage not by LNA performance.
44
3.5.7 Harmonic Distortion
Figure 3.13 Harmonic Distortion
Output of nonlinear system (LNA) relates to input by a polynomial power series which
depend on bias, temperature and other factors. If a sine wave is applied to the input, then
the output will contain linear and wanted term and due to non-linearity, harmonic
distortion terms at 2ω1… DC shift and either gain compression or gain expansion.
Harmonic distortion is defined as the ratio of the power of the fundamental signal and the
sum of the power at the harmonics.
45
3.5.8 GT and GP
Figure 3.14 GT and GP
GT is the most meaningful gain metric is transducer power gain which is the power
delivered to the load (load mismatch) given the power available from the source (source
mismatch).GP is the power gain, and is the power delivered to the load (load mismatch)
from the power input to the network .)The power gain GP is close to the transducer gain
GT and it means that the input matching network is properly designed( S11 is close to
zero).
Note that the source and load are both conjugate matched to the input and output
impedance of LNA; all the power gains will be equal.
46
3.5.9 Stern stability factor and Delta of LNA
Figure 3.15 Stern stability factor and Delta of LNA
The stability condition can be defined in terms of S-parameter and the load and source
impedances by the Small Signal Stern stability factor K and ∆ .There curve is plotted
with respect to frequency sweep as shown in Fig 3.15.
If K>1 and ∆ <1 the LNA is unconditional stable may not oscillate with any combination
of source and load impedance. However, a transistor can still be conditionally stable with
K < 1 and |∆| <1 [3].
From control theory, too large loop gain 12S can prevent stable operation. Reverse gain
12S can be reduced by using neutralization technique (AC coupling) by separating of
input and output by an extra (cascade) transistor.
47
3.6 comparisons with previous works
In this section we compare the proposed LNA design with other published works.
F
[GHz]
Vdd
[V]
Idd
[mA]
Pdc
[mW
]
Gain
[dB]
NF
[dB
]
P1dB [dB]
IIP3
[dBm]
This LNA 0.9 0.5 0.22 0.26 6.1 1.7 -11.0 -9.0
Pre
vio
us
LN
A s
[8]2008RFIC_Mohammadi
[9] 2005RFIC_Wang
[10] 2005RFIC_Hsieh
[11] 2005ITMTT_Chiu
[12]2004RFIC_Mohammadi
[13]2004IMWCL_Ohsato
[14] 2004VLSI_Linten 5.50
[15] 2003IMTT_Zencir 0.44
[16] 2001JSSC_Gramegna
3
0.96
5.0
3.6
5.80
1.60
5.40
0.44
4.95
0.6
1.2
0.6
-
1.8
1.5
0.6
2.5
-
0.67
0.6
1.5
-
-
5.0
-
-
-
0.40
0.72
0.90
3.60
4.50
7.50
1.00
12.50
4.95
9.1
13
9.2
8.0
16.7
10.8
9.2
17.5
10.0
4.0
4.0
4.5
3.3
1.4
4.2
3.6
2.9
1.2
-25
-
-27.0
-8.3
-
3.7
-15.8
-13.7
-
-11
-10.2
-15.0
0.4
-2.6
1.2
-7.3
-1.0
-3.0
As it can be seen, this LNA achieved very low power consumption and very low noise
figure while still it has satisfactory gain and linearity.
48
49
Chapter 4
Conclusion and Future Work
4.1 Conclusion
In this project, an ultra low power LNA is designed in transistor level and it achieves a
very low power with good performance. Different topologies of LNA are studied and
compared. To minimize power, this LNA is biased in subthreshold region. It achieves 200
uW power consumption in 90nm CMOS process with 17 dB of voltage gain and a noise
figure of 1.7 dB.
From this work, many conclusions about low power RF integrated circuits design can be
made. It was shown that RF circuit in subthreshold region can be implemented to save
power while it achieves high gain with good noise figure. Another conclusion which can
be made is that advancements in CMOS technology both theoretically and practically
improve the gain and noise figure of the LNA.
However, the quality of on-chip passives, and parasitic capacitances and resistances from
the board, pads, and layout makes the realization difficult. Furthermore, the small device
sizes of the transistors in low power, deep sub-micron technology designs make
integration of passives, specifically inductors increasingly difficult.
50
4.2 Future Work
The improvement in technology has given designers a chance to design with increased
gain and reduced noise figure .However; there is much work to be done in the area of low
power, deep sub-micron CMOS LNA design. Based on the thesis presented above, there
are certain areas to improve:
i. As it was stated before, reducing parasitic is absolutely necessary in order to achieve
good performance. One way to reduce parasitic is through good layout. In addition since
most of the area in chip is taken by the inductors, if the inductors can be implemented in
such way that they do not take much area, or if a high effective inductance can be made,
it would reduce both the chip area and cost significantly.
ii. Furthermore, it is necessary to lower the interaction between the input and output
signal lines. Too much interaction between these lines can cause positive feedback
between the input and output, which in turn would make the LNA to oscillate. Therefore,
the input and output signal lines should be placed a safe distance apart from one another
to reduce the amount of coupling.
iii. Another possible future work is to look for new ways of enhancing the linearity of the
LNA.
iv. While this work is implemented in transistor level, it can be continued further to layout
implementation and perform post-layout simulation. Finally, a real chip can be
manufactured and it is worth to verifying the LNA by chip measurement.
51
Chapter 5
Reference
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[2] P. Gray, P. Hurst, S. Lewis, R. Meyer. Analysis and Design of Analog Integrated
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[3] G. Gonzalez. Microwave Transistor Amplifiers: Analysis and Design, 2nd Edition.
Prentice Hall, Upper Saddle River, New Jersey, 1996
[4] T. Lee. , The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge
University Press, Cambridge, UK, 1998
[5] B. Razavi. RF Microelectronics. Prentice-Hall, Upper Saddle River, New Jersey
[6]Y. Tsividis. , Operation and Modeling of the MOS Transistor. McGraw-Hill, Boston,
1998
[7] D. Shaeffer, T. Lee. “A 1.5 V, 1.5 GHz CMOS low noise amplifier,” IEEE Journal of
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[8] “A 3GHz Subthreshold CMOS Low Noise Amplifier” Hanil Lee and Saeed
Mohammadi
[9] S.B.T. Wang, et al., “A Sub-mW 960-MHz Ultra-Wideband CMOS LNA,” IEEE
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[10] H.H. Hsieh, et al., “A CMOS 5-GHz Micro-Power LNA,” IEEE RFIC Symp. Dig.,
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[12]B. Mohammadi, et al., “5.8 GHz CMOS LNA for WLAN applications,” IEEE RFIC
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[13] K. Ohsato, et al., “Internally Matched, Ultralow DC Power Consumption CMOS
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52
[14] D. Linten, et al., “Low-power 5 GHz LNA and VCO in 90 nm RF CMOS,” IEEE
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[15]E. Zencir, et al., “A low-power 435-MHz SOI CMOS LNA and mixer,” MTT-S Dig.,
pp. 555-558, 2003.
[16]G. Gramegna, et al., “A Sub-1-dB NF 2.3-kV ESD Protected 900-MHz CMOS
LNA,” IEEE J. Solid-State Circuits, vol. 36, pp. 1010-1017, July. 2001.