The LTC6950 improves SNR performance and solves clocking problems in high end data converter applications. The LTC6950 integrates a low phase noise integer-N synthesizer along with an ultralow jitter clock distribution output section to produce the low jitter signals essential to clocking data converters with high SNR levels. Besides minimizing jitter, the LTC6950 introduces EZSyncTM synchronization, a simple synchronization method that guarantees repeatable edge-synchronized outputs from one chip or multiple chips.

Features n Additive Jitter: 18fsRMS (12kHz to 20MHz) n EZSync Multichip Clock Edge Synchronization n Full PLL Core with Lock Indicator n 226dBc/Hz Normalized In-Band Phase Noise Floor n 274dBc/Hz Normalized 1/f Phase Noise n 1.4GHz Maximum VCO Input Frequency n Four Independent, Low Noise 1.4GHz LVPECL Outputs n One LVDS/CMOS Configurable Output n Five Independently Programmable Dividers n Five Independently Programmable VCO Clock Cycle Delays

1.4GHz Clean Clocking Solution with 18fsRMS Jitter (12kHz to 20MHz Bandwidth)

Offset Frequency (Hz)10M100 100k 1M10k1k

Abso

lute

Pha

se N

oise

(dBc

/Hz)

90

100

110

120

140

160

130

150

170

180

DIV = 4, fOUT = 250MHz

DIV = 16,fOUT = 62.5MHz

DIV = 40, fOUT = 25MHz

DIV = 1, fOUT = 1GHz

fPFD = 10MHz, fVCO = 1GHz

LTC6950 Closed-Loop Phase Noise

Ultralow Jitter Clock Generation and Distribution

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and EZSync and ClockWizard are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

EZSync Synchronization Simplifies the Generation of Repeatable Edge-Synchronized Outputs from One Chip or Multiple Chips

ClockWizard GUI Streamlines the Design and Simulation Processes

EZSync Enabled: Repeatable Rising-Edge Aligned Outputs of the LTC6950s Clock Dividers

With EZSync

EZSync Disabled: Random Phase Relationship Between the Outputs of the LTC6950s Clock Dividers

Advantages n Find PLL Parameters Quickly n Show PLL Frequency Response and Stability n Simulate Output Phase Noise and Jitter n Simulate Output Clock Phase Relationships

Based on EZSync Settings n Read and Write All Device Registers n Configure Using a Block Diagram

Programming Interface n Troubleshoot Common Setup Problems n Import and Export VCO, Reference and

Output Noise Data

Includes Time Domain Simulation

www.linear.com/clockwizard

1114

www.linear.com/6950 n 1-800-4-LINEAR