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Data Concentrator Board Implementation Concept

Rev 2 Update

Tom O’BannonUniversity of Maryland

7/16/2013—Updated on 7/19/2013

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Objectives

• These charts are not intended to imply any decisions.

• The goal here is to stimulate some dialog:– Ensure understanding of key requirements– Offer some general conceptual talking points of

the UT electronics implementation details

Operating Environment for Data Concentrator Electronics1

• Physical Environment – Ambient temperature: 20 ± 2°C– Ambient pressure: Normal Atmospheric– Ambient relative humidity: 40% (typ)– Radiation: 10 Krad

• 10-year accumulated exposure• Includes a 2x radiation safety factor

– Magnetic Field: 2,500 Gauss• Electrical Stresses

– 1000V (ie ±500 VDC) worse case detector bias potentially routed thru detector electronics assemblies

1 Per ‘Mechanical Requirements Document for the LHCb UT Upgrade Tracker” Rev 5/3/2013---WIP

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UT Physical Location Definitions

Physical Configuration: 8 Edge Interfaces x2 for Flex Tails to Data Concentrator Boards (x2 facilitates mechanical right-left separation)

Station 0, Layer AStation 0, Layer B

Station 1, Layer AStation 1, Layer B

UT Detector is electrically divided between top and bottom

UT Detector is split apart Left-from-right for maintenance access

4.5 cm

4.5 cm27 cm

1539 mm

1349

.4 m

m

Quadrant: Lower-Left

Quadrant: Lower-Right

Quadrant: Upper-Left

Quadrant: Upper-Right

(Lower Balcony Area)

(Upper Balcony Area)

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UT ASIC Access via Flextails1:Station 0: UTaX and UTaU

Station 0, Layer A, Upper= 496Station 0, Layer B, Upper= 496

Station 0, Layer A, Lower= 496Station 0, Layer B, Lower= 496

Station 0 has 1984 FE ASICs

1 This analysis based upon JC Wang presentation on 6/17/13

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UT ASIC Access via Flextails1:Station 1: UTbX and UTbU

Station 1, Layer A, Upper= 552Station 1, Layer B, Upper= 552

Station 1 has 2208 FE ASICs

Station 1, Layer A, Lower= 552Station 1, Layer B, Lower= 552

1 This analysis based upon JC Wang presentation on 6/17/13

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UT ASIC E-Link Distribution1:Station 0: UTaX and UTaU

1 This analysis based upon JC Wang presentation on 6/17/13

Station 0 has 2754 E-Links

Per Quadrant via 8 Flex Tails: 56 Hybrids ~ 350 E-Links

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UT ASIC E-Link Distribution1:Station 1: UTbV and UTbX

1 This analysis based upon JC Wang presentation on 6/17/13

Station 1 has 3254 E-Links

Per Quadrant via 9 Flex Tails: 63 Hybrids ~ 410 E-Links

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UT Data Interface Summary

1984 FE ASICs 2754 E-Links

Per Quadrant via 8 Flex Tails: 56 Hybrids ~ 345 E-Links ~ 35 GBTx’s

Per Quadrant via 9 Flex Tails: 63 Hybrids ~ 407 E-Links ~ 41 GBTx’s

276 GBTx’s

Station 0

2208 FE ASICs 3254 E-Links 326 GBTx’s

Station 1

4,192 FE ASICs 6,008 E-Links 608 GBTx’s

UT Total

952 Hybrids Raw Data Rate1

1,945.6 Gbps1 ( ie without data link overhead)

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Initial Electronics Concept-Annotated

GBTX-Master

DCB

DC-DC Power

Backplane

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Board-Level System Partition Options

• Assume standard EDAC (80 bits/frame) for GBTx operation• Total of 6008 Data E-Links (initial estimate only)

– Requires 601 GBTx’s1 dedicated for data transmission• Example Partitions:

– 12 GBTXs per board requires 51 DCBs– 8 GBTXs per board requires 75 DCBs

• What are the mechanical interface options along the left and right of the top and bottom detector plane edges?– Option: one backplane per detector plane quadrant

• Yields 16 smaller backplanes• Facilitates right-left mechanical split• Would be helpful if the 4 quadrants of each detector plane are made

symmetrical1 Note--System board-level partitioning will increase this quantity slightly

Some More Questions• Environment, Health, and status sensors?

– Type, quantity, update rates• Failsafes and interlock approach?• FE ASIC control interfaces via GBT-SCA:

– Interface port type? • I2C, JTAG, parallel port, SPI

– Data update rates? – Number of FE ASICs per GBT-SCA?– Initial prototype effort/support?

• DC-DC power distribution and regulation– FE ASICS– DCBs– Control Board

• Test Equipment plan?• Any dedicated handshake signal interfaces required between FE ASICs and

GBTs?– Data Valid / tx Rdy / rx_Rdy

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Digital Control Interface Signal Details/Options

• GBT-SCA—Control via one 80 Mbps E-Port– SPI (Serial Peripheral Interface)

• Serial Clock• Serial Data out• Serial Data in• 1 select line per slave

– I2C (Inter-Integrated Circuit)• Serial clock• Serial Data (bidir)• Signals are open drain to allow multiple bus masters

– JTAG– Memory interface– Parallel Port– Interrupts

• GBTx (Master)– 32 ports available at 80 Mbps– Provides FE ASIC TFC interface– E-Ports (AKA E-Links)

• Data In (to GBTx) • Data Out (from GBTx)• Clock Out (from GBTx)

Preferred Choice

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GBT-SCA Analog Interface Signal Details1

• 12-bit ADC– Input range: GND < Vin < 1 V– Max. conversion rate ≈ 3.5 KHz

• 32 Multiplexed Input channels– 31 general user input channels– 1 channel dedicated to on-chip temperature

sensor

1 Per Dec 15, 2011 Kostas.Kloukinas@cern.ch summary charts

Need to identify sensor specifics and any associated signal conditioning circuitry requirements to accommodate the GBT-SCA defined analog interface.

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DCBFE ASIC Interconnect Concept…

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DC Power Conversion, Regulation, and Filtering

Split the FE ASIC and DCBs DC power rails– What are the preferred distributed DC power rail voltages

• Input = 9V (11.5V at counting room)?• Backplane rails: ____?• GBTx=1.5V, FE ASIC= ___?, VL= 2.5V

– Select a standard (ie w/ CERN Heritage) rad-tolerant LDO to facilitate local power regulation and switching noise filtering

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Board Function Summary• GBTx-Master

– Bi-direction control interface via GBTx and versatile link ASICs– FPGA-Based Local Manager allows for local support functions

• DC-DC converter power segmented control (isolation/sequencing)• switch mode frequency synchronization/coordination• Autonomous failsafes and interlocks to protect hardware

– Local low drop out regulators• Data Concentrator Board

– E-link to GBTx to VL– Local low drop out regulators

• DC-DC Converter Board– High voltage EMI filtering + local isolation switch controls– Low voltage DC-DC conversion + EMI filtering– Low drop out regulators for FE ASICS

• Backplane– Fully Passive– EMI filtering for EMI isolation and suppression– Interconnect signal routing to match flex tail E-Links to DCBs

Initial concepts and functional placeholders to be refined by on-going system definition development as well as cost and schedule constraints

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An Alternate ‘Back Burner’ Approach

• Alternate prototype approach using intermediate FPGAs between FE ASICs and GBTx.– Flexibility since it can be remotely

re-programmed– Potential GBT SERDES alternate via

SF2 SOC effort if GBTs not readily available

– Potential to reduce risks by accommodating unexpected ‘design features’ between FE ASICs and GBTs

Above excerpt from CMS ngCCM (Terry Shaw)

Potentially useful in the initial prototype detector slice proof-of-concept build

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Near Term Path Forward

• Discuss support needs for prototype development

• Continue system partition efforts– Signal tabulations at all interfaces– Power rollups– Estimate board areas– Define mechanical interfaces