cyclone v soc fpga development kit board · cyclone v soc fpga development kit board 1. project...

40
8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 E E D D C C B B A A DESCRIPTION REV DATE PAGES PAGE DESCRIPTION 2 NOTES: Title, Notes, Block Diagram, Rev. History 1 3 4 7 8 Cyclone V GX SoC Bank 7 9 Cyclone V GX SoC Bank 8 10 11 12 13 14 15 16 PLL 17 JTAG 18 19 20 21 RLDRAM II CIO 22 23 24 25 5 6 Display Port (x4) 1172 Parts, 88 Library Parts, 1330 Nets, 6643 Pins A1 09/27/2012 All INITIAL REVISION A RELEASE FPGA Package Top Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing Schematic Drawing PCB Film Bill of Materials Schematic Design Files Functional Specification PCB Layout Guidelines Assembly Rework PCI Express Edge Connector Cyclone V GX SoC Bank 4,5,6 Cyclone V GX SoC Bank 3 Cyclone V GX SoC Transceiver Banks 2. 100-0321003-A1 110-0321003-A1 120-0321003-A1 130-0321003-A1 140-0321003-A1 150-0321003-A1 160-0321003-A1 170-0321003-A1 180-0321003-A1 210-0321003-A1 220-0321003-A1 320-0321003-A1 On-Board USB Blaster II 26 27 28 29 PAGE DESCRIPTION 30 Power 5 - Linear Regulator Power 7 - Cyclone V GX SoC Power Flash 5M2210 System Controller User I/O (LEDs, Buttons, Switches, LCD) Power 2 - 0.90V SDI TX Cable Driver & SMB 31 32 33 Power 1 - DC Input, 12V, 3.3V Cyclone V GX SoC Clocks Cyclone V GX SoC Configuration DDR3 - Part 1 of 2 Ethernet PHY & RJ-45 QDRII+ SRAM QSFP Interface Power 3 - 5V, 1.5V, 1.8V, 3.3V HSMC Port A & Port B Power 6 - Power & Temp Monitor DDR3 - Part 2 of 2 Power 4 - 1.0V_GXB, 1.5V_FPGA Decoupling 34 Power 8 - Cyclone V GX SoC GND Preliminary Schematic DO NOT COPY Title Size Document Number Rev Date: Sheet of C Cyclone V SoC FPGA Development Kit Board B 1 40 Wednesday, March 20, 2013 150-0321003-C1 (6XX-44184R) Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Copyright (c) 2013, Altera Corporation. All Rights Reserved. Title Size Document Number Rev Date: Sheet of C Cyclone V SoC FPGA Development Kit Board B 1 40 Wednesday, March 20, 2013 150-0321003-C1 (6XX-44184R) Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Copyright (c) 2013, Altera Corporation. All Rights Reserved. Title Size Document Number Rev Date: Sheet of C Cyclone V SoC FPGA Development Kit Board B 1 40 Wednesday, March 20, 2013 150-0321003-C1 (6XX-44184R) Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Copyright (c) 2013, Altera Corporation. All Rights Reserved.

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Page 1: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

DESCRIPTIONREV DATE PAGES

PAGE DESCRIPTION

2

NOTES:

Title, Notes, Block Diagram, Rev. History1

3

4

7

8

Cyclone V GX SoC Bank 7

9

Cyclone V GX SoC Bank 8

10

11

12

13

14

15

16

PLL

17

JTAG

18

19

20

21

RLDRAM II CIO

22

23

24

25

5

6

Display Port (x4)

1172 Parts, 88 Library Parts, 1330 Nets, 6643 Pins

A1 09/27/2012 All INITIAL REVISION A RELEASE

FPGA Package Top

Cyclone V SoC FPGA Development Kit Board

1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing Schematic Drawing PCB Film Bill of Materials Schematic Design Files Functional Specification PCB Layout Guidelines Assembly Rework

PCI Express Edge Connector

Cyclone V GX SoC Bank 4,5,6

Cyclone V GX SoC Bank 3

Cyclone V GX SoC Transceiver Banks

2.

100-0321003-A1110-0321003-A1120-0321003-A1130-0321003-A1140-0321003-A1150-0321003-A1160-0321003-A1170-0321003-A1180-0321003-A1210-0321003-A1220-0321003-A1320-0321003-A1

On-Board USB Blaster II

26

27

28

29

PAGE DESCRIPTION

30 Power 5 - Linear Regulator

Power 7 - Cyclone V GX SoC Power

Flash

5M2210 System Controller

User I/O (LEDs, Buttons, Switches, LCD)

Power 2 - 0.90V

SDI TX Cable Driver & SMB

31

32

33

Power 1 - DC Input, 12V, 3.3V

Cyclone V GX SoC Clocks

Cyclone V GX SoC Configuration

DDR3 - Part 1 of 2

Ethernet PHY & RJ-45

QDRII+ SRAM

QSFP Interface

Power 3 - 5V, 1.5V, 1.8V, 3.3V

HSMC Port A & Port B

Power 6 - Power & Temp Monitor

DDR3 - Part 2 of 2

Power 4 - 1.0V_GXB, 1.5V_FPGA

Decoupling34

Power 8 - Cyclone V GX SoC GND

Preliminary SchematicDO NOT COPY

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

1 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

1 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

1 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Page 2: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

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7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

FPGA Package Top View

XCVR BANK QR2

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

2 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

2 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

2 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Page 3: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

PCI Express Connector

Add Pull up connected to same voltage as IO bank

Add Pull up connected to same voltage as IO bank

PCIE_TX_C_P0PCIE_TX_C_N0

PCIE_TX_C_N1PCIE_TX_C_P1

PCIE_TX_C_N2PCIE_TX_C_P2

PCIE_TX_C_N3PCIE_TX_C_P3

PCIE_SMBCLKPCIE_SMBDAT

3.3V

12V3.3V

3.3V_EXP 12V_EXP12V_EXP12V_EXP

3.3V_EXP

3.3V_EXP

12V_EXP 3.3V_EXP

PCIE_PERSTn 4,11

PCIE_TX_P08PCIE_TX_N08

PCIE_TX_P18PCIE_TX_N18

PCIE_TX_N28

PCIE_TX_P28

PCIE_TX_P38PCIE_TX_N38

PCIE_PRSNT2_X19

PCIE_PRSNT2_X49

PCIE_REFCLK_SYN_N 10

PCIE_REFCLK_SYN_P 10

PCIE_WAKEn11

PCIE_SMBCLK 9PCIE_SMBDAT 9

PCIE_RX_N0 8

PCIE_RX_P08

PCIE_RX_N1 8

PCIE_RX_P18

PCIE_RX_P28

PCIE_RX_N2 8

PCIE_RX_N3 8

PCIE_RX_P38

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

3 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

3 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

3 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R255 4.70K, 1%

C237

220uF16V

C215

220uF16V

R262 4.70K, 1%

C68422uF25V

C670 0.1uF

C662 0.1uF

C650 0.1uF

C637 0.1uF

C68322uF25V

R554

0_Ohms

R271 4.7K

C238

47uF20V

C235

47uF20V

C232

220uF16V

C67822uF25V

R547

0_Ohms

C236

47uF20V

C656 0.1uF

C673 0.1uF

C649 0.1uF

C638 0.1uF

C68722uF25V

KEY

X4

X1

J25

PCIE-064-02-F-D-TH

+12VB1

+12VB2

+12VB3

GNDB4

SMCLKB5

SMDATB6

GNDB7

+3_3VB8

JTAG_TRSTNB9

+3_3VAUXB10

WAKE_NB11

RSVD1B12

GNDB13

PET0PB14

PET0NB15

GNDB16

PRSNT2_N_X1B17

GNDB18

PET1PB19

PET1NB20

GNDB21

GNDB22

PET2PB23

PET2NB24

GNDB25

GNDB26

PET3PB27

PET3NB28

GNDB29

RSVD3B30

PRSNT2_N_X4B31

GNDB32

PRSNT1_NA1

+12VA2

+12VA3

GNDA4

JTAG_TCKA5

JTAG_TDIA6

JTAG_TDOA7

JTAG_TMSA8

+3_3VA9

+3_3VA10

PERST_NA11

GNDA12

REFCLK+A13

REFCLK-A14

GNDA15

PER0PA16

PER0NA17

GNDA18

RSVD2A19

GNDA20

PER1PA21

PER1NA22

GNDA23

GNDA24

PER2PA25

PER2NA26

GNDA27

GNDA28

PER3PA29

PER3NA30

GNDA31

RSVD4A32

C231

47uF20V

Page 4: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Cyclone V GX SoC Bank 3 & 4

PCIE INTERFACE

HSMC LVCMOS INTERFACE

2.5 Volt

1.5 Volt

1.5 Volt

LVCMOS Only

DDR3_FPGA_CLK_P

DDR3_FPGA_CASnDDR3_FPGA_RASn

DDR3_FPGA_WEn

DDR3_FPGA_CSn

DDR3_FPGA_BA2DDR3_FPGA_BA1

DDR3_FPGA_BA0

DDR3_FPGA_CLK_N

DDR3_FPGA_A7

DDR3_FPGA_A8

DDR3_FPGA_A13

DDR3_FPGA_A6

DDR3_FPGA_A12

DDR3_FPGA_A9

DDR3_FPGA_A14 DDR3_FPGA_A4

DDR3_FPGA_A10

DDR3_FPGA_A5

DDR3_FPGA_A11

DDR3_FPGA_A1DDR3_FPGA_A0

DDR3_FPGA_DM1

DDR3_FPGA_DM0

DDR3_FPGA_ODT

DDR3_FPGA_RESETn

DDR3_FPGA_CKE

DDR3_FPGA_DM2

DDR3_FPGA_DM3

DDR3_FPGA_DQ7

DDR3_FPGA_DQ0DDR3_FPGA_DQS_P0

DDR3_FPGA_DQ13

DDR3_FPGA_DQ14

DDR3_FPGA_DQ8

DDR3_FPGA_DQ2

DDR3_FPGA_DQS_P1DDR3_FPGA_DQS_N1

DDR3_FPGA_DQS_N0

DDR3_FPGA_DQ10

DDR3_FPGA_DQ4

DDR3_FPGA_DQ15

DDR3_FPGA_DQ9

DDR3_FPGA_DQ3

DDR3_FPGA_DQ1

DDR3_FPGA_DQ12

DDR3_FPGA_DQ6

DDR3_FPGA_DQ11

DDR3_FPGA_DQ5

DDR3_FPGA_DQ23

DDR3_FPGA_DQ16DDR3_FPGA_DQS_P2

DDR3_FPGA_DQ29

DDR3_FPGA_DQ30

DDR3_FPGA_DQ24

DDR3_FPGA_DQ18

DDR3_FPGA_DQS_P3DDR3_FPGA_DQS_N3

DDR3_FPGA_DQS_N2

DDR3_FPGA_DQ26

DDR3_FPGA_DQ20

DDR3_FPGA_DQ31

DDR3_FPGA_DQ25

DDR3_FPGA_DQ19

DDR3_FPGA_DQ17

DDR3_FPGA_DQ28

DDR3_FPGA_DQ22

DDR3_FPGA_DQ27

DDR3_FPGA_DQ21

HSMA_D0

HSMA_D1HSMA_D2HSMA_D3HSMA_SDAHSMA_SCL

USER_DIPSW_FPGA1

USER_DIPSW_FPGA3

USER_DIPSW_FPGA0

USER_DIPSW_FPGA2

USER_PB_FPGA0USER_PB_FPGA1

USB_B2_DATA[7:0]

USB_FULLUSB_EMPTYUSB_SCLUSB_SDAUSB_B2_CLKUSB_RESETnUSB_OEnUSB_RDnUSB_WRn

DDR3_FPGA_DM3DDR3_FPGA_DM2

DDR3_FPGA_CLK_P

DDR3_FPGA_CASnDDR3_FPGA_RASnDDR3_FPGA_WEnDDR3_FPGA_CSn

DDR3_FPGA_BA2

DDR3_FPGA_ODTDDR3_FPGA_RESETn

DDR3_FPGA_BA1

DDR3_FPGA_CKE

DDR3_FPGA_BA0

DDR3_FPGA_CLK_N

DDR3_FPGA_DM0DDR3_FPGA_DM1

HSMA_PRSNTn

USB_B2_DATA0

USB_B2_DATA1USB_B2_DATA2USB_B2_DATA3USB_B2_DATA4

USB_B2_DATA5USB_B2_DATA6

USB_B2_DATA7

USB_FULLUSB_EMPTYUSB_SCLUSB_SDAUSB_B2_CLKUSB_RESETnUSB_OEnUSB_RDnUSB_WRn

RZQIN_1_5V

USER_LED_FPGA0

PCIE_PERSTn

HSMA_CLK_OUT_P1HSMA_CLK_OUT_N1

HSMA_CLK_IN_P1HSMA_CLK_IN_N1

HSMA_SDA17

HSMA_SCL17

HSMA_D[3:0]17

ENET2_RX_D[3..0] 5,19

ENET2_TX_D[3..0] 5,19

HSMA_PRSNTn16,17,23

USB_B2_DATA[7:0]25

USB_FULL25USB_EMPTY25

USB_SDA25

USB_RESETn25USB_OEn25USB_RDn25USB_WRn25

USB_SCL25

USB_B2_CLK16,25

DDR3_FPGA_DM[3:0]13

DDR3_FPGA_BA[2:0]13

DDR3_FPGA_DQS_P[3:0]13

DDR3_FPGA_DQS_N[3:0]13

DDR3_FPGA_A[14:0]9,13

DDR3_FPGA_DQ[31:0]13

DDR3_FPGA_CKE 13

DDR3_FPGA_CLK_P 13

DDR3_FPGA_CLK_N 13

DDR3_FPGA_DM2 13

DDR3_FPGA_DM3 13

DDR3_FPGA_CSn 13

DDR3_FPGA_WEn 13

DDR3_FPGA_RASn 13

DDR3_FPGA_CASn 13

DDR3_FPGA_BA0 13

DDR3_FPGA_BA1 13

DDR3_FPGA_BA2 13

DDR3_FPGA_RESETn 13

DDR3_FPGA_ODT 13

DDR3_FPGA_DM1 13DDR3_FPGA_DM0 13

USER_DIPSW_FPGA[3:0]23

USER_PB_FPGA[1:0]23

SDI_CLK148_UP8

SDI_CLK148_DN8

USER_LED_FPGA[3:0]9,23

P1TXERR19

P0TXERR19

ENET_DUAL_RESETn 19,21

PCIE_PERSTn 3,11

HSMA_CLK_OUT_P117

HSMA_CLK_OUT_N117

HSMA_CLK_IN_P117

HSMA_CLK_IN_N117

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

4 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

4 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

4 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Bank 3A

Bank 3B

CYCLONE V GX SoC BANK 3

5CSXFC6D_F896

U21A

DIFFIO_TX_B12pAF6

DIFFIO_RX_B14n,DQ2BAJ2

DIFFIO_TX_B29n,DQ4B,B_A_11AK9

DIFFIO_TX_B33n,GNDAJ10

DIFFIO_RX_B34p,DQ5B,B_BA_1AJ11

DIFFIO_TX_B33p,DQ5B,B_BA_0AH10

DIFFIO_TX_B36n,DQ5B,B_A_7AK13

DIFFIO_RX_B35n,DQSn5B,B_CK#AA15

DIFFIO_TX_B36p,B_A_6AK12

DIFFIO_RX_B35p,DQS5B,B_CKAA14

DIFFIO_RX_B38p,DQ5B,B_A_4AG15

DIFFIO_RX_B38n,DQ5B,B_A_5AH15

DIFFIO_TX_B40p,DQ5B,B_A_0AJ14

DIFFIO_TX_B40n,DQ5B,B_A_1AK14

DIFFIO_TX_B13n,DQ2BAH5

DIFFIO_RX_B14p,DQ2BAJ1

DIFFIO_TX_B13p,DQ2BAG5

DIFFIO_TX_B16n,DQ2BAH3

DIFFIO_RX_B15nAD12

DIFFIO_TX_B16p,DQ2BAG2

DIFFIO_RX_B15pAC12

DIFFIO_TX_B28n,DQ4B,B_A_13AK8

DIFFIO_RX_B27n,DQSn4B,B_CS#_1AC14

DIFFIO_TX_B28p,B_A_12AK7

DIFFIO_RX_B27p,DQS4B,B_CS#_0AB15

DIFFIO_RX_B30n,DQ4B,B_A_9AH14

DIFFIO_RX_B19n,DQSn3BAB13

DIFFIO_RX_B11n,DQSn2BAB12

DIFFIO_RX_B18n,DQ3BAG11

DIFFIO_RX_B10n,DQ2BAH2

DIFFIO_TX_B12n,DQ2BAG6

DIFFIO_RX_B26n,DQ4B,B_A_15AG13

DIFFIO_TX_B21n,DQ3BAK4

DIFFIO_TX_B24n,DQ3BAK6

DIFFIO_RX_B19p,DQS3BAA13

DIFFIO_RX_B26p,DQ4B,B_A_14AG12

DIFFIO_RX_B22p,DQ3BAE13

DIFFIO_TX_B9nAG7

DIFFIO_RX_B22n,DQ3BAF13

DIFFIO_RX_B11p,DQS2BAA12

DIFFIO_TX_B17nAH9

DIFFIO_TX_B24p,DQ3BAJ5

DIFFIO_TX_B20n,DQ3BAK3 DIFFIO_TX_B20pAK2

DIFFIO_TX_B25p,DQ4B,B_WE#AJ6

DIFFIO_TX_B21p,DQ3BAJ4

DIFFIO_TX_B17p,DQ3BAG10

DIFFIO_TX_B25n,GNDAJ7

DIFFIO_RX_B18p,DQ3BAF11

DIFFIO_TX_B8p,DQ1BAF9

DIFFIO_RX_B10p,DQ2BAG1

DIFFIO_RX_B23nAE14

DIFFIO_TX_B9p,DQ2BAF8

DIFFIO_RX_B23pAD14

DIFFIO_RX_B30p,DQ4B,B_A_8AH13

DIFFIO_TX_B29p,DQ4B,B_A_10AJ9

DIFFIO_TX_B32n,DQ4B,B_RAS#AH8DIFFIO_TX_B32p,DQ4B,B_CAS#AH7

DIFFIO_RX_B34n,DQ5B,B_BA_2AK11

R449100, 1%

Bank 4A

CYCLONE V GX SoC BANK 4

5CSXFC6D_F896

U21B

DIFFIO_TX_B61n,DQ8B,GNDAJ22

DIFFIO_RX_B42n,DQ6B,B_DQ_0AF18

DIFFIO_RX_B62n,DQ8B,B_DQ_20AF21

RZQ_0,DIFFIO_TX_B41nAG17

DIFFIO_RX_B42p,DQ6B,B_DQ_1AE17

DIFFIO_RX_B62p,DQ8B,B_DQ_21AF20

DIFFIO_TX_B41p,DQ6B,B_DQ_2AG16

DIFFIO_TX_B61p,DQ8B,B_DQ_22AH23

DIFFIO_TX_B64n,DQ8B,B_DQ_23AK24

DIFFIO_TX_B44n,DQ6B,B_DQ_3AF16

DIFFIO_RX_B63n,GNDAA19

DIFFIO_RX_B43n,DQSn6B,B_DQS#_0W16

DIFFIO_TX_B64p,DQ8B,B_DM_2AK23

DIFFIO_RX_B63p,GNDY18

DIFFIO_RX_B66n,DQ9B,B_DQ_24AF24

DIFFIO_TX_B44p,B_ODT_0AE16

DIFFIO_TX_B65n,GNDAJ25

DIFFIO_RX_B43p,DQS6B,B_DQS_0V16

DIFFIO_RX_B46n,DQ6B,B_DQ_4AH20 DIFFIO_RX_B66p,DQ9B,B_DQ_25

AF23DIFFIO_TX_B45n,DQ6B,B_ODT_1AK16 DIFFIO_TX_B65p,DQ9B,B_DQ_26

AJ24

DIFFIO_TX_B68n,DQ9B,B_DQ_27AK26

DIFFIO_RX_B46p,DQ6B,B_DQ_5AG21

DIFFIO_RX_B67n,DQSn9B,B_DQS#_3AD19

DIFFIO_TX_B45p,DQ6B,B_DQ_6AJ16

DIFFIO_TX_B68p,GNDAJ26

DIFFIO_RX_B67p,DQS9B,B_DQS_3AC20

DIFFIO_RX_B70n,DQ9B,B_DQ_28AE23

DIFFIO_TX_B48p,DQ6B,B_DM_0AH17

DIFFIO_TX_B69n,DQ9B,GNDAH25

DIFFIO_TX_B48n,DQ6B,B_DQ_7AH18

DIFFIO_RX_B50n,DQ7B,B_DQ_8AK18

DIFFIO_RX_B70p,DQ9B,B_DQ_29AE22

DIFFIO_TX_B69p,DQ9B,B_DQ_30AG25

DIFFIO_TX_B72n,DQ9B,B_DQ_31AK27

DIFFIO_RX_B71n,GNDW19

DIFFIO_TX_B72p,DQ9B,B_DM_3AJ27

DIFFIO_RX_B71p,GNDV18

DIFFIO_RX_B74n,DQ10B,B_DQ_32AD21

DIFFIO_TX_B73n,GNDAK29

DIFFIO_RX_B74p,DQ10B,B_DQ_33AD20

DIFFIO_TX_B73p,DQ10B,B_DQ_34AK28

DIFFIO_TX_B76n,DQ10B,B_DQ_35AH27

DIFFIO_RX_B75n,DQSn10B,B_DQS#_4AA20

DIFFIO_TX_B76p,GNDAG26

DIFFIO_RX_B75p,DQS10B,B_DQS_4Y19

DIFFIO_RX_B78n,DQ10B,B_DQ_36AC23

DIFFIO_TX_B77n,DQ10B,GNDAF26

DIFFIO_RX_B78p,DQ10B,B_DQ_37AC22

DIFFIO_TX_B77p,DQ10B,B_DQ_38AF25

DIFFIO_TX_B80n,DQ10B,B_DQ_39AE24

DIFFIO_RX_B79n,GNDAB21

DIFFIO_TX_B80p,DQ10B,B_DM_4AD24

DIFFIO_RX_B79p,GNDAA21

DIFFIO_TX_B60p,B_RESET#AK21 DIFFIO_RX_B59n,DQSn8B,B_DQS#_2AA18

DIFFIO_RX_B58n,DQ8B,B_DQ_16AE19

DIFFIO_TX_B57n,GNDAH22

DIFFIO_TX_B52p,B_CKE_1AJ19

DIFFIO_TX_B56p,DQ7B,B_DM_1AG23

DIFFIO_RX_B54p,DQ7B,B_DQ_13AF19

DIFFIO_RX_B58p,DQ8B,B_DQ_17AE18

DIFFIO_TX_B53n,DQ7B,B_CKE_0AJ21

DIFFIO_TX_B52n,DQ7B,B_DQ_11AK19

DIFFIO_RX_B51p,DQS7B,B_DQS_1V17

DIFFIO_TX_B57p,DQ8B,B_DQ_18AG22

DIFFIO_TX_B53p,DQ7B,B_DQ_14AJ20

DIFFIO_TX_B56n,DQ7B,B_DQ_15AH24

DIFFIO_RX_B59p,DQS8B,B_DQS_2Y17

DIFFIO_RX_B50p,DQ7B,B_DQ_9AJ17

DIFFIO_TX_B60n,DQ8B,B_DQ_19AK22

DIFFIO_TX_B49p,DQ7B,B_DQ_10AG18

DIFFIO_RX_B51n,DQSn7B,B_DQS#_1W17

DIFFIO_TX_B49n,GNDAH19

DIFFIO_RX_B54n,DQ7B,B_DQ_12AG20

Page 5: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Cyclone V GX SoC Bank 5 & 6

Si571 VCXO

2.5 Volt

2.5 Volt

1.5 Volt

1.5 Volt

DDR3_HPS_DQS_P0

DDR3_HPS_DQS_P1DDR3_HPS_DQS_N1

DDR3_HPS_DQS_N0

DDR3_HPS_DM1

DDR3_HPS_DM0

DDR3_HPS_CLK_P

DDR3_HPS_A7

DDR3_HPS_A3

DDR3_HPS_A8

DDR3_HPS_CASnDDR3_HPS_RASn

DDR3_HPS_WEn

DDR3_HPS_A13

DDR3_HPS_A6

DDR3_HPS_A12

DDR3_HPS_A2

DDR3_HPS_A9

DDR3_HPS_CSn

DDR3_HPS_BA2

DDR3_HPS_RESETn

DDR3_HPS_BA1

DDR3_HPS_A14

DDR3_HPS_A4

DDR3_HPS_A10

DDR3_HPS_A5

DDR3_HPS_A11

DDR3_HPS_CKE

DDR3_HPS_BA0

DDR3_HPS_CLK_N

DDR3_HPS_A1DDR3_HPS_A0

DDR3_HPS_DQ7

DDR3_HPS_DQ0

DDR3_HPS_DQ13DDR3_HPS_DQ14

DDR3_HPS_DQ8

DDR3_HPS_DQ2

DDR3_HPS_DQ10

DDR3_HPS_DQ4

DDR3_HPS_DQ15

DDR3_HPS_DQ9

DDR3_HPS_DQ3

DDR3_HPS_DQ1

DDR3_HPS_DQ12

DDR3_HPS_DQ6

DDR3_HPS_DQ11

DDR3_HPS_DQ5

DDR3_HPS_DQ23

DDR3_HPS_DQ16

DDR3_HPS_DQS_P2

DDR3_HPS_DQ18

DDR3_HPS_DQS_P3DDR3_HPS_DQS_N3

DDR3_HPS_DQS_N2

DDR3_HPS_DQ20DDR3_HPS_DQ19

DDR3_HPS_DQ17

DDR3_HPS_DQ22DDR3_HPS_DQ21

DDR3_HPS_DQ29DDR3_HPS_DQ30

DDR3_HPS_DQ24

DDR3_HPS_DQ26

DDR3_HPS_DQ31

DDR3_HPS_DQ25

DDR3_HPS_DQ28DDR3_HPS_DQ27

DDR3_HPS_DM3

DDR3_HPS_DM2

DDR3_HPS_DQ32

DDR3_HPS_DQ39

DDR3_HPS_DQS_P4DDR3_HPS_DQS_N4

DDR3_HPS_DQ34DDR3_HPS_DQ35DDR3_HPS_DQ36DDR3_HPS_DQ37DDR3_HPS_DQ38

DDR3_HPS_DQ33

DDR3_HPS_DM4

DDR3_HPS_ODT

DDR3_HPS_CLK_P

DDR3_HPS_CASnDDR3_HPS_RASn

DDR3_HPS_WEnDDR3_HPS_CSn

DDR3_HPS_BA2DDR3_HPS_BA1

DDR3_HPS_CKE

DDR3_HPS_BA0

DDR3_HPS_CLK_N

DDR3_HPS_ODT

DDR3_HPS_RESETn

ENET1_RX_D2ENET1_RX_D3

ENET1_RX_D0ENET1_RX_D1

ENET1_TX_D0ENET1_TX_D1ENET1_TX_D2ENET1_TX_D3

ENET2_RX_D2

ENET2_RX_D0

ENET2_RX_D3

ENET2_RX_D1

ENET2_TX_D0

ENET2_TX_D2ENET2_TX_D1

ENET2_TX_D3

USER_DIPSW_HPS0

USER_DIPSW_HPS2USER_DIPSW_HPS1

USER_DIPSW_HPS3USER_PB_HPS0USER_PB_HPS1USER_PB_HPS2USER_PB_HPS3

HSMA_CLK_OUT_N[2:1]4,7,17

HSMA_CLK_OUT_P[2:1]4,7,17

HSMA_TX_D_P[16:0]7,17

HSMA_TX_D_N[16:0]7,17

HSMA_RX_D_P[16:0]7,17

HSMA_RX_D_N[16:0]7,17

SDI_CLK148_DN 4,8

DDR3_HPS_DQS_P[4:0]14

DDR3_HPS_DQS_N[4:0]14

DDR3_HPS_DQ[39:0]14

DDR3_HPS_BA[2:0]14

DDR3_HPS_A[14:0]14

DDR3_HPS_DM[4:0]14

ENET1_TX_D[3..0]19ENET1_RX_D[3..0]19

ENET1_TX_EN19

ENET1_RX_ERROR19ENET1_RX_DV19ENET1_RX_CLK19

ENET1_TX_CLK_FB19ENET2_RX_ERROR19ENET2_RX_DV19

ENET2_RX_CLK 19ENET2_TX_CLK_FB19

ENET2_TX_EN19

ENET2_TX_D[3..0]19ENET2_RX_D[3..0]19

SDI_TX_EN16,20

SDI_TX_SD_HDn20SDI_RSTI20

SDI_RX_EN16,20

SDI_RX_BYPASS16,20

SDI_FAULT20

DDR3_HPS_CLK_P14

DDR3_HPS_CLK_N14

DDR3_HPS_CKE 14

DDR3_HPS_BA0 14

DDR3_HPS_BA1 14

DDR3_HPS_BA2 14

DDR3_HPS_RASn 14

DDR3_HPS_CASn 14

DDR3_HPS_WEn 14

DDR3_HPS_CSn 14

DDR3_HPS_ODT 14

DDR3_HPS_RESETn 14

USER_DIPSW_HPS[3:0]23

USER_PB_HPS[3:0]23

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

5 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

5 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

5 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R410100, 1%

CYCLONE V GX SoC BANK 5Bank 5A

Bank 5B

5CSXFC6D_F896

U21C

DIFFIO_TX_R12p,DQ2RAG28

RZQ_1,DIFFIO_TX_R1p,DQ1RAG27

DIFFIO_RX_R4p,DQ1RW20

DIFFIO_RX_R17nV25

DIFFIO_TX_R18n,DQ3RAC29

DIFFIO_RX_R19p,DQ3RAB30

DIFFIO_TX_R20p,DQ3RAB28 DIFFIO_RX_R19n,DQ3RAA30

DIFFIO_TX_R20n,DQ3RAA28

DIFFIO_TX_R24p,DQ3RAD30

RZQ_2,DIFFIO_TX_R24nAC30

DIFFIO_RX_R11n,DQ2RY24

DIFFIO_RX_R4n,DQ1RY21

DIFFIO_TX_R12n,DQ2RAF28

DIFFIO_TX_R7p,DQ1RAA25

DIFFIO_RX_R8p,DQ1RAB22 DIFFIO_RX_R13p,DQS2R

V23DIFFIO_TX_R7n

AB26

DIFFIO_TX_R14pAF29

DIFFIO_RX_R8n,DQ1RAB23 DIFFIO_RX_R13n,DQSn2R

W24

DIFFIO_RX_R9pAA24

DIFFIO_TX_R14n,DQ2RAF30

DIFFIO_TX_R10p,DQ2RAE27 DIFFIO_RX_R15p,DQ2R

AD26DIFFIO_RX_R9n

AB25

DIFFIO_TX_R16p,DQ2RAH30

DIFFIO_TX_R10n,DQ2RAE28 DIFFIO_RX_R15n,DQ2R

AC27

DIFFIO_RX_R11p,DQ2RY23

DIFFIO_TX_R16nAG30

DIFFIO_RX_R17pW25

DIFFIO_TX_R18p,DQ3RAC28

CYCLONE V GX SoC BANK 6

Bank 6A

Bank 6B

5CSXFC6D_F896

U21D

HPS_DDR,HPS_A_13C29

HPS_GI14M25

HPS_DDR,HPS_A_14H25

HPS_DDR,HPS_DM_0K28

HPS_DDR,HPS_WE#C28

HPS_DDR,HPS_DQ_7J29

HPS_DDR,HPS_A_15G25

HPS_DDR,HPS_DQ_5L24

HPS_RZQ_0D27

HPS_DDR,HPS_DQ_6J30

HPS_DDR,HPS_DQ_4L25

HPS_DDR,HPS_ODT_1H29

HPS_DDR,HPS_DQS_0N18

HPS_DDR,HPS_ODT_0H28

HPS_DDR,HPS_DQS#_0M19

HPS_DDR,HPS_DQ_3G28

HPS_DDR,HPS_DQ_1K22

HPS_DDR,HPS_DQ_2H30

HPS_DDR,HPS_DQ_0K23

HPS_DDR,HPS_A_0F26

HPS_DDR,HPS_A_1G30

HPS_DDR,HPS_A_4J25

HPS_DDR,HPS_A_2F28

HPS_DDR,HPS_A_5J27

HPS_DDR,HPS_A_3F30

HPS_DDR,HPS_CKM23

HPS_GI11M22

HPS_DDR,HPS_DM_1M28

HPS_GI12N23

HPS_DDR,HPS_A_6F29

HPS_DDR,HPS_DQ_15M30

HPS_DDR,HPS_CK#L23

HPS_DDR,HPS_DQ_13M27

HPS_DDR,HPS_A_7E28

HPS_DDR,HPS_DQ_14L28

HPS_DDR,HPS_BA_1J24 HPS_DDR,HPS_BA_0E29

HPS_DDR,HPS_BA_2J23

HPS_DDR,HPS_DQ_12M26

HPS_DDR,HPS_CAS#E27

HPS_DDR,HPS_CKE_0L29

HPS_DDR,HPS_RAS#D30

HPS_DDR,HPS_DQS_1N25

HPS_DDR,HPS_A_8H27

HPS_DDR,HPS_CKE_1L30

HPS_DDR,HPS_A_10D29

HPS_DDR,HPS_DQS#_1N24

HPS_DDR,HPS_A_9G26

HPS_DDR,HPS_DQ_11K27

HPS_DDR,HPS_A_11C30

HPS_DDR,HPS_DQ_9L26

HPS_DDR,HPS_CS#_0H24

HPS_DDR,HPS_DQ_10K29

HPS_DDR,HPS_A_12B30

HPS_DDR,HPS_DQ_8K26

HPS_DDR,HPS_CS#_1K21

HPS_GI13J26

HPS_DDR,HPS_DQS_4T24

HPS_GI3U20

HPS_DDR,HPS_DQ_36T25

HPS_DDR,HPS_DQ_37U25

HPS_DDR,HPS_DQS#_4T23

HPS_DDR,HPS_DM_2R28

HPS_DDR,HPS_DQ_32W26

HPS_DDR,HPS_DQ_29R26

HPS_DDR,HPS_DQ_26T29

HPS_DDR,HPS_DM_4W27

HPS_DDR,HPS_DQ_27T28

HPS_GI7V20

HPS_DDR,HPS_DQ_23R29

HPS_GI6T30

HPS_DDR,HPS_DQ_39Y29HPS_DDR,HPS_DQ_38V27

HPS_GI8P22

HPS_DDR,HPS_DQ_24P24

HPS_DDR,HPS_DQ_34U27

HPS_GI1Y28

HPS_DDR,HPS_DQ_35V28

HPS_GI2V29

HPS_DDR,HPS_DQ_33R24

HPS_GI4T21

HPS_DDR,HPS_DQ_25P25

HPS_DDR,HPS_DM_3W30

HPS_DDR,HPS_DQ_31W29

HPS_DDR,HPS_DQS#_2R18

HPS_DDR,HPS_DQ_20P26

HPS_GI9P29

HPS_DDR,HPS_DQ_22N27

HPS_DDR,HPS_RESET#P30

HPS_DDR,HPS_DQ_21P27

HPS_DDR,HPS_DQS_2R19

HPS_DDR,HPS_DQ_19N28

HPS_DDR,HPS_DQS#_3R21

HPS_DDR,HPS_DQ_17T26 HPS_DDR,HPS_DQ_16U26

HPS_GI10N30

HPS_DDR,HPS_DQ_18N29

HPS_DDR,HPS_DQ_28R27

HPS_GI5U28

HPS_DDR,HPS_DQ_30V30

HPS_DDR,HPS_DQS_3R22

Page 6: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Cyclone V GX SoC Bank 7

ETHERNET INTERFACE

Micro SD / USB INTERFACE

BOOTSEL0

BOOTSEL1

BOOTSEL2

CLKSEL0

CLKSEL1

Logic 0 = pin 6 <--> pin 7 (Bypass)Logic 1 = pin 6 <--> pin 4 (Enable)

Logic 0 = pin 10 <--> pin 9 (TRST from JTAG)Logic 1 = pin 10 <--> pin 2 (TRST from MICTOR)

ENET_HPS_TX_ENENET_HPS_GTX_CLK

ENET_HPS_MDIO

ENET_HPS_MDC

ENET_HPS_RX_DV

ENET_HPS_TXD[3..0]

ENET_HPS_RX_CLK

ENET_HPS_RXD[3..0]

ENET_HPS_RESETn

ENET_HPS_INTn

ENET_HPS_INTn

SD_DAT2SD_DAT0SD_DAT1

SD_CMDSD_PWREN

SD_CLK

USB_DATA[7..0]

SD_CD_DAT3

MICTOR_PWR2

TRACE_CLK_MIC

MICTOR_PWR1

JTAG_MICTOR_TCKJTAG_MICTOR_TMS

JTAG_HPS_TRST

MISOSCK_SCL

MOSI_SDACSn

SPI_MISO

SPI_SCKSPI_MOSI

SPI_CSn

SPI_MISO

SPI_MOSI

SPI_SCK

SPI_CSn

SCK_SCL

MOSI_SDA

CSn

MISO

I2C_SDA_HPS

I2C_SCL_HPS

BOOTSEL2

QSPI_SS0

SPI_CSn

CAN_0_TX

UART_TX

MICTOR_TRST

MICTOR_RSTn

JTAG_MICTOR_TMSJTAG_MICTOR_TDI

HPS_RESETn

ENET_HPS_GTX_CLK

ENET_HPS_TXD0ENET_HPS_TXD1ENET_HPS_TXD2ENET_HPS_TXD3ENET_HPS_RXD0

ENET_HPS_TX_EN ENET_HPS_RXD3ENET_HPS_RX_CLKENET_HPS_RXD1

ENET_HPS_RXD2

ENET_HPS_MDCENET_HPS_MDIO

ENET_HPS_RX_DV

USB_DATA6

USB_DATA7USB_CLKUSB_NXTUSB_DIRUSB_STP

USB_DATA5USB_DATA4USB_DATA3USB_DATA2USB_DATA1USB_DATA0

BOOTSEL2

HPS_RESETn

CODEC_SEL

USER_LED_HPS0USER_LED_HPS1USER_LED_HPS2 USER_LED_HPS3

USER_LED_HPS[3..0]

MICTR_TRST

MICTOR_TRST

JTAG_MIC_SEL

TRACE_DATA7TRACE_DATA6TRACE_DATA5TRACE_DATA4TRACE_DATA3TRACE_DATA2TRACE_DATA1

TRACE_DATA0

MIC_34MIC_36

TRACE_DATA3TRACE_DATA4TRACE_DATA5

TRACE_DATA7TRACE_DATA6

TRACE_DATA0

TRACE_DATA2TRACE_DATA1

MICTOR_RSTn

JTAG_HPS_TRST

JTAG_MIC_SEL

TRACE_CLK_MIC

I2C_SDA_HPSI2C_SCL_HPS

JTAG_MICTOR_TDI

JTAG_MICTOR_TDO

MIC_36MIC_34

3.3V

3.3V

3.3V

3.3V

3.3V9V_VPP

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

2.5V_REG_HPS

3.3V

2.5V_REG_HPS

5.0V

2.5V_HPS

2.5V_HPS

ENET_HPS_RESETn18,21ENET_HPS_MDC18

ENET_HPS_GTX_CLK18

ENET_HPS_MDIO18

ENET_HPS_TX_EN18

ENET_HPS_RXD[3..0]18

ENET_HPS_RX_DV18ENET_HPS_RX_CLK18

ENET_HPS_TXD[3..0]18

ENET_HPS_INTn18

QSPI_SS0 21QSPI_CLK 21

QSPI_IO3 21

QSPI_IO2 21

QSPI_IO1 21

QSPI_IO0 21

SD_DAT2 22SD_DAT022SD_DAT122

SD_CMD22SD_PWREN

SD_CLK 22

USB_DATA[7..0]22

SD_CD_DAT3 22

I2C_SDA_HPS 18,23,27

I2C_SCL_HPS 18,23,27

CAN_0_TX 24CAN_0_RX 24

CLK_OSC110CLK_OSC210

JTAG_MICTOR_TCK 12JTAG_MICTOR_TMS 12

UART_RX24

UART_TX24JTAG_HPS_TDO12

JTAG_HPS_TDI12

JTAG_HPS_TCK12

JTAG_HPS_TMS12

USB_DATA6 22

USB_DATA7 22

USB_CLK 22

USB_NXT22

USB_DIR22

USB_STP22

USB_DATA5 22

USB_DATA422USB_DATA322USB_DATA222USB_DATA122USB_DATA022

HPS_RESETn16,21

MICTOR_RSTn12,16,21

USER_LED_HPS[3..0]23

JTAG_TRST 12,16

JTAG_MICTOR_TDO 12

JTAG_MICTOR_TDI 12

CONV_HPS_USB_N

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

6 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

6 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

6 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R258

0

R310 10.0K

R2421.00k

R394 22

R330 10K

R395 22

C686

0.1uF

R247 10.0K

XJ3

881545-2

R4 4.70K, 1%

R259 0

R376 22

J4

Mictor38P

5VDC1

SCL2

GND3

SDA4

CLKE5

CLKO6

D15E7

D15O8

D14E9

D14O10

D13E11

D13O12

D12E13

D12O14

D11E15

D11O16

D10E17

D10O18

D9E19

D9O20

D8E21

D8O22

D7E23

D7O24

D6E25

D6O26

D5E27

D5O28

D4E29

D4O30

D3E31

D3O32

D2E33

D2O34

D1E35

D1O36

D0E37

D0O38

GND139

GND240

GND341

GND442

GND543

R266

10.0K

R3 4.70K, 1%

R329 DNI

J26HEADER, 1x3-PIN

123

R248 1.00k

XJ4

881545-2

R392

4.70K, 1%

R244 1.00k

R260 0

R328 10K

R320_Ohms

C244 0.1uF

U57

TS5A23157

IN11

NO12

GND3

NO24

IN25

COM26

NC27

V+8

NC19

COM110

C25

0.1uF

R393

4.70K, 1%

R374 22

R327 10K

R243 10.0K

R373 22

R125 4.70K, 1%

R2401.00k

R375 22

R332 DNI

R396 22

R377 22

J27

HEADER, 1x3-PIN

123

J32

HDR 2X7, VT, THM, 2mm

11

33

55

77

99

1111

1313

22

44

66

88

1010

1212

1414

CYCLONE V GX SoC BANK 7

Bank 7A

Bank 7B

Bank 7C

Bank 7D

5CSXFC6D_F896

U21E

TRACE_D5,SPIS1_MOSI,CAN1_TX,HPS_GPIO54G21

QSPI_IO2,USB1_DIR,HPS_GPIO31A19

TRACE_D6,SPIS1_SS0,I2C0_SDA,HPS_GPIO55C24

QSPI_IO3,USB1_NXT,HPS_GPIO32E19

TRACE_D7,SPIS1_MISO,I2C0_SCL,HPS_GPIO56E23

QSPI_SS0,BOOTSEL1,HPS_GPIO33A18

SPIM0_CLK,I2C1_SDA,UART0_CTS,HPS_GPIO57A23

QSPI_CLK,HPS_GPIO34D19

SPIM0_MOSI,I2C1_SCL,UART0_RTS,HPS_GPIO58C22

QSPI_SS1,HPS_GPIO35C19

SPIM0_MISO,CAN1_RX,UART1_CTS,HPS_GPIO59B23

RGMII0_MDIO,USB1_D5,I2C2_SDA,HPS_GPIO6C14

SPIM0_SS0,CAN1_TX,UART1_RTS,BOOTSEL0,HPS_GPIO60H20

SDMMC_CMD,USB0_D0,HPS_GPIO36F18

SDMMC_PWREN,USB0_D1,HPS_GPIO37B17

SDMMC_D0,USB0_D2,HPS_GPIO38G18

UART0_RX,CAN0_RX,SPIM0_SS1,HPS_GPIO61B22

SDMMC_D1,USB0_D3,HPS_GPIO39C17

UART0_TX,CAN0_TX,SPIM1_SS1,HPS_GPIO62G22

SDMMC_D4,USB0_D4,HPS_GPIO40H17

I2C0_SDA,UART1_RX,SPIM1_CLK,HPS_GPIO63C23

SDMMC_D5,USB0_D5,HPS_GPIO41C18

I2C0_SCL,UART1_TX,SPIM1_MOSI,HPS_GPIO64D22

SDMMC_D6,USB0_D6,HPS_GPIO42G17

CAN0_RX,UART0_RX,SPIM1_MISO,HPS_GPIO65E24

SDMMC_D7,USB0_D7,HPS_GPIO43E18

CAN0_TX,UART0_TX,SPIM1_SS0,HPS_GPIO66D24

SDMMC_CLK_IN,USB0_CLK,HPS_GPIO44E17 SDMMC_CLK,USB0_STP,HPS_GPIO45A16 SDMMC_D2,USB0_DIR,HPS_GPIO46D17

RGMII0_TX_CLK,HPS_GPIO0F16

SDMMC_D3,USB0_NXT,HPS_GPIO47B16

RGMII0_TXD0,USB1_D0,HPS_GPIO1E16RGMII0_TXD1,USB1_D1,HPS_GPIO2G16

RGMII0_RX_CLK,USB1_CLK,HPS_GPIO10N16 RGMII0_TXD2,USB1_D2,HPS_GPIO3

D16

RGMII0_TX_CTL,HPS_GPIO9B15

RGMII0_TXD3,USB1_D3,HPS_GPIO4D14

RGMII0_RX_CTL,USB1_D7,HPS_GPIO8M17

RGMII0_RXD0,USB1_D4,HPS_GPIO5A15

RGMII0_RXD3,USB1_NXT,HPS_GPIO13A14

HPS_nRSTC27

NAND_ALE,RGMII1_TX_CLK,QSPI_SS3,HPS_GPIO14H19

HPS_nPORF23

NAND_CE,RGMII1_TXD0,USB1_D0,HPS_GPIO15F20

HPS_TDOB28

NAND_CLE,RGMII1_TXD1,USB1_D1,HPS_GPIO16J19

VCC_HPSG23

NAND_RE,RGMII1_TXD2,USB1_D2,HPS_GPIO17F21

HPS_TMSA29

NAND_RB,RGMII1_TXD3,USB1_D3,HPS_GPIO18F19

HPS_TCKH22

NAND_DQ0,RGMII1_RXD0,HPS_GPIO19A21

HPS_TRSTA28

NAND_DQ1,RGMII1_MDIO,I2C3_SDA,HPS_GPIO20E21

HPS_TDIB27

NAND_DQ2,RGMII1_MDC,I2C3_SCL,HPS_GPIO21B21

HPS_PORSELF24

NAND_DQ3,RGMII1_RX_CTL,USB1_D4,HPS_GPIO22K17

HPS_CLK1D25

NAND_DQ4,RGMII1_TX_CTL,USB1_D5,HPS_GPIO23A20

HPS_CLK2F25

NAND_DQ5,RGMII1_RX_CLK,USB1_D6,HPS_GPIO24G20

TRACE_CLK,HPS_GPIO48B26

TRACE_D0,SPIS0_CLK,UART0_RX,HPS_GPIO49B25

NAND_DQ7,RGMII1_RXD2,HPS_GPIO26B18

TRACE_D1,SPIS0_MOSI,UART0_TX,HPS_GPIO50C25

NAND_WP,RGMII1_RXD3,QSPI_SS2,HPS_GPIO27D21

TRACE_D2,SPIS0_MISO,I2C1_SDA,HPS_GPIO51A25

NAND_WE,QSPI_SS1,BOOTSEL2,HPS_GPIO28D20

H23TRACE_D3,SPIS0_SS0,I2C1_SCL,HPS_GPIO52

QSPI_IO0,USB1_CLK,HPS_GPIO29C20

TRACE_D4,SPIS1_CLK,CAN1_RX,HPS_GPIO53A24

QSPI_IO1,USB1_STP,HPS_GPIO30H18

RGMII0_RXD2,USB1_DIR,HPS_GPIO12E14

RGMII0_RXD1,USB1_STP,HPS_GPIO11C15

NAND_DQ6,RGMII1_RXD1,USB1_D7,HPS_GPIO25B20

RGMII0_MDC ,USB1_D6,I2C2_SCL,HPS_GPIO7D15

R246 1.00k

J31

CON2

12

R24110.0K

R3180

C24

0.001uf

U54

IDTQS3VH257

I0A2

I0B5

I1A3

I0C11

I1B6

I1C10

I0D14

I1D13

YA4

YB7

YC9

YD12

S1

E15

GND8

VCC16

R331 10K

R330_Ohms

J30

HEADER, 1x3-PIN

123

J28HEADER, 1x3-PIN

123

R245 10.0K

J16

CON2

12

R338 10.0K

R23910.0K

C685

2.2uF

J29

HEADER, 1x3-PIN

123

R391 0

Page 7: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Cyclone V GX SoC Bank 8

2.5 Volt

HSMA_TX_D_P9HSMA_TX_D_N9

HSMA_CLK_OUT_P2HSMA_CLK_OUT_N2

HSMA_RX_D_P6HSMA_RX_D_N6

HSMA_RX_D_P10HSMA_RX_D_N10

I2C_SDA_FPGAI2C_SCL_FPGA

HSMA_TX_D_P0HSMA_TX_D_N0

HSMA_TX_D_P1HSMA_TX_D_N1

HSMA_TX_D_P2HSMA_TX_D_N2

HSMA_TX_D_P3HSMA_TX_D_N3

HSMA_TX_D_P4HSMA_TX_D_N4

HSMA_TX_D_P5HSMA_TX_D_N5

HSMA_TX_D_P6HSMA_TX_D_N6

HSMA_TX_D_P7HSMA_TX_D_N7

HSMA_TX_D_P8HSMA_TX_D_N8

HSMA_TX_D_P10HSMA_TX_D_N10

HSMA_TX_D_P11HSMA_TX_D_N11

HSMA_TX_D_P12HSMA_TX_D_N12

HSMA_TX_D_P13HSMA_TX_D_N13

HSMA_TX_D_P14HSMA_TX_D_N14

HSMA_TX_D_P15HSMA_TX_D_N15

HSMA_TX_D_P16HSMA_TX_D_N16

HSMA_RX_D_N0HSMA_RX_D_P0

HSMA_RX_D_P1HSMA_RX_D_N1

HSMA_RX_D_P2HSMA_RX_D_N2

HSMA_RX_D_P3HSMA_RX_D_N3

HSMA_RX_D_P4HSMA_RX_D_N4

HSMA_RX_D_P5HSMA_RX_D_N5

HSMA_RX_D_P7HSMA_RX_D_N7

HSMA_RX_D_P8HSMA_RX_D_N8

HSMA_RX_D_P9HSMA_RX_D_N9

HSMA_RX_D_P11HSMA_RX_D_N11

HSMA_RX_D_P12HSMA_RX_D_N12

HSMA_RX_D_P13HSMA_RX_D_N13

HSMA_RX_D_P14HSMA_RX_D_N14

HSMA_RX_D_P15HSMA_RX_D_N15HSMA_RX_D_P16HSMA_RX_D_N16

HSMA_CLK_OUT_P[2:1]4,17

HSMA_CLK_OUT_N[2:1]4,17

HSMA_CLK_IN_N[2:1]4,9,17

HSMA_CLK_IN_P[2:1]4,9,17

HSMA_D[3:0]4,17

HSMA_TX_D_P[16:0]17

HSMA_TX_D_N[16:0]17

HSMA_RX_D_P[16:0]17

HSMA_RX_D_N[16:0]17

I2C_SDA 16,20,26

I2C_SCL 16,20,26ENET_FPGA_MDC19

ENET_FPGA_MDIO19

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

7 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

7 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

7 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

CYCLONE V GX SoC BANK 8

Bank 8A

5CSXFC6D_F896

U21F

DIFFIO_RX_T13p,DQS2TH14

DIFFIO_RX_T31n,DQ4TG11

DIFFIO_TX_T14pC10

DIFFIO_TX_T32nD4DIFFIO_RX_T13n,DQSn2T

G13

DIFFIO_RX_T33pK7

DIFFIO_TX_T14n,DQ2TC9

DIFFIO_TX_T34p,DQ5TE3DIFFIO_RX_T15p,DQ2T

F13DIFFIO_RX_T33n

K8

DIFFIO_TX_T16p,DQ2TA6

DIFFIO_TX_T34n,DQ5TE2DIFFIO_RX_T15n,DQ2T

E13

DIFFIO_RX_T35p,DQ5TG10

DIFFIO_TX_T16nA5

DIFFIO_TX_T36p,DQ5TE1DIFFIO_RX_T17p

H8DIFFIO_RX_T35n,DQ5T

F10

DIFFIO_TX_T18p,DQ3TA4

DIFFIO_TX_T36n,DQ5TD1DIFFIO_RX_T17n

G8

DIFFIO_RX_T37p,DQS5TJ10

DIFFIO_TX_T18n,DQ3TA3

DIFFIO_TX_T38pE7DIFFIO_RX_T19p,DQ3T

E12DIFFIO_RX_T37n,DQSn5T

J9

DIFFIO_TX_T20p,DQ3TD6

DIFFIO_TX_T38n,DQ5TE6DIFFIO_RX_T19n,DQ3T

D12

DIFFIO_RX_T39p,DQ5TF9

DIFFIO_TX_T20n,DQ3TC5

DIFFIO_TX_T40p,DQ5TG7DIFFIO_RX_T21p,DQS3T

H13DIFFIO_RX_T39n,DQ5T

F8

DIFFIO_TX_T22pD5

DIFFIO_TX_T40nF6DIFFIO_RX_T21n,DQSn3T

H12

DIFFIO_TX_T22n,DQ3TC4

DIFFIO_TX_T2p,DQ1TB13

DIFFIO_TX_T2n,DQ1TA13

DIFFIO_RX_T3p,DQ1TC13 DIFFIO_RX_T23p,DQ3T

F11

DIFFIO_RX_T3n,DQ1TB12

DIFFIO_TX_T24p,DQ3TE8

DIFFIO_RX_T5p,DQS1TF15

DIFFIO_RX_T23n,DQ3TE11

DIFFIO_TX_T6pC12

DIFFIO_TX_T24nD7

DIFFIO_RX_T25pJ7

DIFFIO_TX_T26p,DQ4TB2

DIFFIO_RX_T5n,DQSn1TF14

DIFFIO_RX_T25nH7

DIFFIO_TX_T6n,DQ1TB11

DIFFIO_TX_T26n,DQ4TB1

DIFFIO_RX_T7p,DQ1TD11

DIFFIO_RX_T27p,DQ4TB6

DIFFIO_TX_T8p,DQ1TA9

DIFFIO_TX_T28p,DQ4TC3

DIFFIO_RX_T7n,DQ1TD10

DIFFIO_RX_T27n,DQ4TB5

DIFFIO_TX_T8nA8

DIFFIO_TX_T28n,DQ4TB3

DIFFIO_TX_T10p,DQ2TC7

DIFFIO_RX_T29p,DQS4TK12

DIFFIO_TX_T10n,DQ2TB7

DIFFIO_TX_T30pD2DIFFIO_RX_T11p,DQ2T

E9DIFFIO_RX_T29n,DQSn4T

J12

DIFFIO_TX_T12p,DQ2TC8

DIFFIO_TX_T30n,DQ4TC2DIFFIO_RX_T11n,DQ2T

D9

DIFFIO_RX_T31p,DQ4TG12

DIFFIO_TX_T12n,DQ2TB8

DIFFIO_TX_T32p,DQ4TE4

R427

0

R426

0

Page 8: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Cyclone V GX SoC Transceivers and Power

CMU PLL (PCIe)

CAD Note:Place resistors& capacitorsnear SMAconnectors

SMA Connector Interface

CAD Note:Overlap R137 & R138Overlap R135 & R136

SMA Connector Interface

CAD Note:Place resistors & capacitorsnear SMA connectors

CAD Note:Overlap R22 & R27Overlap R24 & R19

CAD Note:Place resistor near RREF_TL pins.Route away frm aggressor

LVDS

From MAXV

SDI Reference Clocks

From FPGA

OPTION_SMA_XCVR_RX_P

OPTION_SMA_XCVR_RX_N

GXB_RX_L4_NGXB_RX_L4_P

SDI_RX_NSDI_RX_P

OPTION_SMA_XCVR_TX_P

OPTION_SMA_XCVR_TX_N

SDI_TX_PSDI_TX_NGXB_TX_L4_N

GXB_TX_L4_P

XCVR_RREF_TL

CLK_148_CP

CLK_148_CN

SI571_VCONTROL

CLK_148_P

CLK_148_N

CLK_148_NCLK_148_P

2.5V_REG_HPS

PCIE_RX_N03

PCIE_RX_N13

PCIE_RX_P13

PCIE_RX_N23

PCIE_RX_P23

PCIE_RX_N33

PCIE_RX_P33

PCIE_RX_P03

REFCLK_QL2_P10REFCLK_QL2_N10

PCIE_TX_N0 3

PCIE_TX_N1 3

PCIE_TX_P1 3

PCIE_TX_N2 3

PCIE_TX_P2 3

PCIE_TX_N3 3

PCIE_TX_P3 3

PCIE_TX_P0 3

PCIE_REFCLK_QL0_P10PCIE_REFCLK_QL0_N10

SDI_RX_N

20

SDI_RX_P

20

HSMA_RX_N017

HSMA_RX_P017HSMA_TX_N0 17

HSMA_TX_P0 17

HSMA_RX_N217

HSMA_RX_P217

HSMA_RX_N117

HSMA_RX_P117

HSMA_RX_N317

HSMA_RX_P317

HSMA_TX_N1 17

HSMA_TX_P1 17

HSMA_TX_N2 17

HSMA_TX_P2 17

HSMA_TX_N3 17

HSMA_TX_P3 17

SDI_TX_P 20SDI_TX_N 20

SI571_EN16

SDI_CLK148_UP4

SDI_CLK148_DN4

I2C_SDA_MAX10,16

I2C_SCL_MAX10,16

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

8 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

8 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

8 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

J181

2345

R135 0

J101

2 3 4 5J191

2345

R54 DNI

R136DNI

R58 4.99K

R138DNI

R57 180K

R63 0

C65 0.1uF

R59 4.99K

R60

DNI

R1370 R61 0

C66

10uF

C53 1000pF

C50 0.1uF

C64 0.1uF

C62

0.1uF

X3

Si571

OE2

VC1

GND3

CLK+4

CLK-5

VDD6

SDA7

SCL8

R62DNI

Cyclone V GX SoC Transceiver

GXB_LO

GXB_L1

GXB_L2

5CSXFC6D_F896

U21M

REFCLK0LnW7 REFCLK0LpW8

GXB_RX_L0n,GXB_REFCLK_L0nAE1 GXB_RX_L0p,GXB_REFCLK_L0pAE2

GXB_TX_L0pAD4

GXB_TX_L0nAD3

GXB_RX_L1n,GXB_REFCLK_L1nAC1 GXB_RX_L1p,GXB_REFCLK_L1pAC2

GXB_TX_L1pAB4

GXB_TX_L1nAB3

GXB_RX_L2n,GXB_REFCLK_L2nAA1 GXB_RX_L2p,GXB_REFCLK_L2pAA2

GXB_TX_L2pY4

GXB_TX_L2nY3

GXB_RX_L3n,GXB_REFCLK_L3nW1 GXB_RX_L3p,GXB_REFCLK_L3pW2

GXB_TX_L3pV4

GXB_TX_L3nV3

GXB_TX_L4nT3GXB_TX_L4pT4

GXB_RX_L5p,GXB_REFCLK_L5pR2

GXB_RX_L5n,GXB_REFCLK_L5nR1

GXB_TX_L5nP3GXB_TX_L5pP4

REFCLK2LpP9

REFCLK2LnP8

GXB_RX_L6p,GXB_REFCLK_L6pN2

GXB_RX_L6n,GXB_REFCLK_L6nN1

GXB_TX_L6nM3GXB_TX_L6pM4

GXB_TX_L7nK3GXB_TX_L7pK4

GXB_RX_L8p,GXB_REFCLK_L8pJ2

GXB_RX_L8n,GXB_REFCLK_L8nJ1

GXB_TX_L8nH3GXB_TX_L8pH4

GXB_RX_L4n,GXB_REFCLK_L4nU1 GXB_RX_L4p,GXB_REFCLK_L4pU2

REFCLK1LpT9

REFCLK1LnT8

GXB_RX_L7p,GXB_REFCLK_L7pL2

GXB_RX_L7n,GXB_REFCLK_L7nL1

RREF_TLG1

R413

2.0K

1%

J111

2 3 4 5

Page 9: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Cyclone V GX SoC Clocks

1.5 Volt

1.5 Volt

2.5 Volt

2.5 Volt

HSMA_CLK_IN0

HSMA_CLK_IN_P2 HSMA_CLK_IN_N2

HSMA_CLK_OUT0HSMA_CLK_IN_P2HSMA_CLK_IN_N2

DDR3_FPGA_A3DDR3_FPGA_A2

CLK_ENET_FPGA_P

CLK_TOP1CLK_100M_FPGA

CLK_50M_FPGA

PCIE_SMBDAT

PCIE_SMBCLK PCIE_SMBCLK

CLK_ENET_FPGA_N

CLK_BOT1

USER_LED_FPGA2

USER_LED_FPGA3

USER_LED_FPGA1

CLK_ENET_FPGA_PHY

CLK_ENET_FPGA_P 10

CLK_TOP1 10

CLK_BOT1 10

CLK_50M_FPGA 10

CLK_100M_FPGA 10

HSMA_CLK_OUT017

HSMA_CLK_IN0 17

HSMA_CLK_IN_P2 17HSMA_CLK_IN_N2 17

DDR3_FPGA_A[14:0]4,13

PCIE_SMBDAT 3

PCIE_SMBCLK3

CLK_ENET_FPGA_N 10

USER_LED_FPGA[3:0]4,23

PCIE_PRSNT2_X1 3

PCIE_PRSNT2_X4 3

CLK_ENET_FPGA_PHY10

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

9 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

9 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

9 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R456DNI

R412 100, 1%

Cyclone V GX SoC Clocks

Bank 3B

Bank 4A

Bank 5B

Bank 8A

5CSXFC6D_F896

U21N

CLK1n,DIFFIO_RX_B39nY16

CLK1p,DIFFIO_RX_B39pW15

CLK2n,DIFFIO_RX_B47nAB17

CLK2p,DIFFIO_RX_B47pAA16

CLK5p,DIFFIO_RX_R21p,DQS3RAA26

FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB,DIFFIO_TX_R22pAE29

CLK3n,DIFFIO_RX_B55nAD17

CLK3p,DIFFIO_RX_B55pAC18

CLK4p,FPLL_BR_FBp,DIFFIO_RX_R23p,DQ3RY26

CLK4n,FPLL_BR_FBn,DIFFIO_RX_R23n,DQ3RY27

FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn,DIFFIO_TX_T4n,DQ1TA10CLK7p,DIFFIO_RX_T1p

H15

CLK7n,DIFFIO_RX_T1nG15

CLK0p,FPLL_BL_FBp,DIFFIO_RX_B31pAF14 CLK0n,FPLL_BL_FBn,DIFFIO_RX_B31nAF15

FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB,DIFFIO_TX_B37p,DQ5B,B_A_2AH12

FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn,DIFFIO_TX_B37n,DQ5B,B_A_3AJ12

CLK5n,DIFFIO_RX_R21n,DQSn3RAB27

FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn,DIFFIO_TX_R22n,DQ3RAD29

CLK6p,FPLL_TL_FBp,DIFFIO_RX_T9pK14

CLK6n,FPLL_TL_FBn,DIFFIO_RX_T9nJ14 FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB,DIFFIO_TX_T4p,DQ1T

A11

R453 0

Page 10: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Si570 Programmable OscillatorUse Clock Control GUI(Default 100MHz)I2C Address 66 HEX

PLL

OSC1_CLK_SEL = HIGH selects (OSC1_CLK_SMA) SMA inputOSC1_CLK_SEL = LOW selects (OSC1_CLK_SYN) Si5356A input

CMOS

Si5356 Programmable Oscillator Use Clock Control GUI (Defaults 25MHz,25MHz,25MHz,25MHz, 100MHz, 100MHz,50MHz, 50MHz)I2C Address 70 HEX

DanP:Consider to remove ac couplingl

DanP:Consider to DNI termination

25Mhz

25Mhz

100MHz

156.25MHz

25Mhz

25Mhz

100Mhz

100Mhz

I2C_SDA_MAXI2C_SCL_MAX

REFCLK_QL2_C_N

REFCLK_QL2_C_P

SI570_EN

OSC1_CLK_SYN

OSC1_CLK_SMA

2.5V_CLK_MUX

CLKIN_50

CLK125A_EN

CLK125A_EN

OSC1_CLK_SEL

CLK_DIFF1_N

CLK_DIFF1_P

CLK_DIFF2_N

CLK_DIFF2_P

PCIE_REFCLK_SYN_N

PCIE_REFCLK_SYN_P

PCIE_REFCLK_QL0_N

PCIE_REFCLK_QL0_P

3.3V

2.5V_REG_HPS

1V81V8

1V8

1V8

2.5V_PLL1

2.5V_PLL1

2.5V_PLL12.5V_PLL1

2.5V_REG_HPS

2.5V_REG_HPS

1V8

1V8

1V8

1V8_PLL

1V8_PLL

2.5V_REG_HPS2.5V_REG_HPS

1V8

2.5V_REG_HPS

2.5V_REG_HPS

1V8 2.5V_REG_HPS

2.5V_REG_HPS

2.5V_PLL1

2.5V_REG_HPS

2.5V_REG_HPS

2.5V_REG_HPS

SI570_EN12,16

REFCLK_QL2_N 8

REFCLK_QL2_P 8

CLK_BOT1 9

CLK_TOP1 9

CLK_OSC2 6

OSC1_CLK_SEL CLK_OSC1 6

CLK50_EN16

CLK_50M_FPGA 9

CLK_50M_MAX 16

CLK_ENET_FPGA_P9

CLK_ENET_FPGA_N9

I2C_SDA_MAX8,10,16

I2C_SCL_MAX8,10,16

CLK125A_EN 12,16

PCIE_REFCLK_SYN_N 3

PCIE_REFCLK_SYN_P 3

PCIE_REFCLK_QL0_P 8

PCIE_REFCLK_QL0_N 8

I2C_SCL_MAX8,10,16

I2C_SDA_MAX8,10,16

CLK_DUAL_ENET_PHY 19

CLK_ENET_FPGA_PHY 9

CLK_100M_FPGA 9

CLK_100M_MAX 16

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

10 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

10 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

10 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

U29

Si5338A-CUSTOM

CLKIN_P1

CLKIN_N2

CLKIN3

I2C_LSB4

FDBK_P5

FDBK_N6

VDD17

VDD224

VDDO311

VDDO215

VDDO116

VDDO020

INTR8

CLK3B9

CLK3A10SCL

12

CLK2B13

CLK2A14

CLK1B17

CLK1A18

SDA19

CLK0B21

CLK0A22

RSVD_GND23

EPAD25

J13

CON2

12

C95

0.1uF

C214

0.1uF

R436 1.00K

R2540

C83

0.1uF

C391

0.1uF

C483

0.1uF

C18 0.1uF

R71 10K

TP7

R741.00K

R72 22

C207 DNI

C7

2.2uF

R2510

C504

0.1uF

R7 DNIC11

0.1uF

C89 DNI

Y4

25.00MHz

13

24

R250

DNI

C674

0.1uF

C464

10uFC101 DNI

C362

0.1uF

R18 100, 1%

C392

0.1uF

C484

0.1uF

C114

0.1uF

C361

2.2uF

C134 DNI

R109 DNI

U52

ICS83054I-01

Clk_in010

Clk_in17

SEL31

SEL26

SEL111

SEL016

VD

D8

VS

S0

4

Q32

Q25

Q112

Q015

VD

DQ

114

VD

DQ

03

EN9

VS

S1

13

R14 DNI

R103DNI

C155

0.1uF

C169

0.1uF

C84

0.1uF

C211

2.2uF

J36

LTI-SASF546-P26-X11

2345

R2530

L27

742792780

C102

0.1uF

R111 1.00K

C142

0.1uF

C19 0.1uF

R2490

X5

125.0MHz

EN1

NC2

GND3

OUT4

OUTn5

VCC6

C113

0.1uF

R64 22

C115

0.1uF

L29

742792780

R263DNI

Y2

25.00MHz

13

24

C206 DNI

R252DNI

PLL

U49

Si52112

VSS25

DIFF16

DIFF28

DIFF29

XIN/CLKIN3

XOUT2

VDD1

VSS4

DIFF17

VDD210

C503

0.1uF

C465

0.1uF

C153

0.1uF

L7

742792780

X1

SI570

OE2

NC1

GND3

CLK+4

CLK-5

VCC6

SDA7

SCL8

U23

SL18860DC

CLKIN3 CLKOUT1

8

CLKOUT29

GND1

CLKOUT310

VDD2

OE16

OE_OSC4

OE27

OE35

C679

0.1uF

U35

Si5335

XA_CLKIN1

XB_CLKINB2

P33

GND4

P55

P66

VDD7VDD24

VDDO311VDDO215VDDO116VDDO020

LOS8

CLK3B9CLK3A10

P112

CLK2B13CLK2A14

CLK1B17CLK1A18

P219

CLK0B21CLK0A22

RSVD_GND23

EPAD25

C135 DNI

R556 22

R13 1.00K

C154

0.1uF

C165

0.1uF

X4

50MHz

VCC4

GND2

OUT3

EN1

Y3

25.00MHz

13

24

R110 DNI

Page 11: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Cyclone V GX SoC Configuration

USER I/O INTERFACES

2.5V BANK

2.5V BANK

2.5V BANK

FPGA_nSTATUS

FPGA_CONFIG_D7

FPGA_CONFIG_D0FPGA_CONFIG_D1FPGA_CONFIG_D2FPGA_CONFIG_D3FPGA_CONFIG_D4FPGA_CONFIG_D5FPGA_CONFIG_D6

FPGA_CONF_DONE

FPGA_CONFIG_D8FPGA_CONFIG_D9FPGA_CONFIG_D10FPGA_CONFIG_D11FPGA_CONFIG_D12FPGA_CONFIG_D13FPGA_CONFIG_D14FPGA_CONFIG_D15

MSEL0MSEL1MSEL2MSEL3MSEL4

FPGA_DCLK

FPGA_nCONFIG

JTAG_FPGA_TDI

MAX_FPGA_SCK

MAX_FPGA_SSEL

MAX_FPGA_MOSI

MAX_FPGA_MISO

2.5V_REG_FPGA

2.5V_REG_FPGA

2.5V_REG_FPGA

FPGA_CONFIG_D[15:0]15,16

CPU_RESETn16,23

FPGA_DCLK15,16

FPGA_nCONFIG16

FPGA_PR_REQUEST 16

FPGA_PR_DONE 16

FPGA_PR_READY 16

FPGA_PR_ERROR 16

FPGA_CvP_CONFDONE 16

MSEL016

MSEL116

MSEL216

MSEL316

MSEL416

FPGA_CONF_DONE16

FPGA_nSTATUS16

JTAG_FPGA_TDI12JTAG_FPGA_TDO12

JTAG_FPGA_TMS12JTAG_MUX_TCK12,16,17

MAX_FPGA_MOSI 16

MAX_FPGA_MISO 16

MAX_FPGA_SSEL16

MAX_FPGA_SCK16

PCIE_PERSTn 3,4

PCIE_WAKEn 3

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

11 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

11 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

11 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R304 1.00k

R306 1.00k

C463 DNI

R305 1.00k

R411 10K

Cyclone V GX SoC Configuration

Bank 3A

Bank 5A

Bank 9A

5CSXFC6D_F896

U21G

nCEO,DIFFIO_TX_R3p,DQ1RAJ29

DATA12,DIFFIO_RX_B3p,DQS1BAC9

DEV_OE,DIFFIO_TX_R5pAE26 nPERSTL0,DIFFIO_RX_R6p,DQS1R

W21

CvP_CONFDONE,DIFFIO_TX_R3n,DQ1RAH29

TDOAB9

AS_DATA2,DATA2AE8

nCSO,DATA4AB8

TMSV9

AS_DATA3,DATA3AC7

TCKAC5

nCEG5

nSTATUSF4

PR_DONE,DIFFIO_RX_B7nAF5

MSEL1K6

DATA15,DIFFIO_TX_B6p,DQ1BAG3

DATA11,DIFFIO_TX_B4pAE11

DATA13,DIFFIO_TX_B6n,DQ1BAH4

DATA14,DIFFIO_RX_B5n,DQ1BAE7

CLKUSR,DIFFIO_RX_B5p,DQ1BAD7

PR_READY,DIFFIO_TX_B8n,DQ1BAG8

MSEL2G6

PR_ERROR,DIFFIO_RX_B7pAF4

MSEL3L7nCONFIG

J5

INIT_DONE,DIFFIO_RX_R2pAD25

PR_REQUEST,DIFFIO_TX_R1n,DQ1RAH28

MSEL4L9

CRC_ERROR,DIFFIO_RX_R2nAC25

AS_DATA1,DATA1AE5

TDIU8

AS_DATA0,ASDO,DATA0AE6

DCLKU7

DATA5,DIFFIO_TX_B2nAE9

DATA6,DIFFIO_RX_B1n,DQ1BAE12

DATA7,DIFFIO_TX_B2p,DQ1BAD9

DATA8,DIFFIO_RX_B1p,DQ1BAD11

DATA9,DIFFIO_TX_B4n,DQ1BAF10

DATA10,DIFFIO_RX_B3n,DQSn1BAD10

DEV_CLRn,DIFFIO_TX_R5n,DQ1RAD27

nPERSTR0,DIFFIO_RX_R6n,DQSn1RW22

MSEL0L8

CONF_DONEF3

R4

58

10K

R4

48

10K

R4

57

10K

R414 10K

R397 10K

R415 10K

OPEN

SW3

TDA06H0SB1

123456 7

89101112

R303 1.00k

R433 DNI

R4

59

10K

R302 1.00k

R432

DNI

Page 12: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

JTAG(uses JTAG mode only)

USB Blaster Programming Header

JTAG Chain Control

ON = not-in-chainOFF = in-chain

TS5A23157 Switch FunctionsWhen Pins 1 & 5 are:LOW --> NC to/from COM = ON and NO to/from COM = OFFHIGH --> NC to/from COM = OFF and NO to/from COM = ON

Logic 0 = pin 10 <--> pin 9 (HPS Bypass)Logic 1 = pin 10 <--> pin 2 (HPS Enable)

Logic 0 = pin 6 <--> pin 7 (HPS Bypass)Logic 1 = pin 6 <--> pin 4 (HPS Enable)

Logic 0 = pin 10 <--> pin 9 (HSMA Bypass)Logic 1 = pin 10 <--> pin 2 (HSMA Enable)

Logic 0 = pin 6 <--> pin 7 (HSMA Bypass)Logic 1 = pin 6 <--> pin 4 (HSMA Enable)

Logic 0 = pin 10 <--> pin 9 (FPGA Bypass)Logic 1 = pin 10 <--> pin 2 (FPGA Enable)

Logic 0 = pin 6 <--> pin 7 (FPGA Bypass)Logic 1 = pin 6 <--> pin 4 (FPGA Enable)

Populate R58 if you would like toMaster the JTAG chain throughHSMA

Logic 0 = pin 6 <--> pin 7 (HSMBBypass)Logic 1 = pin 6 <--> pin 4 (HSMB Enable)

Logic 0 = pin 10 <--> pin 9 (MAX II Bypass)Logic 1 = pin 10 <--> pin 2 (MAX II Enable)

1 0

1 0

1 0

1 0

1 0

1 0

JTAG_BLASTER_TDI

HSMA_JTAG_EN

HPS_JTAG_ENFPGA_JTAG_EN

MAX_JTAG_EN

JTAG_HSMA_TDI

BP_FPGA_TMS

BP_HPS_TMS

BP_HSMA_TMS

JTAG_BLASTER_TDO JTAG_BLASTER_TDI

SI570_ENFACTORY_LOAD

CLK125A_EN

SECURITY_MODE

JTAG_SELJTAG_MICTOR_TDO

JTAG_MICTOR_TDI

HSMA_JTAG_EN

HPS_JTAG_EN

FPGA_JTAG_EN

MAX_JTAG_EN

HPS_JTAG_EN

FPGA_JTAG_EN

HSMA_JTAG_EN

BP_MAX_TMS

JTAG_MAX_TDI

MAX_JTAG_EN

JTAG_MUX_TMS

JTAG_MUX_TMS

JTAG_MUX_TMS

JTAG_MUX_TMS

JTAG_MUX_TDO

JTAG_MUX_TCK

JTAG_HPS_SEL

JTAG_MUX_TMS

JTAG_FPGA_TDI

JTAG_MUX_HPS_TDI

JTAG_BLASTER_TDO

JTAG_TMS

JTAG_BLASTER_TDI

JTAG_TCK

JTAG_MICTOR_TCK

JTAG_MICTOR_TMS

JTAG_MUX_TDO

JTAG_MUX_TDI

JTAG_MUX_TMS

JTAG_MUX_TCK

JTAG_MICTOR_TCK

JTAG_MICTOR_TMS

JTAG_MICTOR_TDO

JTAG_MICTOR_TDI

JTAG_MUX_TCKJTAG_MICTOR_TCK

JTAG_HPS_TCKJTAG_HPS_TCK

JTAG_MUX_TMSJTAG_MICTOR_TMS

JTAG_HPS_TMSJTAG_HPS_TMS

JTAG_MUX_HPS_TDIJTAG_MICTOR_TDO

JTAG_HPS_TDIJTAG_HPS_TDI

JTAG_FPGA_TDIJTAG_MICTOR_TDI

JTAG_HPS_TDOJTAG_HPS_TDO

JTAG_MICTOR_TDO

JTAG_MICTOR_TDI

JTAG_BLASTER_TDO

JTAG_TMS

JTAG_BLASTER_TDI

JTAG_TCKJTAG_MICTOR_TCK

JTAG_MICTOR_TMS

JTAG_MUX_TCKJTAG_MUX_TCK

JTAG_MUX_TMSJTAG_MUX_TMS

JTAG_MUX_TDIJTAG_MUX_TDI

JTAG_MUX_TDOJTAG_MUX_TDO

JTAG_MAX_TDO

JTAG_MUX_TMS

JTAG_MUX_TMS

JTAG_HSMA_TDO

JTAG_MUX_TMS

JTAG_FPGA_TDOJTAG_FPGA_TDI

JTAG_HSMA_TDI

JTAG_MAX_TDI

BP_MAX_TMS

BP_HSMA_TMS

BP_FPGA_TMS

BP_HPS_TMS

JTAG_MUX_TDOJTAG_MUX_TDO

JTAG_HPS_TMS

JTAG_FPGA_TMSJTAG_FPGA_TMS

JTAG_HSMA_TMSJTAG_HSMA_TMS

JTAG_MAX_TMSJTAG_MAX_TMS

JTAG_MUX_HPS_TDI HPS FPGA

HSMA

MAX

MUX

FPGA

HSMA

MAXHPS

MUXHSMA

MAX

MUX

FACTORY_LOADSECURITY_MODE

CLK125A_ENSI570_EN

JTAG_SEL

JTAG_HPS_SEL

JTAG_HPS_SEL

JTAG_SEL

1V8

3.3V

3.3V

2.5V_REG_HPS2.5V_REG_HPS 2.5V_REG_HPS

2.5V_REG_HPS

2.5V_REG_HPS

2.5V_REG_HPS

2.5V_REG_HPS

2.5V_REG_HPS

2.5V_REG_HPS

2.5V_REG_HPS

2.5V_REG_HPS

2.5V_REG_HPS

2.5V_REG_HPS

3.3V

3.3V

3.3V

3.3V

JTAG_TCK 12,25

JTAG_TMS 12,25

JTAG_BLASTER_TDO 12,25

JTAG_HSMA_TDO17

JTAG_HSMA_TMS 17

JTAG_FPGA_TMS 11

JTAG_FPGA_TDO11

JTAG_HPS_TMS 6,12

USB_DISABLEn25

JTAG_MICTOR_TDO 6,12

JTAG_MICTOR_TDI 6,12

JTAG_MAX_TDO16

JTAG_MAX_TMS 16

JTAG_MUX_TCK11,12,16,17

JTAG_HPS_TDO 6

JTAG_HPS_TDI 6

JTAG_MUX_TMS12

JTAG_MUX_HPS_TDI

JTAG_TCK 12,25

JTAG_MICTOR_TCK 6,12

JTAG_TMS 12,25

JTAG_MICTOR_TMS 6,12

JTAG_BLASTER_TDI 25

JTAG_BLASTER_TDO 12,25

JTAG_MUX_TDI12

JTAG_MUX_TMS12

JTAG_MUX_TCK11,12,16,17

JTAG_HPS_TCK 6

JTAG_HPS_TMS 6,12

JTAG_FPGA_TDI 11,12

JTAG_MICTOR_TCK 6,12

JTAG_MICTOR_TMS 6,12

JTAG_MICTOR_TDO 6,12

JTAG_MICTOR_TDI 6,12

JTAG_FPGA_TDI11,12

JTAG_FPGA_TDI11,12

JTAG_HSMA_TDI 17

JTAG_MAX_TDI 16

JTAG_MUX_TDI 12

MICTOR_RSTn6,16,21

JTAG_TRST 6,16

FACTORY_LOAD16SECURITY_MODE16

CLK125A_EN 10,16SI570_EN 10,16

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

12 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

12 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

12 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R399 DNIR398 DNI

R240

C40

2.2uF

R344 DNI

R31 1.00k

OPEN

SW4

TDA04H0SB1

1234 5

678

R380 DNI

R400 DNI

U10

TS5A23157

IN11

NO12

GND3

NO24

IN25

COM26

NC27

V+8

NC19

COM110

R387 DNI

R317 10.0K

R343 DNI

R351 DNI

R382 DNI

R212 1.00k

R355 DNI

R2090

R404 DNI

R323 1.00k

J7

CON2

12

U15

IDTQS3VH257

I0A2

I0B5

I1A3

I0C11

I1B6

I1C10

I0D14

I1D13

YA4

YB7

YC9

YD12

S1

E15

GND8

VCC16

R201 1.00k

R346 DNI

R381 DNI

C41

0.1uF

R386 DNI

R345 DNI

C265 0.1uF

R27 1.00k

U9

TS5A23157

IN11

NO12

GND3

NO24

IN25

COM26

NC27

V+8

NC19

COM110

R300

J6

CON2

12

R403 DNI

R29 1.00k

OPEN

SW2

TDA04H0SB1

12345

678

C39

0.1uF

J23

70247-1051

2468

10

13579

R280

R405 DNI

R210 1.00k

U8

TS5A23157

IN11

NO12

GND3

NO24

IN25

COM26

NC27

V+8

NC19

COM110

XJ6

881545-2

C266 0.1uF

U16

IDTQS3VH257

I0A2

I0B5

I1A3

I0C11

I1B6

I1C10

I0D14

I1D13

YA4

YB7

YC9

YD12

S1

E15

GND8

VCC16

R400

R361 DNI

R352 DNI

R287 10.0K

R325 1.00k

R357 DNI

R359 DNI

R360 DNI

R385 DNI

R308 10.0K

R25 1.00k

U7

TS5A23157

IN11

NO12

GND3

NO24

IN25

COM26

NC27

V+8

NC19

COM110

R356 DNI

R202 DNI

R43 1.00k

R402 DNI

R353 DNI

XJ5

881545-2

R354 DNI

R260

R44 1.00k

R384 DNI

R322 1.00k

R358 DNI

R324 1.00k

R401 DNI

C264 0.1uF

R307 10.0K

C263 0.1uF

C38

2.2uF

R383 DNI

Page 13: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

1024MB DDR3 (x32) - FPGADDR3_FPGA_CLK_P DDR3_FPGA_CLK_N

DDR3_FPGA_DQ23

DDR3_FPGA_DQ16

DDR3_FPGA_DQS_P2

DDR3_FPGA_DQ24

DDR3_FPGA_DQS_P3DDR3_FPGA_DQS_N3

DDR3_FPGA_DQS_N2

DDR3_FPGA_DQ20

DDR3_FPGA_DQ31

DDR3_FPGA_DQ19

DDR3_FPGA_DQ22

DDR3_FPGA_DQ27

DDR3_FPGA_DM3DDR3_FPGA_DM2

DDR3_FPGA_CLK_P

DDR3_FPGA_ZQ1

DDR3_FPGA_CASnDDR3_FPGA_RASnDDR3_FPGA_WEnDDR3_FPGA_CSn

DDR3_FPGA_BA2

DDR3_FPGA_ODTDDR3_FPGA_RESETn

DDR3_FPGA_BA1

DDR3_FPGA_CKE

DDR3_FPGA_BA0

DDR3_FPGA_CLK_N

DDR3_FPGA_DQ7

DDR3_FPGA_DQ0

DDR3_FPGA_DQS_P0

DDR3_FPGA_DQ13DDR3_FPGA_DQ14

DDR3_FPGA_DQ8

DDR3_FPGA_DQ2

DDR3_FPGA_DQS_P1DDR3_FPGA_DQS_N1

DDR3_FPGA_DQS_N0

DDR3_FPGA_DQ10

DDR3_FPGA_DQ4

DDR3_FPGA_DQ15

DDR3_FPGA_DQ9

DDR3_FPGA_DQ3

DDR3_FPGA_DQ1

DDR3_FPGA_DQ12

DDR3_FPGA_DQ6

DDR3_FPGA_DQ11

DDR3_FPGA_DQ5

DDR3_FPGA_DM1DDR3_FPGA_DM0

DDR3_FPGA_CLK_P

DDR3_FPGA_ZQ

DDR3_FPGA_CASnDDR3_FPGA_RASnDDR3_FPGA_WEnDDR3_FPGA_CSn

DDR3_FPGA_BA2

DDR3_FPGA_ODTDDR3_FPGA_RESETn

DDR3_FPGA_BA1

DDR3_FPGA_CKE

DDR3_FPGA_BA0

DDR3_FPGA_CLK_N

DDR3_FPGA_RESETn

DDR3_FPGA_A14

DDR3_FPGA_A12

DDR3_FPGA_A7

DDR3_FPGA_A2

DDR3_FPGA_A6

DDR3_FPGA_A3

DDR3_FPGA_A13

DDR3_FPGA_A8

DDR3_FPGA_A1

DDR3_FPGA_A11

DDR3_FPGA_A5

DDR3_FPGA_A10

DDR3_FPGA_A4

DDR3_FPGA_A9

DDR3_FPGA_A0

DDR3_FPGA_A7

DDR3_FPGA_A3

DDR3_FPGA_A8

DDR3_FPGA_A13

DDR3_FPGA_A6

DDR3_FPGA_A12

DDR3_FPGA_A2

DDR3_FPGA_A9

DDR3_FPGA_A14

DDR3_FPGA_A4

DDR3_FPGA_A10

DDR3_FPGA_A5

DDR3_FPGA_A11

DDR3_FPGA_A1DDR3_FPGA_A0

DDR3_FPGA_DQ17

DDR3_FPGA_DQ18

DDR3_FPGA_DQ21

DDR3_FPGA_DQ29DDR3_FPGA_DQ30

DDR3_FPGA_DQ25DDR3_FPGA_DQ26

DDR3_FPGA_DQ28

DDR3_FPGA_CKE

DDR3_FPGA_CSn DDR3_FPGA_BA0DDR3_FPGA_A3 DDR3_FPGA_A0

DDR3_FPGA_A5 DDR3_FPGA_A2

DDR3_FPGA_A7DDR3_FPGA_A9 DDR3_FPGA_A13 DDR3_FPGA_WEnDDR3_FPGA_ODT DDR3_FPGA_CASn DDR3_FPGA_RASnDDR3_FPGA_A14

DDR3_FPGA_A11 DDR3_FPGA_A8DDR3_FPGA_A1 DDR3_FPGA_A4 DDR3_FPGA_A12DDR3_FPGA_BA1 DDR3_FPGA_A10

DDR3_FPGA_BA2

DDR3_FPGA_A6VTT_FPGA_DDR3

VTT_FPGA_DDR3

VTT_FPGA_DDR3

VTT_FPGA_DDR3VTT_FPGA_DDR3

VTT_FPGA_DDR3

VREF_FPGA_DDR3 VREF_FPGA_DDR3

1.5V_REG_FPGA

1.5V_REG_FPGA

1.5V_REG_FPGA

1.5V_REG_FPGA

1.5V_REG_FPGA

DDR3_FPGA_DM[3:0]4

DDR3_FPGA_BA[2:0]4

DDR3_FPGA_DQS_P[3:0]4

DDR3_FPGA_DQS_N[3:0]4

DDR3_FPGA_A[14:0]4,9

DDR3_FPGA_DQ[31:0]4

DDR3_FPGA_CKE 4

DDR3_FPGA_CLK_P 4

DDR3_FPGA_CLK_N 4

DDR3_FPGA_DM2 4

DDR3_FPGA_DM3 4

DDR3_FPGA_CSn 4

DDR3_FPGA_WEn 4

DDR3_FPGA_RASn 4

DDR3_FPGA_CASn 4

DDR3_FPGA_BA0 4

DDR3_FPGA_BA1 4

DDR3_FPGA_BA2 4

DDR3_FPGA_RESETn4

DDR3_FPGA_ODT 4

DDR3_FPGA_DM0 4

DDR3_FPGA_DM1 4

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

13 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

13 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

13 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.C575

0.47uF

V34

V32

C574

4.7nF

DDR3 DeviceU38

MT41K256M16HA-125:E

A5P2 A4P8 A3N2 A2P3 A1P7 A0N3

NC4L9

A10/APL7

A11R7

A12/BCnN7

RESETnT2

VSSQB1

VSSQB9

VSSQD1

A9R3 A8T8 A7R2 A6R8

NC5M7

NC1J1

NC3L1

ZQL8

CK_NK7

WEL3

CKEK9

A13T3

ODTK1

NC2J9

RASJ3

CK_PJ7

CSL2

BA0M2

BA1N8

BA2M3

CASK3

UDMD3

A14T7

LDME7

VDDB2

VDDD9

VDDG7

VDDK2

VSSA9

VSSB3

VSSE1

VSSG8

DQ0E3

LDQS_PF3

DQ1F7

DQ2F2

DQ3F8

DQ4H3

DQ5H8

DQ6G2

DQ7H7

DQ8D7

DQ9C3

DQ10C8

DQ11C2

DQ12A7

DQ13A2

DQ14B8

DQ15A3

UDQS_PC7LDQS_NG3

UDQS_NB7

VSSQD8

VSSQE2

VSSQE8

VSSQF9

VDDQH9

VDDK8

VDDN1

VDDN9

VDDR1

VDDR9

VREFDQH1

VREFCAM8

VSSQG1

VSSQG9

VDDQA1

VDDQA8

VDDQC1

VDDQC9

VDDQD2

VDDQE9

VDDQF1

VDDQH2

VSSJ2

VSSJ8

VSSM1

VSSM9

VSSP1

VSSP9

VSST1

VSST9

C597

3.3nF

C599

0.01uF

V23

V28

C586

0.1uF

RN4H 518 9V29

V18RN6H 518 9

RN5G 517 10

C583

3.3nF

V17

C585

2.2nF

V30

C588

0.47uF

RN4F 516 11

R471

240

V38

RN6F 516 11

RN4A 511 16

RN6D 514 13

V20

V36

RN4B 512 15

C589

2.2nF

RN6A 511 16RN5E 515 12

C569

2.2nF

V10

C598

2.2nF

RN4E 515 12

C572

2.2nF

C590

0.1uF

C577

0.1uF

RN6B 512 15

V27R472 4.70K, 1%

C576

0.1uF

V15

CN5

0.1uF

1234 5

678

C568

2.2nF

V26

RN4C 513 14

C602

2.2nF

C571

2.2nF

V12RN5B 512 15

C603

0.01uF

RN5H 518 9

C600

0.01uF

V33

V37

R469100, 1%

V35

C601

2.2nF

RN4G 517 10RN5C 513 14

R473

240

RN6G 517 10

C570

4.7nF

V16RN5F 516 11

V31

RN6E 515 12

RN5A 511 16RN5D 514 13

DDR3 DeviceU37

MT41K256M16HA-125:E

A5P2 A4P8 A3N2 A2P3 A1P7 A0N3

NC4L9

A10/APL7

A11R7

A12/BCnN7

RESETnT2

VSSQB1

VSSQB9

VSSQD1

A9R3 A8T8 A7R2 A6R8

NC5M7

NC1J1

NC3L1

ZQL8

CK_NK7

WEL3

CKEK9

A13T3

ODTK1

NC2J9

RASJ3

CK_PJ7

CSL2

BA0M2

BA1N8

BA2M3

CASK3

UDMD3

A14T7

LDME7

VDDB2

VDDD9

VDDG7

VDDK2

VSSA9

VSSB3

VSSE1

VSSG8

DQ0E3

LDQS_PF3

DQ1F7

DQ2F2

DQ3F8

DQ4H3

DQ5H8

DQ6G2

DQ7H7

DQ8D7

DQ9C3

DQ10C8

DQ11C2

DQ12A7

DQ13A2

DQ14B8

DQ15A3

UDQS_PC7LDQS_NG3

UDQS_NB7

VSSQD8

VSSQE2

VSSQE8

VSSQF9

VDDQH9

VDDK8

VDDN1

VDDN9

VDDR1

VDDR9

VREFDQH1

VREFCAM8

VSSQG1

VSSQG9

VDDQA1

VDDQA8

VDDQC1

VDDQC9

VDDQD2

VDDQE9

VDDQF1

VDDQH2

VSSJ2

VSSJ8

VSSM1

VSSM9

VSSP1

VSSP9

VSST1

VSST9

V11

CN4

0.1uF

1234 5

678

R4972.00K

C587

4.7nF

C584

0.47uF

RN6C 513 14

RN4D 514 13

C579

0.1uF

V25

C578

0.47uF

V19CN6

0.1uF

1234 5

678

C596

0.1uF

V24

Page 14: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

1024MB DDR3 (x32 + ECC) - HPS

DDR3 ECC TEST

DDR3_HPS_CLK_P DDR3_HPS_CLK_N

DDR3_HPS_DQS_P4DDR3_HPS_DQS_N4

DDR3_HPS_DQ34

DDR3_HPS_DQ36

DDR3_HPS_DM4

DDR3_HPS_ZQ1

DDR3_HPS_CLK_P

DDR3_HPS_CSnDDR3_HPS_WEnDDR3_HPS_RASnDDR3_HPS_CASn

DDR3_HPS_RESETnDDR3_HPS_ODT

DDR3_HPS_BA2

DDR3_HPS_CKE

DDR3_HPS_BA1

DDR3_HPS_CLK_N

DDR3_HPS_BA0

DDR3_HPS_A13

DDR3_HPS_A5

DDR3_HPS_A1

DDR3_HPS_A6

DDR3_HPS_A11

DDR3_HPS_A0

DDR3_HPS_A7

DDR3_HPS_A12

DDR3_HPS_A2

DDR3_HPS_A8

DDR3_HPS_A3

DDR3_HPS_A9

DDR3_HPS_A4

DDR3_HPS_A10

DDR3_HPS_A14

DDR3_HPS_DQS_P2

DDR3_HPS_DQS_P3DDR3_HPS_DQS_N3

DDR3_HPS_DQS_N2

DDR3_HPS_DQ28

DDR3_HPS_DM3DDR3_HPS_DM2

DDR3_HPS_CLK_P

DDR3_HPS_ZQ2

DDR3_HPS_CASnDDR3_HPS_RASnDDR3_HPS_WEnDDR3_HPS_CSn

DDR3_HPS_BA2

DDR3_HPS_ODTDDR3_HPS_RESETn

DDR3_HPS_BA1

DDR3_HPS_CKE

DDR3_HPS_BA0

DDR3_HPS_CLK_N DDR3_HPS_DQS_P0

DDR3_HPS_DQS_P1DDR3_HPS_DQS_N1

DDR3_HPS_DQS_N0

DDR3_HPS_DQ6

DDR3_HPS_DM1DDR3_HPS_DM0

DDR3_HPS_CLK_P

DDR3_HPS_ZQ

DDR3_HPS_CASnDDR3_HPS_RASnDDR3_HPS_WEnDDR3_HPS_CSn

DDR3_HPS_BA2

DDR3_HPS_ODTDDR3_HPS_RESETn

DDR3_HPS_BA1

DDR3_HPS_CKE

DDR3_HPS_BA0

DDR3_HPS_CLK_N

DDR3_HPS_RESETn

DDR3_HPS_A14

DDR3_HPS_A12

DDR3_HPS_A7

DDR3_HPS_A2

DDR3_HPS_A6

DDR3_HPS_A3

DDR3_HPS_A13

DDR3_HPS_A8

DDR3_HPS_A1

DDR3_HPS_A11

DDR3_HPS_A5

DDR3_HPS_A10

DDR3_HPS_A4

DDR3_HPS_A9

DDR3_HPS_A0

DDR3_HPS_A7

DDR3_HPS_A3

DDR3_HPS_A8

DDR3_HPS_A13

DDR3_HPS_A6

DDR3_HPS_A12

DDR3_HPS_A2

DDR3_HPS_A9

DDR3_HPS_A14

DDR3_HPS_A4

DDR3_HPS_A10

DDR3_HPS_A5

DDR3_HPS_A11

DDR3_HPS_A1DDR3_HPS_A0

DDR3_HPS_DQ15

DDR3_HPS_DQ14

DDR3_HPS_DQ8

DDR3_HPS_DQ9

DDR3_HPS_DQ10

DDR3_HPS_DQ11

DDR3_HPS_DQ13

DDR3_HPS_DQ14

DDR3_HPS_DQ15

DDR3_HPS_DQ12

DDR3_HPS_DQ0

DDR3_HPS_DQ2DDR3_HPS_DQ4

DDR3_HPS_DQ3

DDR3_HPS_DQ1

DDR3_HPS_DQ5DDR3_HPS_DQ7

DDR3_HPS_DQ23

DDR3_HPS_DQ16DDR3_HPS_DQ18

DDR3_HPS_DQ20

DDR3_HPS_DQ19DDR3_HPS_DQ17

DDR3_HPS_DQ22

DDR3_HPS_DQ21

DDR3_HPS_DQ24

DDR3_HPS_DQ29

DDR3_HPS_DQ30DDR3_HPS_DQ25DDR3_HPS_DQ26

DDR3_HPS_DQ31

DDR3_HPS_DQ27

DDR3_HPS_DQ39

DDR3_HPS_DQ32DDR3_HPS_DQ35

DDR3_HPS_DQ37DDR3_HPS_DQ38

DDR3_HPS_DQ33

DDR3_HPS_CKE

DDR3_HPS_A0

DDR3_HPS_A1

DDR3_HPS_A7

DDR3_HPS_A2

DDR3_HPS_A3

DDR3_HPS_A4

DDR3_HPS_A5

DDR3_HPS_A6DDR3_HPS_A8

DDR3_HPS_RASn

DDR3_HPS_A9

DDR3_HPS_ODT

DDR3_HPS_WEn

DDR3_HPS_A13

DDR3_HPS_BA2

DDR3_HPS_CSn

DDR3_HPS_A10

DDR3_HPS_CASn

DDR3_HPS_BA0

DDR3_HPS_A11DDR3_HPS_A14

DDR3_HPS_A12 DDR3_HPS_BA1

VTT_HPS_DDR3

VTT_HPS_DDR3

VTT_HPS_DDR3

VTT_HPS_DDR3VTT_HPS_DDR3

VTT_HPS_DDR3

VREF_HPS_DDR3 VREF_HPS_DDR3 VREF_HPS_DDR3

1.5V_REG_HPS 1.5V_REG_HPS 1.5V_REG_HPS

1.5V_REG_HPS

1.5V_REG_HPS

1.5V_REG_HPS

1.5V_REG_HPS

1.5V_REG_HPS

DDR3_HPS_DM[4:0]5

DDR3_HPS_BA[2:0]5

DDR3_HPS_DQS_P[4:0]5

DDR3_HPS_DQS_N[4:0]5

DDR3_HPS_A[14:0]5

DDR3_HPS_DQ[39:0]5

DDR3_HPS_CLK_P5

DDR3_HPS_CLK_N5

DDR3_HPS_CKE 5

DDR3_HPS_BA0 5

DDR3_HPS_BA1 5

DDR3_HPS_BA2 5

DDR3_HPS_RASn 5

DDR3_HPS_CASn 5

DDR3_HPS_WEn 5DDR3_HPS_CSn 5

DDR3_HPS_ODT 5DDR3_HPS_RESETn 5

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

14 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

14 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

14 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

CN2

0.1uF

1234 5

678

RN3E 515 12

RN2C 513 14

C365

0.01uF

C546

0.1uF

C310

4.7nF

C445

0.1uF

DDR3 DeviceU14

MT41K256M16HA-125:E

A5P2 A4P8 A3N2 A2P3 A1P7 A0N3

NC4L9

A10/APL7

A11R7

A12/BCnN7

RESETnT2

VSSQB1

VSSQB9

VSSQD1

A9R3 A8T8 A7R2 A6R8

NC5M7

NC1J1

NC3L1

ZQL8

CK_NK7

WEL3

CKEK9

A13T3

ODTK1

NC2J9

RASJ3

CK_PJ7

CSL2

BA0M2

BA1N8

BA2M3

CASK3

UDMD3

A14T7

LDME7

VDDB2

VDDD9

VDDG7

VDDK2

VSSA9

VSSB3

VSSE1

VSSG8

DQ0E3

LDQS_PF3

DQ1F7

DQ2F2

DQ3F8

DQ4H3

DQ5H8

DQ6G2

DQ7H7

DQ8D7

DQ9C3

DQ10C8

DQ11C2

DQ12A7

DQ13A2

DQ14B8

DQ15A3

UDQS_PC7LDQS_NG3

UDQS_NB7

VSSQD8

VSSQE2

VSSQE8

VSSQF9

VDDQH9

VDDK8

VDDN1

VDDN9

VDDR1

VDDR9

VREFDQH1

VREFCAM8

VSSQG1

VSSQG9

VDDQA1

VDDQA8

VDDQC1

VDDQC9

VDDQD2

VDDQE9

VDDQF1

VDDQH2

VSSJ2

VSSJ8

VSSM1

VSSM9

VSSP1

VSSP9

VSST1

VSST9

C327

0.47uF

CN1

0.1uF

1234 5

678

RN1B 512 15

C443

2.2nF

DDR3 DeviceU22

MT41K256M16HA-125:E

A5P2 A4P8 A3N2 A2P3 A1P7 A0N3

NC4L9

A10/APL7

A11R7

A12/BCnN7

RESETnT2

VSSQB1

VSSQB9

VSSQD1

A9R3 A8T8 A7R2 A6R8

NC5M7

NC1J1

NC3L1

ZQL8

CK_NK7

WEL3

CKEK9

A13T3

ODTK1

NC2J9

RASJ3

CK_PJ7

CSL2

BA0M2

BA1N8

BA2M3

CASK3

UDMD3

A14T7

LDME7

VDDB2

VDDD9

VDDG7

VDDK2

VSSA9

VSSB3

VSSE1

VSSG8

DQ0E3

LDQS_PF3

DQ1F7

DQ2F2

DQ3F8

DQ4H3

DQ5H8

DQ6G2

DQ7H7

DQ8D7

DQ9C3

DQ10C8

DQ11C2

DQ12A7

DQ13A2

DQ14B8

DQ15A3

UDQS_PC7LDQS_NG3

UDQS_NB7

VSSQD8

VSSQE2

VSSQE8

VSSQF9

VDDQH9

VDDK8

VDDN1

VDDN9

VDDR1

VDDR9

VREFDQH1

VREFCAM8

VSSQG1

VSSQG9

VDDQA1

VDDQA8

VDDQC1

VDDQC9

VDDQD2

VDDQE9

VDDQF1

VDDQH2

VSSJ2

VSSJ8

VSSM1

VSSM9

VSSP1

VSSP9

VSST1

VSST9

R450 240

RN1E 515 12

C364

2.2nF

C289

2.2nF

R462 10.0K

C493

0.1uF

C326

0.01uF

R452 240

R390

10.0K

C545

0.01uF

R451 240

C328

2.2nF

R438 10.0K

R425

240

C370

0.1uF

C446

0.01uF

R441 10.0K

R4312.00K

C491

2.2nF

RN1A 511 16

C369

3.3nF

C447

4.7nF

C497

0.47uF

RN1D 514 13

TP5

RN2D 514 13

C444

0.01uF

RN2B 512 15

C287

0.1uF

R465 10.0K

C309

0.1uF

RN3H 518 9

C294

0.1uF

C324

2.2nF

RN1F 516 11

C494

0.47uF

C325

0.01uF

C448

0.47uF

RN2F 516 11

C492

0.01uF

C311

2.2nF

RN3B 512 15RN2E 515 12

C520

2.2nF

C286

0.47uF

C367

0.1uF

RN1H 518 9

R463 10.0K

C284

0.01uF

TP3

CN3

0.1uF

1234 5

678

R428100, 1%

C285

0.1uF

C368

0.47uF

RN3G 517 10

C496

0.1uF

C547

0.01uF

C366

2.2nF

RN3D 514 13

R440 10.0K

C518

2.2nF

C549

2.2nF

RN2H 518 9

C506

0.1uF

C288

2.2nF

TP4

C283

2.2nF

C495

3.3nF

DDR3 DeviceU30

MT41K256M16HA-125:E

A5P2 A4P8 A3N2 A2P3 A1P7 A0N3

NC4L9

A10/APL7

A11R7

A12/BCnN7

RESETnT2

VSSQB1

VSSQB9

VSSQD1

A9R3 A8T8 A7R2 A6R8

NC5M7

NC1J1

NC3L1

ZQL8

CK_NK7

WEL3

CKEK9

A13T3

ODTK1

NC2J9

RASJ3

CK_PJ7

CSL2

BA0M2

BA1N8

BA2M3

CASK3

UDMD3

A14T7

LDME7

VDDB2

VDDD9

VDDG7

VDDK2

VSSA9

VSSB3

VSSE1

VSSG8

DQ0E3

LDQS_PF3

DQ1F7

DQ2F2

DQ3F8

DQ4H3

DQ5H8

DQ6G2

DQ7H7

DQ8D7

DQ9C3

DQ10C8

DQ11C2

DQ12A7

DQ13A2

DQ14B8

DQ15A3

UDQS_PC7LDQS_NG3

UDQS_NB7

VSSQD8

VSSQE2

VSSQE8

VSSQF9

VDDQH9

VDDK8

VDDN1

VDDN9

VDDR1

VDDR9

VREFDQH1

VREFCAM8

VSSQG1

VSSQG9

VDDQA1

VDDQA8

VDDQC1

VDDQC9

VDDQD2

VDDQE9

VDDQF1

VDDQH2

VSSJ2

VSSJ8

VSSM1

VSSM9

VSSP1

VSSP9

VSST1

VSST9

C371

0.47uF

C519

4.7nF

C517

2.2nF

C396

2.2nF

R439 10.0K

RN3F 516 11

RN2G 517 10

R447

240

RN3C 513 14

R389

10.0K

RN2A 511 16RN1G 517 10

C419

2.2nF

R372

240

C418

0.1uF

TP6

C420

2.2nF

RN1C 513 14

C548

0.47uF

RN3A 511 16

R464 10.0K

R420 4.70K, 1%

Page 15: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

FM BUS

FLASH, EPCQ

FLASH 512Mb (32M X 16)

- When using a single x16 flash device a word consists of 16 data bits so addressing starts with FM_A1 mapped to address bit 1 in software.

NOR PARALLEL FLASHEPCQ

FM_A1

FM_D0

FLASH_RESETn

FLASH_WEnFLASH_RDYBSYn

FLASH_WPn

FM_D1FM_D2FM_D3FM_D4FM_D5FM_D6FM_D7

FM_D8FM_D9FM_D10FM_D11FM_D12FM_D13FM_D14FM_D15

FM_A2FM_A3FM_A4FM_A5FM_A6FM_A7FM_A8FM_A9FM_A10FM_A11FM_A12FM_A13FM_A14FM_A15FM_A16FM_A17FM_A18FM_A19FM_A20FM_A21FM_A22FM_A23FM_A24FM_A25

FLASH_WPn

FM_A26

FPGA_CONFIG_D0FPGA_CONFIG_D1FPGA_CONFIG_D2FPGA_CONFIG_D3FPGA_CONFIG_D4

FPGA_AS_DATA0FPGA_AS_DATA1FPGA_AS_DATA2FPGA_AS_DATA3

FPGA_nCSO

LT1761_CSENSE

FPGA_nCSO

FPGA_AS_DATA0FPGA_AS_DATA1FPGA_AS_DATA2FPGA_AS_DATA3

1V8

1V8

1V8

1V81V8

3.3V

5.0V

VPP

1V8VPP

VPP

9V_VPP

12V9V_VPP

FM_A[26:1]16

FLASH_RDYBSYn 16

FM_D[15:0]16

FLASH_CLK16

FLASH_RESETn16FLASH_CEn016FLASH_OEn16FLASH_WEn16FLASH_ADVn16

FPGA_CONFIG_D111,16FPGA_CONFIG_D211,16FPGA_CONFIG_D311,16FPGA_CONFIG_D411,16

MAX_AS_CONF16

FPGA_CONFIG_D011,16

FPGA_DCLK 11,16

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

15 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

15 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

15 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

C315

0.1uF

R336 10K

C22

4.7uF

PC28FxxxP30B85FLASH

U6

PC28F512P30BF

A1A1

A2B1

A3C1

A4D1

A5D2

A6A2

A7C2

A8A3

A9B3

A10C3

A11D3

A12C4

A13A5

A14B5

A15C5

A16D7

A17D8

A18A7

A19B7

A20C7

A21C8

A22A8

NC(64M)/A23G1

CE#B4

OE#F8

WE#G8

WP#C6

VCCA6

RESET#D4

VCCH3

D0F2

D1E2

D2G3

D3E4

D4E5

D5G5

D6G6

D7H7

D8E1

D9E3

D10F3

D11F4

D12F5

D13H5

D14G7

D15E7

WAITF7

GNDB2

GNDH4GNDH2

CLKE6

ADV#F6

NC/A26(1G)B8

RFU3E8RFU2F1RFU1G2RFU0H1

NC(64M,128M)/A24H8

NC/A25(512M)B6

VPPA4

VCCQD6VCCQD5

VCCQG4

GNDH6

C17

4.7uF

C31

0.1uF

R3345.62k

C316

0.1uF

U20

EPCQ256

VC

C2

NC013

NC024

NC035

NC046

nCS7

DATA18

DCLK16

DATA015

NC0511

NC0612

NC0713

NC0814

GN

D10

DATA29

DATA31

C268

0.1uF

D13

CMDSH-3

C257

0.1uF

C246

0.1uFR362 10K

R326 10K

J5

CON2

12

R3354.7K

C30

0.1uF

U4

LT1761

VIN1

GND2

VOUT5

ADJ/BYPASS4

SHDN3

U13

IDTQS3861

NC1

A02

A13

A24

A35

A46

A57

A68

A79

A810

A911

GND12

BE23

VCC24

B022

B121

B220

B319

B418

B517

B616

B715

B814

B913

C267

0.1uF

R363 10K

XJ1

881545-2

C253

0.1uF

C247

0.1uF

R333 36K

Page 16: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

LED INTERFACE

PUSH BUTTON INTERFACE

MAXV DIPSWITCH

5M2210 System Controller

VCCINT 2.5V VCCIO

ON-BOARD USB BLASTER II

1.5V VCCIO

FPGA_DCLKFPGA_CONFIG_D1FPGA_CONFIG_D2FPGA_CONFIG_D3

FPGA_CONFIG_D5FPGA_CONFIG_D6

FPGA_CONFIG_D4

FPGA_nSTATUSFPGA_CONF_DONE

FPGA_CONFIG_D0

FPGA_CONFIG_D7

PGM_LED[2:0]

MAX_ERROR

MAX_CONF_DONEMAX_LOAD

PGM_CONFIGMAX_RESETn

PGM_SEL

MSEL1MSEL2

MSEL0

MSEL3MSEL4

FPGA_CONFIG_D8FPGA_CONFIG_D9FPGA_CONFIG_D10FPGA_CONFIG_D11FPGA_CONFIG_D12FPGA_CONFIG_D13FPGA_CONFIG_D14FPGA_CONFIG_D15

CLK_100M_MAX

CLK_50M_MAX

FM_A21FM_A22

FPGA_CvP_CONFDONEFPGA_PR_ERROR

CLK50_EN

Si570_EN

CLK125A_EN

HSMA_PRSNTn

PGM_SEL

MAX_CONF_DONE

FPGA_nCONFIG

PGM_LED0PGM_CONFIG

SDI_RX_EN

SDI_TX_ENSDI_RX_BYPASS

CPU_RESETn

MAX_ERRORMAX_LOAD

SI571_EN

FM_D14FM_D15

FM_D10FM_D11FM_D12FM_D13

FM_D8FM_D9

FM_A1FM_A2FM_A3

FM_A0

FM_A4FM_A5FM_A6FM_A7

FM_A14

FM_A8FM_A9

FM_A15

FM_A10FM_A11FM_A12FM_A13

FM_A19FM_A20

FM_A18

FM_A16FM_A17

FM_D1FM_D2FM_D3

FM_D0

FM_D4FM_D5FM_D6FM_D7

FPGA_PR_READYFPGA_PR_REQUESTFPGA_PR_DONE

PGM_LED1PGM_LED2

FACTORY_LOAD

CLK_SEL

MAX_RESETn

FACTORY_STATUS

SECURITY_MODEM570_CLOCK

FACTORY_REQUEST

PCIE_JTAG_EN

USB_CFG[11:0]

USB_CFG0

USB_CFG1

USB_CFG2USB_CFG3USB_CFG4USB_CFG5USB_CFG6USB_CFG7USB_CFG8USB_CFG9

USB_CFG10

USB_CFG11

USB_B2_CLK

EXTRA_SIG[2:0]

EXTRA_SIG1

EXTRA_SIG2

HPS_RESETn

I2C_SDA_MAX

I2C_SCL_MAX

I2C_SDA_MAXI2C_SCL_MAX

I2C_SDA_MAXI2C_SCL_MAX MAX_FPGA_MOSI

MAX_FPGA_MISO

MAX_FPGA_MISOMAX_FPGA_MOSI

MAX_AS_CONF

FLASH_OEn

FLASH_ADVn

FLASH_CEn0

FLASH_CLKFLASH_RESETn

FLASH_WEn

FLASH_RDYBSYn

M570_PCIE_JTAG_EN

FM_A23

FM_A24FM_A25FM_A26

MAX_FPGA_SCKMAX_FPGA_SSEL

MAX_FPGA_SCKMAX_FPGA_SSEL

1V8

2.5V_REG_HPS

1V8

1.5V_REG_HPS

1.5V_REG_HPS2.5V_REG_HPS

2.5V_REG_HPS

1V8

1V8

CPU_RESETn 11,23

FLASH_RDYBSYn 15

FPGA_nCONFIG11

CLK_SEL

FM_A[26:0]15

FM_D[15:0]15

FPGA_DCLK 11,15

FPGA_CONF_DONE 11

FPGA_nSTATUS 11

FLASH_CEn0 15

HSMA_PRSNTn 4,17,23

FLASH_ADVn 15

FLASH_WEn15

FLASH_OEn 15

FLASH_RESETn 15FLASH_CLK 15

SDI_TX_EN 5,20SDI_RX_BYPASS 5,20SDI_RX_EN 5,20

CLK125A_EN 10,12

Si570_EN 10,12

CLK50_EN 10

FPGA_CONFIG_D[15:0]11,15

FACTORY_LOAD 12SECURITY_MODE 12

PGM_SEL23PGM_CONFIG23MAX_RESETn23

PGM_LED[2:0]23

MAX_ERROR23

MAX_LOAD23

MAX_CONF_DONE23

FPGA_PR_DONE 11FPGA_PR_REQUEST 11FPGA_PR_READY 11FPGA_PR_ERROR 11FPGA_CvP_CONFDONE11

MSEL0 11MSEL1 11MSEL2 11MSEL3 11MSEL4 11

SI571_EN 8

M570_CLOCK 25FACTORY_STATUS 25FACTORY_REQUEST 25

PCIE_JTAG_EN

M570_PCIE_JTAG_EN 25

USB_CFG[11:0]25

USB_B2_CLK4,25

EXTRA_SIG[2:0]25

JTAG_MAX_TDI 12JTAG_MAX_TDO 12JTAG_MAX_TMS 12

JTAG_MUX_TCK11,12,17

CLK_50M_MAX 10CLK_100M_MAX 10

OVERTEMP26

HPS_RESETn6,21

USB_RESET 22

I2C_SDA 7,20,26

I2C_SCL 7,20,26

I2C_SDA_MAX 8,10

I2C_SCL_MAX 8,10 MAX_FPGA_MOSI11

MAX_FPGA_MISO11

MAX_AS_CONF 15,16

MAX_AS_CONF 15,16

JTAG_TRST6,12MICTOR_RSTn6,12,21

TRST 25RST 25

MAX_FPGA_SCK11MAX_FPGA_SSEL11

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

16 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

16 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

16 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

C323

0.1uF

C319

0.1uF

C394

0.1uF

C281

0.1uF

C304

0.1uF

R4240

R5460

C320

0.1uF

R4230

MAX VBANK1

U19A

5M2210ZF256

DIFFIO_L19PN1

IOB1/CLK0H5

IOB1/CLK1J5

DIFFIO_L9PG1

DIFFIO_L9NG4

DIFFIO_L8PG2

DIFFIO_L8NG3

DIFFIO_L7PF1

DIFFIO_L7NF6

DIFFIO_L6PF4

DIFFIO_L6NF2

DIFFIO_L5PF3

DIFFIO_L5NE1

DIFFIO_L4PD1

DIFFIO_L4NE5

DIFFIO_L3PD2

DIFFIO_L3NE4

DIFFIO_L2PC3

DIFFIO_L2NE3

DIFFIO_L21PN3

DIFFIO_L21NP2

DIFFIO_L20PN2

DIFFIO_L20NM3

DIFFIO_L1PD3

DIFFIO_L1NC2

DIFFIO_L19NM4

DIFFIO_L18PL4

DIFFIO_L18NL3

DIFFIO_L17PM1

DIFFIO_L17NM2

DIFFIO_L16PL2

DIFFIO_L16NK3

DIFFIO_L15PK5

DIFFIO_L15NL1

DIFFIO_L14PJ3

DIFFIO_L14NK2

DIFFIO_L13PJ4

DIFFIO_L13NK1

DIFFIO_L12PH4

DIFFIO_L12NJ2

DIFFIO_L11PH3

DIFFIO_L11NJ1

DIFFIO_L10PH2

DIFFIO_L10NG5

IOB1_1E2

IOB1_2F5

IOB1_3H1

IOB1_4K4

IOB1_5L5

TMSN4TDOM5TDIL6TCKP3

C291

0.1uF

MAX VBANK4

U19D

5M2210ZF256

DIFFIO_B13N/DEV_CLRnM9

DIFFIO_B13P/DEV_OEM8

DIFFIO_B9PP8

DIFFIO_B9NT7

DIFFIO_B8PM7

DIFFIO_B8NR7

DIFFIO_B7PR6

DIFFIO_B7NN7

DIFFIO_B6PT5

DIFFIO_B6NP7

DIFFIO_B5PR5

DIFFIO_B5NM6

DIFFIO_B4PP6

DIFFIO_B4NN6

DIFFIO_B3PR3

DIFFIO_B3NN5

DIFFIO_B2PT2

DIFFIO_B2NP5

DIFFIO_B22PR16

DIFFIO_B22NP13

DIFFIO_B21PP12

DIFFIO_B21NT15

DIFFIO_B20PN12

DIFFIO_B20NR14

DIFFIO_B1PR1

DIFFIO_B1NP4

DIFFIO_B19PT13

DIFFIO_B19NR13

DIFFIO_B18PR12

DIFFIO_B18NP11

DIFFIO_B17PT12

DIFFIO_B17NN11

DIFFIO_B16PP10

DIFFIO_B16NR11

DIFFIO_B15PN10

DIFFIO_B15NT11

DIFFIO_B14PM10

DIFFIO_B14NR10

DIFFIO_B12PR9

DIFFIO_B12NP9

DIFFIO_B11PT8

DIFFIO_B11NT9

DIFFIO_B10PN8

DIFFIO_B10NR8 IOB4_28

M11

IOB4_29M12

IOB4_30N9

IOB4_31R4

IOB4_32T10

IOB4_33T4

C336

0.1uF

C393

0.1uF

C321

0.1uF

C395

0.1uF

R418 10K

C322

0.1uF

MAX VBANK2

U19B

5M2210ZF256

DIFFIO_T9PB8

DIFFIO_T9NA8

DIFFIO_T8PD8

DIFFIO_T8NA7

DIFFIO_T7PC8

DIFFIO_T7NB7

DIFFIO_T6PB6

DIFFIO_T6NE7

DIFFIO_T5PA5

DIFFIO_T5ND7

DIFFIO_T4PE6

DIFFIO_T4NB5

DIFFIO_T3PB4

DIFFIO_T3ND6

DIFFIO_T2PC5

DIFFIO_T2NC4

DIFFIO_T1PD4

DIFFIO_T1NB1

DIFFIO_T18PC13

DIFFIO_T18NB16

DIFFIO_T17PD12

DIFFIO_T17NB14

DIFFIO_T16PC11

DIFFIO_T16NB13

DIFFIO_T15PE11

DIFFIO_T15NB12

DIFFIO_T14PB11

DIFFIO_T14NA12

DIFFIO_T13PE10

DIFFIO_T13NA11

DIFFIO_T12PA10

DIFFIO_T12NC9

DIFFIO_T11PB9

DIFFIO_T11ND9

DIFFIO_T10PA9

DIFFIO_T10NE9

IOB2_6A13

IOB2_7A15

IOB2_8A2

IOB2_9A4

IOB2_10A6

IOB2_11B10

IOB2_12B3

IOB2_13C10

IOB2_14C12

IOB2_15C6

IOB2_16C7

IOB2_17D10

IOB2_18D11

IOB2_19D5

IOB2_20E8

C345

0.1uF

MAX VPower

U19E

5M2210ZF256

GNDINTF7

GNDINTG6

GNDINTH7

GNDINTH9

GNDIOA1

GNDIOA16

GNDIOB15

GNDIOB2

GNDIOG10

GNDIOG7

GNDIOG8

GNDIOG9

GNDIOK10

GNDIOK7

GNDIOK8

GNDIOK9

GNDIOR15

GNDIOR2

GNDIOT1

GNDIOT16

VCCINTH8VCCINTH10VCCINTG11VCCINTF10

VCCIO1C1

VCCIO1H6

VCCIO1J6

VCCIO1P1

VCCIO2A14

VCCIO2A3

VCCIO2F8

VCCIO2F9

VCCIO3C16

VCCIO3H11

VCCIO3J11

VCCIO3P16

VCCIO4L8

VCCIO4L9

VCCIO4T14

VCCIO4T3

GNDINTJ10

VCCINTJ7

VCCINTL7

GNDINTJ8

GNDINTK11

VCCINTK6VCCINTJ9

GNDINTL10

GNDIOT6

R5520

C306

0.1uF

MAX VBANK3

U19C

5M2210ZF256

IOB3/CLK2J12

IOB3/CLK3H12

DIFFIO_R9PG12

DIFFIO_R9NG16

DIFFIO_R8PG13

DIFFIO_R8NG15

DIFFIO_R7PG14

DIFFIO_R7NF16

DIFFIO_R6PE16

DIFFIO_R6NF15

DIFFIO_R5PF13

DIFFIO_R5NE15

DIFFIO_R4PF14

DIFFIO_R4ND16

DIFFIO_R3PE12

DIFFIO_R3ND15

DIFFIO_R2PC15

DIFFIO_R2NE13

DIFFIO_R22PP15

DIFFIO_R22NP14

DIFFIO_R21PN15

DIFFIO_R21NN14

DIFFIO_R20PN16

DIFFIO_R20NM13

DIFFIO_R1PE14

DIFFIO_R1NC14

DIFFIO_R19PM15

DIFFIO_R19NL14

DIFFIO_R18PM16

DIFFIO_R18NL13

DIFFIO_R17PL15

DIFFIO_R17NL12

DIFFIO_R16PL16

DIFFIO_R16NL11

DIFFIO_R15PK15

DIFFIO_R15NK14

DIFFIO_R14PK16

DIFFIO_R14NK13

DIFFIO_R13PJ14

DIFFIO_R13NJ15

DIFFIO_R12PJ13

DIFFIO_R12NJ16

DIFFIO_R11PH13

DIFFIO_R11NH16

DIFFIO_R10PH14

DIFFIO_R10NH15

IOB3_21D13

IOB3_22D14

IOB3_23F11

IOB3_24F12

IOB3_25K12

IOB3_26M14

IOB3_27N13

R419 10K

C337

0.1uF

C318

0.1uF

C282

0.1uF

C305

0.1uF

C346

0.1uF

C317

0.1uF

Page 17: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

HSMC Port A

A

HSMA_D1HSMA_D3

HSMA_RX_D_P0HSMA_RX_D_N0

HSMA_RX_D_P1HSMA_RX_D_N1

HSMA_RX_D_P2HSMA_RX_D_N2

HSMA_RX_D_P3HSMA_RX_D_N3

HSMA_RX_D_P4HSMA_RX_D_N4

HSMA_RX_D_P5HSMA_RX_D_N5

HSMA_RX_D_P6HSMA_RX_D_N6

HSMA_RX_D_P7HSMA_RX_D_N7

HSMA_RX_D_P8HSMA_RX_D_N8

HSMA_RX_D_P9HSMA_RX_D_N9

HSMA_RX_D_P10HSMA_RX_D_N10

HSMA_RX_D_P11HSMA_RX_D_N11

HSMA_RX_D_P12HSMA_RX_D_N12

HSMA_RX_D_P13HSMA_RX_D_N13

HSMA_RX_D_P14HSMA_RX_D_N14

HSMA_RX_D_P15HSMA_RX_D_N15

HSMA_RX_D_P16HSMA_RX_D_N16

HSMA_CLK_IN_P2HSMA_CLK_IN_N2

HSMA_TX_D_P0HSMA_TX_D_N0

HSMA_TX_D_P1HSMA_TX_D_N1

HSMA_TX_D_P2HSMA_TX_D_N2

HSMA_TX_D_P3HSMA_TX_D_N3

HSMA_TX_D_P4HSMA_TX_D_N4

HSMA_TX_D_P5HSMA_TX_D_N5

HSMA_TX_D_P6HSMA_TX_D_N6

HSMA_TX_D_P7HSMA_TX_D_N7

HSMA_TX_D_P8HSMA_TX_D_N8

HSMA_TX_D_P9HSMA_TX_D_N9

HSMA_TX_D_P10HSMA_TX_D_N10

HSMA_TX_D_P11HSMA_TX_D_N11

HSMA_TX_D_P12HSMA_TX_D_N12

HSMA_TX_D_P13HSMA_TX_D_N13

HSMA_TX_D_P14HSMA_TX_D_N14

HSMA_TX_D_P15HSMA_TX_D_N15

HSMA_TX_D_P16HSMA_TX_D_N16

HSMA_CLK_OUT_P2HSMA_CLK_OUT_N2

HSMA_D0HSMA_D2

HSMA_PRSNTn

HSMA_CLK_OUT_P1HSMA_CLK_OUT_N1

HSMA_CLK_IN_P1HSMA_CLK_IN_N1

12V

3.3V

3.3V

12V

HSMA_SCL 4JTAG_HSMA_TMS 12JTAG_HSMA_TDI 12

HSMA_TX_N08

HSMA_TX_P08

HSMA_TX_N18

HSMA_TX_P18

HSMA_TX_N28

HSMA_TX_P28

HSMA_TX_N38

HSMA_TX_P38

HSMA_CLK_OUT_P[2:1]4,7

HSMA_CLK_OUT_N[2:1]4,7

HSMA_CLK_IN_N[2:1]4,9

HSMA_CLK_IN_P[2:1]4,9

HSMA_SDA4JTAG_MUX_TCK11,12,16

HSMA_D[3:0]4

HSMA_TX_D_P[16:0]7

HSMA_TX_D_N[16:0]7

HSMA_RX_D_P[16:0]7

HSMA_RX_D_N[16:0]7

HSMA_PRSNTn4,16,23

JTAG_HSMA_TDO12HSMA_CLK_IN0 9HSMA_CLK_OUT09

HSMA_RX_N38

HSMA_RX_P3 8

HSMA_RX_N08

HSMA_RX_P0 8

HSMA_RX_N18

HSMA_RX_P1 8

HSMA_RX_N28

HSMA_RX_P2 8

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

17 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

17 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

17 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

BANK 1

BANK 2

BANK 3

J12

ASP-122953-01

11

33

55

77

99

1111

1313

1515

1717

1919

2121

2323

2525

2727

2929

3131

3333

3535

3737

3939

4141

4343

3.3V45

4747

4949

3.3V51

5353

5555

3.3V57

5959

6161

3.3V63

6565

6767

3.3V69

7171

7373

3.3V75

7777

7979

3.3V81

8383

8585

3.3V87

8989

9191

3.3V93

9595

9797

3.3V99

101101

103103

3.3V105

107107

109109

3.3V111

113113

115115

3.3V117

119119

22

44

66

88

1010

1212

1414

1616

1818

2020

2222

2424

2626

2828

3030

3232

3434

3636

3838

4040

4242

4444

12V46

4848

5050

12V52

5454

5656

12V58

6060

6262

12V64

6666

6868

12V70

7272

7474

12V76

7878

8080

12V82

8484

8686

12V88

9090

9292

12V94

9696

9898

12V100

102102

104104

12V106

108108

110110

12V112

114114

116116

12V118

120120

GN

D_1_1

161

GN

D_1_2

162

GN

D_1_3

163

GN

D_1_4

164

GN

D_2_1

165

GN

D_2_2

166

GN

D_2_3

167

GN

D_3_1

169

GN

D_2_4

168

GN

D_3_2

170

GN

D_3_3

171

GN

D_3_4

172

121121

3.3V123

125125

127127

3.3V129

131131

133133

3.3V135

137137

139139

3.3V141

143143

145145

3.3V147

149149

151151

3.3V153

155155

157157

3.3V159

122122

12V124

126126

128128

12V130

132132

134134

12V136

138138

140140

12V142

144144

146146

12V148

150150

152152

12V154

156156

158158

PSNTn160

C48222uF25V

C33522uF25V

Page 18: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

10/100/1000 Ethernet - HPS

Place near KSZ9021RN PHY

ETHERNET INTERFACE

BOOT-STRAPS

1.2V AVDLL_PLL

MDI_HPS_P1MDI_HPS_N1MDI_HPS_P2MDI_HPS_N2

CT3

MDI_HPS_P3

CT1

CT0

CT2

MDI_HPS_N3

MDI_HPS_N0MDI_HPS_P0

ENET_HPS_TX_ENENET_HPS_GTX_CLK

ENET_HPS_MDIO

ENET_HPS_MDC

ENET_HPS_RX_DV

ENET_HPS_TXD[3..0]

ENET_HPS_RX_CLK

ENET_HPS_RXD[3..0]

ENET_HPS_RESETn

ENET_HPS_INTn

ENET_HPS_RXD2

ENET_HPS_RXD0

ENET_HPS_RXD3

ENET_HPS_RXD1

ENET_HPS_RX_CLK

ENET_HPS_RX_DV

ENET_HPS_GTX_CLK

ENET_HPS_TX_EN

ENET_HPS_MDCENET_HPS_MDIO

ENET_HPS_LED2_LINKENET_HPS_LED1_LINK

ENET_HPS_INTn

ENET_HPS_RSET

ENET_HPS_RESETnENET_HPS_LED2_LINK

ENET_HPS_LED1_LINK

ENET_HPS_LED2_LINKENET_HPS_LED1_LINK

ENET_HPS_RXD2ENET_HPS_RXD3

ENET_HPS_RXD1ENET_HPS_RXD0ENET_HPS_RX_DV

CLK125_NDO_LED_MODE

CLK125_NDO_LED_MODE

ENET_HPS_TXD2

ENET_HPS_TXD0

ENET_HPS_TXD3

ENET_HPS_TXD1

CT0

CT1

CT2

CT3

ENET_HPS_RX_CLK

3.3V_REG_HPS

3.3V_REG_HPS

3.3V_REG_HPS1.2V_AVDLL_PLL

3.3V_AVDDH

3.3V_DVDDH 1.2V_AVDDL

1.2V_AVDLL_PLL

1.2V_AVDDL

1.2V_DVDDL 1.2V_DVDDL3.3V_DVDDH

3.3V_REG_HPS

3.3V_REG_HPS

3.3V_REG_HPS

3.3V_AVDDH

3.3V

2.5V_REG_HPS2.5V_REG_HPS

5.0V2.5V_REG_HPS

2.5V_REG_HPS

1.2V_AVDLL_PLL

ENET_HPS_RESETn18,21ENET_HPS_MDC6,18

ENET_HPS_GTX_CLK6

ENET_HPS_MDIO6,18

ENET_HPS_TX_EN6

ENET_HPS_RXD[3..0]6

ENET_HPS_RX_DV6ENET_HPS_RX_CLK6

ENET_HPS_TXD[3..0]6

ENET_HPS_INTn6,18

ENET_HPS_MDIO6,18

ENET_HPS_RESETn18,21

ENET_HPS_MDC6,18

I2C_SCL_HPS 6,23,27I2C_SDA_HPS 6,23,27

ENET_HPS_INTn6,18

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

18 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

18 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

18 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

L3

3A, 30 Ohm FB

R47 4.70K, 1%

R371 4.70K, 1%

R367 DNI R48 4.70K, 1%

C5922uF

C60

0.1uF

C47 1uFU18

LTC3026

IN11

IN22

GN

D3

SW4

BST5

SHDN6

PG7ADJ8

OUT19OUT210

GN

D11

C442.2uF

R1 220

MDI INTERFACE

U11A

KSZ9021RN

TXRXP_A2

LED1_PHYAD017

TXRXP_D10

TXRXP_C7

TXRXM_C8

TXRXP_B5

TXRXM_B6

TXRXM_A3

TXRXM_D11

LED2_PHYAD115

TXD120

TXD019

GTX_CLK24

RXD0_MODE032

RX_DV_CLK125_EN33

TXD322

RXD2_MODE228

TX_EN25

RXD3_MODE327

RXD1_MODE131

TXD221

RX_CLK_PHYAD235

MDC36

MDIO37

INT_N38

XO45 XI46

ISET48

RESET_N42

CLK125_NDO_LED_MODE41

R342 1.00k

U11B

KSZ9021RN

DVDDL39

DVDDH40

LDO_O43AVDDL_PLL44

AVDDH47

P_GND49

VSS29 VSS_PS13

AVDDL9

AVDDL4AVDDH

1 AVDDH12

DVDDL30

DVDDL26

DVDDL23

DVDDL14DVDDH

16DVDDL

18

DVDDH34

U28

24LC32A

A01

A12

A23

GND4

VCC8

WP7

SCL6

SDA5

R341 1.00k

C5622uF

C28

0.1uF

C2622uF

C49 DNI

C27

10uF

R49 4.70K, 1%

R56 2.00K

R339 DNI

C4522uF

C26222uF

C15 0.01uF

Y1

25.00MHz

13

24

C270

0.1uF

R365 4.70K, 1%

R340 DNI

L1

3A, 30 Ohm FB

R379 DNI

C57

0.1uF

C552.2uF

R364 4.70K, 1%

C612.2uF

C52

10uF

R42 4.70K, 1%R348 DNI

R2

220

R378 4.70K, 1%

R368 4.70K, 1%

C4322uF

C16 0.01uF

L4

3A, 30 Ohm FB

R406 4.70K, 1% R407 DNI

R46 10.0K R55

1.00K

C2612.2uF

C232.2uF

R366 DNI

C48 DNIC21

10uF

C14 0.01uF

R50 4.99K

R369 DNI

C46

2.2uF

L24

3A, 30 Ohm FB

C58

0.1uF

R347 4.70K, 1%

Yellow

Green

Orange

J2

ENET_L829-1J1T-43

TD0_P11

TD0_N10

TD1_P4

TD1_N5

TD2_P3

TD2_N2

TD3_P8

TD3_N9

CT012

GND_TAB19 GND_TAB18

OK15

GOA16

YA14

YK13

GK17

CT16

CT21

CT37

R370 DNI

C13 0.01uF

Page 19: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

10/100M Ethernet - FPGA

Place near uPD60620 PHY

PLACE NEAR LEVEL TRANSLATORS

Place near uPD60620 PHY

BOOT-STRAPS

ENET1_TX_D0ENET1_TX_D1ENET1_TX_D2ENET1_TX_D3

ENET2_TX_D0

ENET2_TX_D2ENET2_TX_D1

ENET2_TX_D3

ENET2_RX_D2

ENET2_RX_D0

ENET2_RX_D3

ENET2_RX_D1

ENET1_RX_D2ENET1_RX_D3

ENET1_RX_D0ENET1_RX_D1

ENET1_TX_EN

ENET2_TX_EN

ENET1_RX_DV

ENET2_RX_DV

ENET1_RX_CLK

ENET2_RX_CLK

ENET1_RX_ERROR

ENET2_RX_ERROR

ENET1_TX_CLK_FB

ENET2_TX_CLK_FB

ENET1_TX_D0ENET1_TX_D1ENET1_TX_D2ENET1_TX_D3

ENET1_RX_D2ENET1_RX_D3

ENET1_RX_D0ENET1_RX_D1

ENET2_TX_D0

ENET2_TX_D2ENET2_TX_D1

ENET2_TX_D3

ENET2_RX_D2

ENET2_RX_D0

ENET2_RX_D3

ENET2_RX_D1

ENET1_LINK_LED

ENET1_RX_DVENET2_RX_DVENET1_RX_D0ENET1_RX_D1

ENET2_RX_D0ENET2_RX_D1ENET2_RX_CLKENET1_RX_ERRORENET2_RX_ERRORENET1_RX_CLK

ENET2_LINK_LED

ENET1_MDI_TX_PENET1_MDI_TX_N

ENET1_MDI_RX_PENET1_MDI_RX_N

ENET1_LINK_LED

ENET2_LINK_LED

ENET2_MDI_TX_PENET2_MDI_TX_N

ENET2_MDI_RX_PENET2_MDI_RX_N

ENET1_ACT_LED

ENET2_ACT_LED

ENET2_ACT_LED

ENET1_ACT_LED

REG_FB

ENET_DUAL_RESETn

REG_FB

P0TXERR_PHY

P1TXERR_PHY

P1TXERR_PHYP0TXERR_PHY

1.5V_REG_HPS

3.3V

3.3V

1.5V_REG_HPS

1V5_ECAT2

3.3V3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

1V5_ECAT

3.3V

1V5_ECAT2

ENET1_TX_D[3..0]5

ENET1_RX_D[3..0]5

ENET2_RX_D[3..0]5

ENET2_TX_D[3..0]5

ENET1_RX_ERROR5ENET1_RX_DV5ENET1_RX_CLK5ENET1_TX_CLK_FB5

ENET2_RX_ERROR5

ENET2_RX_CLK5

ENET2_RX_DV5

ENET2_TX_CLK_FB5

ENET1_TX_EN5

ENET2_TX_EN5

ENET_FPGA_MDC7

ENET_FPGA_MDIO7

ENET_DUAL_RESETn4,21

P0TXERR4,19

P1TXERR4,19

P0TXERR4,19

CLK_DUAL_ENET_PHY10

P1TXERR4,19

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

19 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

19 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

19 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

C644

0.1uF

R218

0_Ohms

R483 DNI

R495 4.70K, 1%

R22749.9

C220

0.01uF

C109

0.1uF

L2210uH

12

U45

uPD60620

P0TXD043

P0TXD144

P0TXD245

P0TXD346

P1TXD023

P1TXD124

P1TXD225

P1TXD326

P0TXERR47

P0TXEN48

P0TXCLK49

P0RXD053

P0RXD154

P0RXD255

P0RXD356

P0RXDV57 P0RXERR58

P0RXCLK59

P0CRS60

P0TXP15

P0TXN16

P0RXP17

P0RXN18

P1RXD136

P1TXEN28

P1RXD237

P1TXERR27

P1RXCLK41 P1RXDV39

P1CRS42

P1RXERR40

P1RXD035

P1RXD338

P1TXCLK29

REGBVDD170

REGBVDD271

REGAVDD77

VCC33ESD20

VDDIO132

VDDIO366VDDIO250

REGLX172

REGLX273

VDDACB10

VDD15_130

VDD15_252

VDDAPLL11

P1TXN6P1TXP7

P1RXP5

P1RXN4

REGBGND174

REGBGND275

P0AGND14

P1AGND8

GNDIO31

GND1551

VSSAPLL9

P0VDDMEDIA19

P1VDDMEDIA3

REGFB78

XCLK033

XCLK134

REGOFF80

RESETB1

TEST2 ATP

13

P0COL21

P1COL22

EXTRES12

DR79

MDC62 MDIO63

P0100BTLED64

P1100BTLED61

P0ACTLED68

P1ACTLED65

P0LINKED69

P1LINKED67

REGAGND76

R23049.9

C230

0.01uF

R481 DNI

C111

0.1uF

C633

0.1uF

C229

12pF

R23149.9

C61422uF25V

R515 DNI

R23549.9

R494 DNI

R503 4.70K, 1%

R501 DNI

C217

12pF

R477 DNI

C627

0.1uF

C223

0.01uF

R23310

C631

0.1uF

C227

0.01uF

R482 4.70K, 1%

R238

0

R23610

R23210

C221

12pF

C224

12pF

R273 220

R217DNI

R485 4.70K, 1%

R502 DNI

R500 DNI

R524 4.70K, 1%

R527 12.4K

C228

12pF

C643

0.1uF

R276 220

R213 DNIR22449.9

C108

0.1uF

R509 DNI

C645

0.1uF

R488 DNI

R22510

R22849.9

C219

0.01uF

C110

0.1uF

R533 4.70K, 1%

R275 220

R22610

C112

4.7uF

C630

0.1uF

R490 DNIR489 4.70K, 1%

R23449.9

R514

0

R487 4.70K, 1%

C626

0.1uF

R22910

R504 4.70K, 1%

C218

12pF

Green

Yellow

J34

EN

ET

-74

99

01

11

21

A

TD+1

TD-3

RD+4

RD-6

GND8

GND_TAB13

GND_TAB14

GK

12

GA

11

YA

9

YK

10

TCT2

RCT5

GN

D_T

AB

115

GN

D_T

AB

216

NC

7

C226

0.01uF

R499 4.70K, 1%

C628

0.1uF

R540 4.70K, 1%

R480

0

C632

0.1uF

Green

Yellow

J33

EN

ET

-74

99

01

11

21

A

TD+1

TD-3

RD+4

RD-6

GND8

GND_TAB13

GND_TAB14

GK

12

GA

11

YA

9

YK

10

TCT2

RCT5

GN

D_T

AB

115

GN

D_T

AB

216

NC

7

C641

0.1uF

R528 4.70K, 1%

R484 4.70K, 1%R274 220

R498 4.70K, 1%

C222

12pF

R526 DNI

C629

0.1uF

C225

12pF

R496 DNI

R478 4.70K, 1%

R512 DNI

D32

40V

R525 DNI

C61522uF25V

R523 4.70K, 1%

C642

0.1uF

R237

DNI

R486 DNI

R479 DNI

R22349.9

R508 4.70K, 1%

Page 20: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

75 Ohm Impedance

75 Ohm Impedance

SDI Cable Driver, Equalizer, SMA Option and SMB

RightAngle

RightAngle

From EPM2210

Read-Only (Auto-Mute)

CAD Note:Route traces at secondary side

CAD Note:Route traces at secondary side

CAD Note:Overlap C189 & R284

CAD Note:Overlap C188 & R286

SDI_TXBNC_P

SDI_TXBNC_N

SDI_RX_CDn

SDI_IN_P1

SDI_EQIN_P1SDI_EQIN_N1

SDO_P

SDI_TX_RSET

AEC

SDI_TXCAP_PSDI_TXCAP_N SDI_TXDRV_P

SDI_TXDRV_FILTER_P

SDI_TXDRV_FILTER_N

SDI_TXDRV_N

SDI_IN_FILTER_P1

SDI_SDASDI_SCL

SDO_N

SDI_SDASDI_SCL

3.3V_SDI

3.3V_SDI

3.3V_SDI

3.3V_SDI

3.3V_SDI

3.3V_SDI

3.3V

3.3V_SDI

3.3V_SDI

3.3V_SDI

3.3V_SDI

3.3V_SDI

SDI_RX_P 8

SDI_RX_N 8

SDI_RX_EN5,16

SDI_RX_BYPASS5,16

SDI_TX_N8

SDI_TX_EN5,16

SDI_TX_SD_HDn5

SDI_TX_P8

SDI_FAULT5SDI_RSTI5

I2C_SDA7,16,26

I2C_SCL7,16,26

Title

Size Document Number Rev

Date: Sheet of

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

20 40Wednesday, March 20, 2013

Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

20 40Wednesday, March 20, 2013

Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

20 40Wednesday, March 20, 2013

Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

C75

0.1uF

C97 1.0UF

R86

75

R91 750

R95 10K

J17

Mini SMB

1

2345

R85 75

R127 75

J14

Mini SMB

1

2 3 4 5

L5

120 ohm FB

R78

49.9

C76

220nF

L11 5.6nH1 2

R4430

R96 10K

R94 10K

C80 4.7uF

V1

C116 4.7UF

L9 5.6nH1 2

R920

U31

SDI Cable Equalizer, LMH0384SQ

VEE11

SPI_EN4

SDI2

SDI3

AEC+5

AEC-6

BYPASS7

MUTEref8 VEE2

9

SDO11

SDO10

AUTO_SLEEP12

MUTE14

CD15

VCC113

VCC216

DAP17

R75

10K

CableDriver

U25

SDI Cable Driver, LMH0303SQx

SDI1

SDI2

VEE3

RREF4

VCC9

SD/HD10

SDO12

SDO11

CENTERPAD17

RSTI5

ENABLE6

SDA7

SCL8

FAULT13

NC514

NC615

RSTO16

R442 0

L6 5.6nH1 2

C81 4.7uF

C86 4.7uF

R128 75

R97 37.4

C119

0.1uF

R80 75

R79

49.9

C96

22uF

C117 4.7UF

R76 75

R93

0

C85

0.01uF

C104

220nF

D17

Green_LED

C103 1.0UF

R81 75

R98 75

C90 4.7uF

R126

0

C120 1.0UF

Page 21: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

QSPI Flash & Reset Circuit

RESET CIRUIT

PLACE NEAR QSPI FLASH

QSPI FLASH

USB_RESET IS ACTIVE HIGH AND IS INVERTED THROUGH THE MAX II SYSTEM CONTROLLER

Input only to CV device cold reset

Input/output to CV device warm reset

PB_COLD_RESETn

HPS_RESETn

PB_WARM_RESETn

MICTOR_RSTn

COLD_RESETn

WARM_RESETn

3.3V

3.3V

3.3V3.3V

3.3V3.3V

QSPI_SS06

QSPI_CLK6

QSPI_IO36

QSPI_IO26

QSPI_IO16

QSPI_IO06

ENET_HPS_RESETn 18

HPS_RESETn6,16

MICTOR_RSTn6,12,16

RESET_HPS_UART_N 24

ENET_DUAL_RESETn4,19

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

21 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

21 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

21 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R3200

U56

MAX811

GND1

RESET2

VCC4

MR3

U55

MAX811

GND1

RESET2

VCC4

MR3

R314

0

C258

4.7uF

R534DNI

S8

PB Switch1 2

R315 100K

R312 100K

R31620.0K

C2410.1uF

C259

0.1uF

R3190

U5

N25Q00AA13GSF40F

DQ015

DQ18

DQ2/VPP/W#9

DQ3/HOLD#1

C16

S#7

DNU13

DNU24

DNU35

DNU46

DNU511

DNU612

DNU713

DNU814

VSS10

VCC2

R31320.0K

S7

PB Switch1 2

TP1

C2400.1uF

R311

0

Page 22: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

USB 2.0 OTG , Micro SD Card

PLACE NEAR USB3300

Micro SD / USB INTERFACE

DanP Update:SMSC schematic review reference number is 834654-B1081.SMSC placement review reference number is 375404-B1082.

USB 2.0 OTG

Micro SD Card

DanP: Should ESD protection diodes to be added?

USB INTERFACE

USB_DATA0USB_DATA1USB_DATA2USB_DATA3USB_DATA4USB_DATA5USB_DATA6USB_DATA7

USB_IDUSB_DP_PUSB_DM_N

USB_CLKUSB_NXTUSB_DIRUSB_STP

USB_RBIAS

USB_XIUSB_XO

USB_DATA[7..0]

USB_CLK

USB_CPEN

USB_VBUS

USB_EXTVBUS

USB_EXTVBUS

USB_RESET_PHY

USB_RESET

USB_RESET USB_RESET_PHY

SD_CLK

SD_CMD

SD_DAT1SD_DAT2SD_CD_DAT3

SD_DAT2SD_CD_DAT3SD_DAT0SD_DAT1SD_CMD

SD_CLK

SD_DAT0

USB_NXTUSB_DIR

USB_STP

USB_VDD

USB_VDDA

USB_VDD USB_VDDA

3.3V

5.0V USB_5.0V

USB_5.0V

USB_5.0V

3.3V

3.3V

3.3V

3.3V

3.3V

USB_DATA[7..0] 6

USB_CLK 6USB_RESET 16

SD_DAT26SD_CD_DAT36SD_DAT06SD_DAT16SD_CMD6

SD_CLK6

USB_STP 6USB_DIR 6USB_NXT 6

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

22 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

22 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

22 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

C6

0.1uF

C254

0.1uF

R34 10.0K

D12 ESD5V3U2U

K1

1

K2

2

A3

C255

0.1uF

R20 10.0K

R6 DNI

C243

0.1uF

C249

0.1uF

R17

1M

U1

MAX1693H

IN11

OUT12

IN23

OUT24

ON5

GND6

FAULT7

OUT38

IN39

OUT410

C1

2.2uF

D11 ESD5V3U2U

K1

1

K2

2

A3

J3

MicroSD_skt

CD/DAT32

CMD3

VSS6

VDD4

CLK5

DAT07

DAT18

DAT21

CAGE9

CAGE10

CAGE11

CAGE12

C20 30pF

J1USB MINI-AB

12345

6 7

R16

DNI

C10

2.2uF

C12 30pF

C4 4.7uF

C3

2.2uF

R15

100K

C242

0.1uF

C2

2.2uF

C251

0.1uF

TP8

R23 10.0K

X2

24MHz13

24

R35 10.0K

R22 10.0K

C245

0.1uF

C5

0.1uF

C256

0.1uFC252

4.7uF

U2

USB3300

VD

D3.3

6

VBUS4

CPEN3

ID5

GND2GND1

DATA024

DATA123

DATA222

DATA321

DATA420

DATA519

DATA618

DATA717

DP7DM8

RESET9

EXTVBUS10

NXT11

DIR12

STP13

CLKOUT14

VD

D1.8

15

VD

D3.3

16

VD

D3.3

25

VD

D1.8

26

VD

DA

1.8

29

XO27

XI28

VD

D3.3

30

REG_EN31

GND_FLAG33

RBIAS32

R9

10.0K

D10 ESD5V3U2U

K1

1

K2

2

A3

C8

0.1uF

C260

4.7uF

R5 820,1%

R8 0

R21 10.0K

R19 10.0K

C250

0.1uFC248

4.7uF

C9

0.1uF

R10

DNI

R36 10.0K

R11

12.0K

Page 23: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

PUSH BUTTON INTERFACE

LED INTERFACE

User I/O, RTC

DIPSW INTERFACE

I2C ADDRESS: 0x40

I2C ADDRESS: 0x50MAX_LOAD

MAX_ERROR

MAX_CONF_DONE

MAX_RESETn

CPU_RESETn

USER_PB_HPS0

USER_PB_HPS1

USER_PB_HPS2

PGM_SEL

PGM_CONFIG

PGM_LED1

PGM_LED2

PGM_LED0

PGM_CONFIGMAX_RESETn

PGM_SEL

PGM_LED[2:0]

CVP_CONF_DONE

HSMA_PRSNTn

USER_LED_HPS0

USER_LED_HPS3

USER_LED_HPS2

USER_LED_HPS1

USER_LED_FPGA0

USER_LED_FPGA3

USER_LED_FPGA2

USER_LED_FPGA1

USER_DIPSW_FPGA1

USER_DIPSW_HPS1

USER_DIPSW_FPGA3

USER_DIPSW_HPS0

USER_DIPSW_HPS2

USER_DIPSW_FPGA0USER_DIPSW_HPS3

USER_DIPSW_FPGA2

USER_PB_FPGA0

USER_PB_FPGA1

USER_PB_HPS3

I2C_SCL_HPSI2C_SDA_HPS

VBAT

USER_LED_HPS[3..0]

I2C_SCL_DISPI2C_SDA_DISP

I2C_SCL_DISPI2C_SDA_DISP

3.3V

2.5V_REG_HPS2.5V_REG_FPGA

3.3V

3.3V

2.5V_REG_FPGA

2.5V_REG_FPGA

3.3V

1.5V_REG_FPGA

3.3V

2.5V_REG_HPS

5.0V

5.0V

3.3V

2.5V_REG_HPS

USER_DIPSW_FPGA[3:0]4

CPU_RESETn 11,16

HSMA_RX_LEDHSMA_TX_LED

MAX_ERROR16

MAX_LOAD 16

USER_LED_FPGA[3:0]4,9

MAX_CONF_DONE16

PCIE_LED_X1PCIE_LED_X4

HSMA_PRSNTn 4,16,17

PGM_SEL16

PGM_CONFIG16

MAX_RESETn16

PGM_LED[2:0]16

USER_PB_FPGA[1:0]4

USER_DIPSW_HPS[3:0]5

USER_PB_HPS[3:0]5

USER_LED_HPS[3..0]6

I2C_SDA_HPS 6,18,27

I2C_SCL_HPS 6,18,27

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

23 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

23 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

23 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R290 4.70K, 1%

R563 49.9

S5

PB Switch1 2

R549 49.9

D7 Green_LED

R555 49.9

R298 4.70K, 1%

SW1

TDA08H0SB1

12345678

161514131211109

S1

PB Switch1 2

R283 49.9

R289 4.70K, 1%

R300 4.70K, 1%

R569 49.9

S11

PB Switch1 2

D1 Green_LED

D2 Green_LED

R288 4.70K, 1%

U24

MAX3373

VCCIO21

GND2

VL3

VL_IO24VL_IO15

VCCIO18

VCC7

TRI_STATE6

B2

HEADER 3X1

D37 Green_LED

S3

PB Switch1 2

D8 Green_LED

C29 0.1uF

R309 49.9

D34 Green_LED

D6 Green_LEDR280 49.9

R278 49.9

R435

0

R564 4.70K, 1%

R567 49.9

R295 4.70K, 1%

R37 0

S9

PB Switch1 2

S12

PB Switch1 2

R301 4.70K, 1%

R565 4.70K, 1%

J15

LCD_HEADER

123456789

10

R297 4.70K, 1%

D5 Green_LEDR294 4.70K, 1%

S10

PB Switch1 2

S6

PB Switch1 2

R38 4.70K, 1%

D39 Green_LED

R284 49.9

B4

HEADER 6X1

R566 4.70K, 1%

B1

2x16 LCD I2C

R282 49.9

R293 4.70K, 1%

R299 4.70K, 1%

D41 Green_LED

R337 4.70K, 1%

R285 49.9

R292 4.70K, 1%

D3 Green_LED

S4

PB Switch1 2

BT1

12

R4

29

10K

S2

PB Switch1 2

D9 Green_LED

D38 Green_LED

D4 Green_LED

R4

30

10K

R568 49.9

D36 Red_LED

R557 49.9

R279 49.9

R291 4.70K, 1%

R434 DNI

D40 Green_LED

U3

DS1339C

SDA16

SCL1

GND15

VCC3

VBACKUP14

SQW/INT2

NC54

NC65

NC76

NC87

NC98

NC109

NC410 NC311 NC212 NC113

R12 0

R296 4.70K, 1%

R281 49.9

Page 24: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

UART, CAN

RS = VCC -> Standby ModeRS = GND -> High-Speed ModeRS = Resistor to GND -> Slope Control

Place near SN65HVD230

CAN BUS

UART

CAN_RS

CANH_PCANL_N

DM_N

PWR_EN

UART_TX_LEDUART_RX_LED

DP_P

RESET_HPS_UART_N

3.3V

CAN_VREF

CAN_VREF3.3V

3.3V_USB_UART

3.3V_USB_UART

3.3V

VIO_USB_UART

5V_USB_UART

3.3V_USB_UART VIO_USB_UART 5V_USB_UART

5V_USB_UART

CAN_0_TX 6

CAN_0_RX 6

RESET_HPS_UART_N21

UART_RX6UART_TX6

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

24 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

24 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

24 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

TP2

C666

2.2uF

C51

0.1uF

D15Green_LED

R41 10.0K

L2

742792780J9

CON2

12

C36

2.2uF

C54

2.2uF

C667

0.1uF

R350220D14Green_LED

C32

39pF

R45

4.70K, 1%

U17

FT232R

VCCIO1RXD

2

RI3

GN

D1

4

NC35

DSR6

DCD7

CTS8

CBUS49

CBUS210

USBDP14

NC513NC412

CBUS311

GN

D2

17

USBDM15

3V3OUT16

RESET18

VCC19

CBUS022 NC2

23

AG

ND

24

CBUS121

GN

D3

20

NC125

OSCO28

NC629

TXD30

DTR31

RTS32

OSCI27

TE

ST

26

EP

AD

_G

ND

33

R538 0

C668

0.1uFU50

SN65HVD230

D1

GND2

VCC3

R4

VREF5

CANL6CANH7

RS8

R51 10.0K

R550 120

C34

4.7uF

C42

0.1uF

R39 0

R539 DNI

R52 0R53

DNI

R349220

C33

39pF

C37

0.1uF

U12

TPD4S012DRYR

VB

US

6

ID3

D+

1

D-

2

NC

5G

ND

4

J8USB MINI-B

12345

6 7

R272 DNI

XJ2

881545-2

J35

61800925023

594837261

10

11

Page 25: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

On-Board USB Blaster II FPGA USB INTERFACE

PLACE NEAR MAX II (U14)

JTAG INTERFACE

PLACE NEAR CY7C68013A

MAX V USB INTERFACE

C_USB_MAX_TDOC_USB_MAX_TMS

C_USB_MAX_TCK

C_USB_MAX_TDI

FX2_D_NFX2_D_P

FX2_WAKEUPVBUS_5V

VBUS_5V

RESn_JTAG_TXJTAG_TX

FX2_PD4FX2_PD3

FX2_PD0FX2_PD1FX2_PD2

FX2_PD5FX2_PD6FX2_PD7

24M_XTALIN24M_XTALOUT

FX2_PB0FX2_PB1FX2_PB2FX2_PB3FX2_PB4FX2_PB5FX2_PB6FX2_PB7

FX2_PA1FX2_PA2FX2_PA3FX2_PA4FX2_PA5FX2_PA6FX2_PA7

USB_B2_CLK

FX2_RESETn

USB_B2_DATA[7:0]

USB_ADDR[1:0]

USB_FULLUSB_EMPTYUSB_SCLUSB_SDAUSB_B2_CLKUSB_RESETnUSB_OEnUSB_RDnUSB_WRn

FX2_SDA MAX_SDA

RESn_SC_RXSC_RX

RESn_SC_TXSC_TX

RESn_JTAG_RXJTAG_RX

JTAG_BLASTER_TDO

JTAG_TMSJTAG_BLASTER_TDI

JTAG_TCK

USB_DISABLEnFX2_FLAGCFX2_FLAGB

FX2_WAKEUP

FX2_SLWRnFX2_SLRDn

FX2_FLAGA

FX2_SCLFX2_SDA

FX2_RESETn

USB_SCLUSB_SDAUSB_FULLUSB_EMPTY

FACTORY_STATUSM570_CLOCK

FACTORY_REQUEST

FACTORY_REQUEST JTAG_BLASTER_TDOJTAG_BLASTER_TDIJTAG_TMSJTAG_TCK

C_JTAG_TDOC_JTAG_TDIC_JTAG_TMSC_JTAG_TCK

M570_PCIE_JTAG_EN

FX2_PD2FX2_PD0

FX2_PD3FX2_PD1

JTAG_BLASTER_TDI

USB_CFG[11:0]

C_USB_MAX_TDI

USB_B2_CLK

C_USB_MAX_TMS

MAX_SDA

C_USB_MAX_TCK

C_USB_MAX_TDO

FX2_RESETn

EXTRA_SIG[2:0]

FX2_FLAGC

FX2_PA3

FX2_PA2

FX2_PA4

FX2_PA7

FX2_PB4

FX2_PB7

FX2_FLAGA

FX2_PB5

FX2_FLAGB

FX2_PA1

FX2_PA6

FX2_PB0

FX2_PB2

USB_DISABLEn

FX2_SLWRn

JTAG_TX

M570_CLOCKUSB_CFG7

FX2_PB6

FX2_SCL

FX2_PB1FX2_PB3

FX2_PD4FX2_PD6

C_JTAG_TCK

FX2_SLRDn

FX2_PA5FX2_PD5FX2_PD7

C_JTAG_TDIC_JTAG_TMSC_JTAG_TDO

JTAG_RXFACTORY_REQUEST

USB_RESETnUSB_OEnUSB_RDnUSB_WRnFACTORY_STATUS

USB_CFG5

SC_RXSC_TX

USB_CFG3

USB_CFG4

USB_CFG6EXTRA_SIG1

USB_CFG2USB_CFG9

USB_CFG1USB_B2_DATA2

USB_B2_DATA0USB_B2_DATA1

USB_B2_DATA3USB_B2_DATA4

USB_B2_DATA7USB_B2_DATA5USB_B2_DATA6

RSTUSB_CFG8

TRSTUSB_FULLUSB_EMPTYUSB_CFG11USB_SCLUSB_SDAEXTRA_SIG2USB_CFG10USB_CFG0

M570_PCIE_JTAG_EN

EXTRA_SIG0

C_USB_MAX_TDI

C_USB_MAX_TMSC_USB_MAX_TCK

C_USB_MAX_TDO

3.3V3.3V

3.3V3.3V

1V83.3V

1V8

3.3V

3.3V

1.5V_REG_HPS

2.5V_REG_HPS

3.3V

1V8

1.5V_REG_HPS

1.5V_REG_HPS

USB_B2_DATA[7:0]4

USB_FULL4USB_EMPTY4

USB_SDA4

USB_RESETn4USB_OEn4USB_RDn4USB_WRn4

JTAG_BLASTER_TDO12

JTAG_TMS12JTAG_TCK12

JTAG_BLASTER_TDI12

USB_DISABLEn12

USB_ADDR[1:0]

USB_SCL4

FACTORY_STATUS16M570_CLOCK16

USB_B2_CLK4,16

FACTORY_REQUEST16

M570_PCIE_JTAG_EN16

USB_CFG[11:0]16

EXTRA_SIG[2:0]16

TRST 16RST 16

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

25 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

25 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

25 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R537 0

R286 1.00K

U53

TPD2EUSB30

D-2D+1

GND3

R216100K

R551 2.00K

C233

12pF

R520 56.2

C216 0.1uF

C682

0.1uF

R545 1.00k

J37USB MINI-B

12345

67U48

MAX811

GND1

RESET2

VCC4

MR3

C680

0.1uF

J38

DNI

11

33

55

77

22

44

66

88

99

1010

R5300

R518 56.2

C655

0.1uF

R562

20.0KC677

0.1uF

C654

0.1uF

MAX IICONFIGURATION

U47D

EPM570GF100

IO2/GCLK2pF8

IO2/GCLK3pE10

IO1/DEV_CLRnK9

IO1/DEV_OEJ7

IO1/GCLK0pE2

IO1/GCLK1pE1

TCKH3 TDIH2

TMSJ1

TDOJ2

R561 10.0K

C675

0.1uF

R211 DNI

R542 1.00kR544 1.00k

R5350

V43

C234

12pF

D30

Green_LED

R265 DNI

MAX IIBANK 1

U47B

EPM570GF100

IO_B1_B1B1

IO_B1_C1C1

IO_B1_C2C2

IO_B1_D1D1

IO_B1_D2D2

IO_B1_D3D3

IO_B1_E3E3

IO_B1_F1F1

IO_B1_F2F2

IO_B1_F3F3

IO_B1_G1G1

IO_B1_G2G2

IO_B1_G3G3

IO_B1_H1H1

IO_B1_H4H4

IO_B1_H7H7

IO_B1_H8H8

IO_B1_J3J3

IO_B1_J4J4

IO_B1_J5J5

IO_B1_J6J6

IO_B1_J8J8

IO_B1_J9J9

IO_B1_K1K1

IO_B1_K10K10

IO_B1_K2K2

IO_B1_K3K3

IO_B1_K4K4

IO_B1_K5K5

IO_B1_K6K6

IO_B1_K7K7

IO_B1_K8K8

C661

0.1uF

R559 0

C676

0.1uF

R558 0

MAX IIPOWER

U47A

EPM570GF100

GNDINTC5

GNDINTF5 GNDINTE6

GNDIOD5

GNDIOG7

GNDIOD7

GNDIOG5 GNDIOF6 GNDIOE5

GNDINTH5

VCCINTC6

VCCINTE7

VCCINTH6VCCINTF4

VCCIO2F7VCCIO2D6VCCIO2D4

VCCIO1E4

VCCIO1G4

VCCIO1G6

C653

0.1uF

U51

CY7C68013A_VFBGA

RDY0A1

RDY1B1

XTALINC1

AVCCD1

DMINUSE1

AGNDF1

VCCG1

GNDH1

PD7A2

CLKOUTB2

XTALOUTC2

AVCCD2

DPLUSE2

AGNDF2

IFCLKG2

RESERVEDH2

PD5A3PD4B3

PD6C3

SCLF3

SDAG3

PB0H3

GNDA4

GNDB4

GNDC4

PB1F4

PB3G4PB2H4

VCCA5

VCCB5

PB6F5PB5G5PB4H5

PD3A6PD2B6

PA7C6

PA4F6

PA1G6

PB7H6

PD1A7

WAKEUPB7

PA6C7

GNDD7

VCCE7

PA3F7

CTL1G7CTL0H7

PD0A8

RESETB8

PA5C8

GNDD8

VCCE8

PA2F8

PA0G8

CTL2H8

VCCC5

D31

Green_LED

C672

0.1uF

R5290

R519 56.2

C647

0.1uF

R531 0

C648

0.1uF

R5360

R553 2.00K

R541 1.00k

C671

0.1uF

C681

0.1uF

Y5

24.00MHz

1 3

24

C2394.7nF

D29

Green_LED

R2771M

R517 56.2

V42C669

0.1uF

R560 0

R321 1.00K

R543 1.00k

D28

Green_LED

MAX IIBANK 2

U47C

EPM570GF100

IO_B2_A1A1

IO_B2_A10A10

IO_B2_A2A2

IO_B2_A3A3

IO_B2_A4A4

IO_B2_A7A7

IO_B2_B8B8

IO_B2_D10D10

IO_B2_D9D9

IO_B2_A9A9

IO_B2_C7C7

IO_B2_B2B2

IO_B2_B3B3

IO_B2_B4B4

IO_B2_B5B5

IO_B2_B9B9

IO_B2_C9C9

IO_B2_C8C8

IO_B2_B7B7

IO_B2_B10B10

IO_B2_C3C3

IO_B2_C4C4

IO_B2_A6A6

IO_B2_F10F10

IO_B2_F9F9

IO_B2_D8D8

IO_B2_E8E8

IO_B2_C10C10

IO_B2_B6B6

IO_B2_E9E9

IO_B2_A5A5IO_B2_A8A8

IO_B2_G10G10

IO_B2_G8G8

IO_B2_G9G9

IO_B2_H10H10IO_B2_H9H9

IO_B2_J10J10

V39

Page 26: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FPGA Power Monitor

GND pad

LTC2978Address SelectPWRMON2 = 7'h5D

SCL_PMSDA_PM

PM_ALERTBPM_PWRGD

PM2_FAULTB00PM2_FAULTB01PM2_FAULTB10PM2_FAULTB11

PM_CNTL0PM_CNTL1PM_RSTn

PM_ALERTBPM_PWRGD

1.5V_FPGA_VDACP2 PM_SHARE_CLK

PM2_ASEL0PM2_ASEL1

PM_CNTL1PM_CNTL0

SDA_PM

PM_SHARE_CLK

SCL_PM

PM2_FAULTB10

PM2_FAULTB00

PM2_FAULTB11

PM_RSTn

PM2_FAULTB01

PM2_ASEL0PM2_ASEL1

PM2_FAULTB10

PM2_FAULTB00

PM2_FAULTB11

PM2_FAULTB01

2.5V_FPGA_V_P

1.1V_VCC_V_P

1.5V_FPGA_I_P1.5V_FPGA_I_N

1.1V_VCC_V_N

2.5V_FPGA_I_N2.5V_FPGA_I_P

1.1V_VCC_I_N

1.5V_FPGA_V_P

1.1V_VCC_I_P

1.5V_FPGA_V_N

2.5V_FPGA_V_N

TSENSE_FAN_CNTL

2.5V_FPGA_RUN

1.5V_FPGA_RUN

1.1V_FPGA_RUN

1.1V_FPGA_VDACP4

1.1V_FPGA_VDACP4

2.5V_FPGA_VDACP01.5V_FPGA_VDACP2

SDA_PMSCL_PM

SDA_PMSCL_PM

2.5V_FPGA_P

2.5V_FPGA_N

1.5V_FPGA_P

1.5V_FPGA_N

1.1V_VCC_P

1.1V_VCC_N

PM2_ASEL0

2.5V_FPGA_VDACP0

12V

3.3V_PM_FPGA

12V

1.1V_VCC

1.1V_REG_VCC

1.5V_FPGA

1.5V_REG_FPGA

2.5V_FPGA

2.5V_REG_FPGA

3.3V_PM_FPGA

3.3V_PM_FPGA

SCL_PM27

SDA_PM27

PM_PWRGD27

PM2_FAULTB00PM2_FAULTB01PM2_FAULTB10PM2_FAULTB11

PM_CNTL027

PM_CNTL127

PM_RSTn27

PM_ALERTB27

PM_SHARE_CLK27

OVERTEMP16

2.5V_FPGA_RUN31

1.5V_FPGA_RUN30

1.1V_FPGA_RUN29

2.5V_FPGA_VDACP0311.5V_FPGA_VDACP2301.1V_FPGA_VDACP429

I2C_SDA 7,16,20

I2C_SCL 7,16,20

Title

SizeDocument Number

Rev

Date: Sheet of

Altera Corporation, 101 Innovation Drive, San Jose, CA

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

26 40Wednesday, March 20, 2013

Title

SizeDocument Number

Rev

Date: Sheet of

Altera Corporation, 101 Innovation Drive, San Jose, CA

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

26 40Wednesday, March 20, 2013

Title

SizeDocument Number

Rev

Date: Sheet of

Altera Corporation, 101 Innovation Drive, San Jose, CA

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

26 40Wednesday, March 20, 2013

R88 1K

R77 1K

R69 1K

C88 0.1uF

C99

0.1uf

R66 1K

C87 0.1uF

R10510K

V44

SENSE_PAD

RSNS1

SNS2

R83 1K

R10710K

V49

SENSE_PAD

RSNS1

SNS2

R65 1K

V41

SENSE_PAD

RSNS1

SNS2

C72 0.1uF

R422

0

C73 0.1uF

C69 0.1uF

C82 0.1uF

J21

22_23_2021

12

R67 1K

R70 1K

C68 0.1uF

C70 0.1uF

R104

10K

C91

0.1uf

C77 0.1uF

R10610K

R416 10K

V45

SENSE_PAD

RSNS1

SNS2

C93 0.1uF

R68 1K

R87 1K

V48

SENSE_PAD

RSNS1

SNS2

V40

SENSE_PAD

RSNS1

SNS2

R108

10K

R73 1K

C92 0.1uF

B3

FAN_2pin_Conn

C98

0.1uf

R82 1K

R421

0

U26

LTC2978

VOUT_EN48

VOUT_EN59

VOUT_EN610

VOUT_EN711

VIN_EN12

NC13

VIN_SNS14

VPWR15

VDD33_OUT16

VDD33_IN17

VDD2518WP

19 PWRGD20SHARE_CLK

21

WDI/RESET22

FAULTB0023

FAULTB0124

FAULTB1025

FAULTB1126

SDA27 SCL28

ALERTB29

CONTROL030

CONTROL131

ASEL032

ASEL133

REFP34

REFM35VSENSEP0

36

VSENSEM037

VDACM038VDACP039

VDACP140

VDACM141

VSENSEP142

VSENSEM143

VDACP244

VDACM245

VSENSEP246

VSENSEM247

VSENSEP348

VSENSEM349

VDACP350

VDACM351

VSENSEP452

VSENSEM61

VSENSEP72

VSENSEM73

VOUT_EN04

VOUT_EN15

VOUT_EN26

VOUT_EN37

VSENSEM453

VDACM454VDACP455

VDACP556

VDACM557

VDACM658VDACP659

VDACP760

VDACM761

VSENSEP562

VSENSEM563

VSENSEP664

E-PAD65

C71 0.1uF

C481

0.1uf

R417 10K

Q1

FDV305N

Page 27: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

HPS Power Monitor

GND pad

these GND connections toeach VSENSEMx pinneeds to be placed closeto a GND pin of the BGA!

LTC2978Address SelectPWRMON1 = 7'h5C

I2C Interface

1.1V_HPS_V_P

1.1V_HPS_VDACP0

PM_ALERTBPM_PWRGD

2.5_HPS_VDACP4

1.5V_HPS_VDACP2

1.1V_HPS_I_N1.1V_HPS_I_P

1.5V_HPS_I_P

1.1V_HPS_V_N

PM_ALERTBPM_PWRGD

PM1_FAULTB00PM1_FAULTB01PM1_FAULTB10PM1_FAULTB11

PM_CNTL0PM_CNTL1PM_RSTn

PM_SHARE_CLK

PM_PWRGD

SDA_PMSCL_PM

PM1_ASEL0

PM_RSTn

PM_ALERTBPM_CNTL1

SCL_PMSDA_PM

1.1V_HPS_VDACP0

2.5_HPS_VDACP41.5V_HPS_VDACP2

PM_SHARE_CLK

PM1_ASEL1

PM_SHARE_CLK

SCL_PM

PM1_FAULTB10

PM1_FAULTB00

PM1_FAULTB11

PM_RSTn

PM1_FAULTB01

SDA_PMPM1_ASEL0PM1_ASEL1

PM_CNTL1PM_CNTL0

SDA_PMSCL_PM

3.3_HPS_VDACP6

3.3_HPS_VDACP6

EN_1.5V_HPS

EN_1.1V_HPS

EN_2.5V_HPS

EN_3.3V_HPSEN_1.5V_HPSEN_1.1V_HPS

EN_2.5V_HPSEN_3.3V_HPS

PM1_FAULTB10

PM1_FAULTB00

PM1_FAULTB11

PM_ALERTB

PM1_FAULTB01

1.1V_HPS_P

1.1V_HPS_N

1.5V_HPS_P

1.5V_HPS_N

2.5V_HPS_P

2.5V_HPS_N

3.3V_HPS_P

3.3V_HPS_N

PM_CNTL0PM_CNTL1

3.3V_HPS_V_P

2.5V_HPS_V_P1.5V_HPS_I_N

2.5V_HPS_V_N

3.3V_HPS_I_N3.3V_HPS_I_P

2.5V_HPS_I_N

1.5V_HPS_V_P

2.5V_HPS_I_P

1.5V_HPS_V_N

3.3V_HPS_V_N

12V

3.3V_PM_HPS

3.3V_HPS

3.3V_REG_HPS

2.5V_HPS

2.5V_REG_HPS

1.5V_HPS

1.5V_REG_HPS

1.1V_HPS

1.1V_REG_HPS

3.3V_PM_HPS

SCL_PM26 SDA_PM26

1.1V_HPS_VDACP0351.5V_HPS_VDACP2332.5_HPS_VDACP432

PM_PWRGD26

PM1_FAULTB00PM1_FAULTB01PM1_FAULTB10PM1_FAULTB11

PM_CNTL026

PM_CNTL126

PM_RSTn26

PM_ALERTB26

PM_SHARE_CLK26

3.3_HPS_VDACP634

EN_1.1V_HPS35EN_1.5V_HPS33EN_2.5V_HPS32EN_3.3V_HPS34

I2C_SDA_HPS 6,18,23I2C_SCL_HPS 6,18,23

Title

SizeDocument Number

Rev

Date: Sheet of

Altera Corporation, 101 Innovation Drive, San Jose, CA

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

27 40Wednesday, March 20, 2013

Title

SizeDocument Number

Rev

Date: Sheet of

Altera Corporation, 101 Innovation Drive, San Jose, CA

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

27 40Wednesday, March 20, 2013

Title

SizeDocument Number

Rev

Date: Sheet of

Altera Corporation, 101 Innovation Drive, San Jose, CA

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

27 40Wednesday, March 20, 2013

R17210K

V14

SENSE_PAD

RSNS1

SNS2

R112 1K

R17010K

V6

SENSE_PAD

RSNS1

SNS2

R113 1K

R155 1K

V21

SENSE_PAD

RSNS1

SNS2

R118 1K

R167

10K

C157

0.1uf

C122 0.1uF

C156

0.1uf

V3

SENSE_PAD

RSNS1

SNS2

R475

0

C159 0.1uF

C121 0.1uF

R140 1K

R141 1K

R139 1K

R154 1K

J24

2x6HDR

11

22

33

44

55

66

77

88

99

1010

1212

1111

R114 1K

R16210K

R16810K

R17310K

R17110K

R16410K

C126 0.1uF

V13

SENSE_PAD

RSNS1

SNS2

C138 0.1uF

C143 0.1uF

R131 1K

C137 0.1uF

R115 1K

V7

SENSE_PAD

RSNS1

SNS2

C580

0.1uf

R119 1K

R150 1K

R16910K

V22

SENSE_PAD

RSNS1

SNS2

C132 0.1uF

C125 0.1uF

C167

0.1uf

V2

SENSE_PAD

RSNS1

SNS2

R149 1K

C128 0.1uF

C136 0.1uF

U34

LTC2978

VOUT_EN48

VOUT_EN59

VOUT_EN610

VOUT_EN711

VIN_EN12

NC13

VIN_SNS14

VPWR15

VDD33_OUT16

VDD33_IN17

VDD2518WP

19 PWRGD20SHARE_CLK

21

WDI/RESET22

FAULTB0023

FAULTB0124

FAULTB1025

FAULTB1126

SDA27 SCL28

ALERTB29

CONTROL030

CONTROL131

ASEL032

ASEL133

REFP34

REFM35VSENSEP0

36

VSENSEM037

VDACM038VDACP039

VDACP140

VDACM141

VSENSEP142

VSENSEM143

VDACP244

VDACM245

VSENSEP246

VSENSEM247

VSENSEP348

VSENSEM349

VDACP350

VDACM351

VSENSEP452

VSENSEM61

VSENSEP72

VSENSEM73

VOUT_EN04

VOUT_EN15

VOUT_EN26

VOUT_EN37

VSENSEM453

VDACM454VDACP455

VDACP556

VDACM557

VDACM658VDACP659

VDACP760

VDACM761

VSENSEP562

VSENSEM563

VSENSEP664

E-PAD65

C123 0.1uF

C127 0.1uF

C144 0.1uF

R116 1K

C124 0.1uF

R16310K

C158 0.1uF

R474

0

R16610K

R16510K

R117 1K

Page 28: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Power 1 - DC Input & 12V, 3.3V Output

POWER LED

19VDC Input

LTC3855_S2PLTC3855_S2N

PG_12V

VFB2

INTVCC_1

INTVCC_1

VFB2

LTC3855_S1N

INTVCC_1

3.3V_SHDNn

DIFFOUT

12V_SHDNn

DIFFOUT

3.3V_SHDNn12V_SHDNn

LTC3855_S1P

5.0V

DC_IN

12V_REG

3.3V

DC_IN

3.3V

DC_INPUT

DC_IN DC_IN

DC_IN

3.3V

12V

12V_ATX

12V_REG

12V_ATX

12V_ATX12V_ATXTitle

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

28 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

28 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

28 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

drain-tab

Q6

RJK0305DPB4

5

31 2

C540

330uF

10V

C564100uF

6.3v

C187

4.7uF

C174

0.1uF

C21022uF25V

C665

68uF25V

R200

DNI

C196

47uF35V

R17920.0K

R20511.5K

drain-tab

Q2

RJK0301DPB4

5

31 2

R19857.6K

J20

ATX-POWER_4P

COM1

COM2

+12V3

+12V4

D24

CMDSH-3

D27

MMBD1205

R1773.09K

V46

SENSE_PAD

RSNS1

SNS2

C663

68uF25V

R25711.3K

L23

0.68uH12

drain-tab

Q4RJK0305DPB

4

5

31 2

Q8

FDMC8878

5

123

4

C185

22pF

C16622uF25V

R256215.0KV47

SENSE_PAD

RS

NS

1S

NS

2

R4704.02K

SW5SW SLIDE-4P2T

1

239

8

7

4

56

10

1211

J22CONN JACK PWR

3

21

V8

SENSE_PAD

RS

NS

1S

NS

2

R17820.0K

R26720.0K

C19722uF25V

C181 0.1uF

drain-tab

Q5RJK0301DPB

4

5

31 2

U41

FDMC8878

5

123

4

R270 100K

R264100K

C664

68uF25V

R26920.0K

C175

47uF35V

C186

82pF

R206100K

C194

1000pF

D35

BLUE LED

C192100pF

U60

LTC4357

OUT1

GND4VDD6

NC5

GATE3

IN2

EP_GND7

Q7

FDMC8878

5

123

4

R548

1.00k

U63

LTC4357

OUT1

GND4VDD6

NC5

GATE3

IN2

EP_GND7

L14

1.5uH12

R180169.0K

R199 3.92K

gnd-pad

U43

LTC3855EUJ

TK/SS11 ITH12

VFB13

SGND14

VFB25

ITH26

TK/SS27

SENSE2+8

SENSE2-9

PGOOD217

NC18

PGOOD116

TG220

BOOST221

PGND222

BG223

EXTVCC24 INTVCC25

PGND128

SW219

DIFFP10

DIFFN11

DIFFOUT12

RUN213

ILIM114

ILIM215

VIN26

BG127

BOOST129

TG130

SW131

CLKOUT32 PHSASMD33 MODE/PLLIN34 FREQ35

ITEMP236

ITEMP137 RUN138

SENSE1+39

SENSE1-40

SGND241

drain-tab

Q3RJK0305DPB

4

5

31 2

R193

2.55K

C193

0.1uF

D26CMDSH-3

U44

FDMC8878

5

123

4

R192

52.3K

U62

LTC4357

OUT1

GND4VDD6

NC5

GATE3

IN2

EP_GND7

C195 0.1uF

C17622uF25V

U59

LTC4357

OUT1

GND4VDD6

NC5

GATE3

IN2

EP_GND7

V9

SENSE_PAD

RSNS1

SNS2

R268100K

C180

22pF

R261100K

C179

1000pF

Page 29: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Power 2

FSW = 350kHz

CAD Note:Regulator input capsPlace near regulator controller

SW

REF

TRACK

SW

BOOST

INTVCC

INTVCC

INTVCC

INTVCC

INTVCCMODE

VOUT

SNS_M

SNS_P

SNS_P

SNS_M12V

1.1V_VCC

12V

1.1V_REG_VCC

1.1V_REG_VCC

1.1V_VCC 1.1V_VCCEL

12V

1.1V_FPGA_RUN26

1.1V_FPGA_VDACP426

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

29 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

29 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

29 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

C213

47uF35V

C118

330uF6.3V

V5

SENSE_PAD

RS

NS

1S

NS

2

C133100UF6.3VU39B

LTC3613EWKH_6

PVIN72

PVIN83

PVIN94

PVIN105

PVIN116

PVIN127

PVIN138

PVIN149

SGND316

SGND417

SGND519

SGND628

SGND729 PGND9

37PGND838PGND739PGND640PGND541PGND442PGND343PGND244

SW945SW846SW747SW648SW549SW450SW351

NC52

PVIN653 PVIN554 PVIN455 PVIN356

SGND259

SW258

PVIN257

R18213.7K

1%

C170

0.01uF

R195 10

R158

115K (1%)

R160

DNI

U39A

LTC3613EWKH_6

PGOOD13

SNS+14

SNS-15

VOUT18

VOSNS-20

VOSNS+21

TRACK/SS22

ITH23

VRNG24

RT25

RUN26

EXTVCC30

MODE/PLLIN31

INTVCC233

PGND136

NC27

SW110

PVIN11

BOOST11

SVIN132

SG

ND

12

INTVCC134

SW235

C160DNI

R152DNI

C1454.7uF

C18822uF25V

1210

R142 0

C19922uF25V

1210

R461 0.001

R15110.0K

R187

100K

L10

3A, 30 Ohm FB

C182

1.0nF

C183

0.1uF

C35

47uF35V

C172270pF

C139100UF6.3V

R1320.0015

L12 0.47uH

Isat = 20A

Wurth Elektronik744314047

1 2

R194 10

R18116.5K1%

C19822uF25V

1210

C18922uF25V

1210

V4

SENSE_PAD

RS

NS

1S

NS

2

R183215.0K

R159

0

C17147pF

C146

0.1uF

D25

CMDSH-3

R174 21K (1%)

Page 30: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Power 3 - 1.5V FPGA

CAD Note:Regulator input capsPlace near regulator controller

Design Note:DNI for ES device

Cad Note:1 overlapping pad

Design Note:Ith is tied to INTVCC forinternal compensation

CAD Note:Overlap R289 & R290pads at 1 of the pinsPlace resistor & capnear pin 6

Design Note:Added extra 1uF at INTVCC due tosourcing Vbias pin of LTC3025-1

Design Note:tss = Css x 0.6V/2uARamp rate ~990us

Cad Note:Place output caps near inductor

Design Note:Prefer 0603 size cap25V rated voltage is sufficient

3.3V logic signal

PGOOD_1.5V

LTC3605_RUN

LTC3605_SVIN

LTC3605_INTVCC

LTC3605_FB

LTC3605_FB

LTC3605_SW

LTC3605_BOOST

LTC3605_SS

LTC3605_RT

LTC3605_ITHLTC3605_INTVCC

1.5V_FPGA_RUN

1.5V_REG_FPGA 1.5V_FPGA

3.3V

12V

1.5V_FPGA_RUN 26

1.5V_FPGA_VDACP226

Title

Size Document Number Rev

Date: Sheet of

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

30 40Wednesday, March 20, 2013

Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

30 40Wednesday, March 20, 2013

Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

30 40Wednesday, March 20, 2013

Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

C612 33pF

R197 24.0K 1%

C623

22uFEXPOSED PAD

LTC3605EUFU42

RT1

PHMODE2

MODE3

FB4

TRACK/SS5

ITH6

RU

N7

PG

OO

D8

VO

N9

PG

ND

10

SW

11

SW

12

SW13

SW14

SW15

SW16

PVIN17

PVIN18

SV

IN19

BO

OS

T20

INT

VC

C21

SG

ND

22

CLK

OU

T23

CLK

IN24

PG

ND

25

C611 3300pF

L19

1.2uH

Isat = 11A

R196 DNI

C610 2.2uF

C200 1200pF

R506 215.0K

C19022uF25V

1210

R2140.003

C205

22uF

C17322uF25V

1210

R185 10

C622

22uFR204

15K

1%

C624

22uF

R203

10.0K

R507 0

C609

0.1UF

50V

C201

39pF

R184169.0K

C593

0.1uF

25V

D22

CMDSH-3C595 1.0UF

R505 100K

Page 31: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Cad Note:Place near INTVCC pin

Power 3 - 2.5V FPGA

Design Note:DCR = 40m ohmsCAD Note:

Regulator input capsPlace near regulator controller

Design Note:DNI for ES device

Cad Note:1 overlapping pad

Design Note:Ith is tied to INTVCC forinternal compensation

CAD Note:Overlap R289 & R290pads at 1 of the pinsPlace resistor & capnear pin 6

Design Note:Added extra 1uF at INTVCC due tosourcing Vbias pin of LTC3025-1

Design Note:tss = Css x 0.6V/2uARamp rate ~990us

Cad Note:Place output caps near inductor

Design Note:Prefer 0603 size cap25V rated voltage is sufficient

PGOOD_2.5V

LTC3605_RUN

LTC3605_SVIN

LTC3605_INTVCC

LTC3605_FB

LTC3605_FB

LTC3605_SW

LTC3605_BOOST

LTC3605_SS

LTC3605_RT

LTC3605_ITHLTC3605_INTVCC

2.5V_FPGA_RUN

2.5V_FPGA_FILT2.5V_FPGA

3.3V

12V

2.5V_FPGA2.5V_REG_FPGA

2.5V_FPGA_RUN 26

2.5V_FPGA_VDACP026

Title

Size Document Number Rev

Date: Sheet of

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

31 40Wednesday, March 20, 2013

Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

31 40Wednesday, March 20, 2013

Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

31 40Wednesday, March 20, 2013

Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R222

4.70K, 1%

R208 0.001

C657 10pF

C208

39pF

C20222uF25V

1210

C212 560pF

C20322uF25V

1210

L20

1.2uH

Isat = 11A

R215

15K

1%

R521 215.0K

R219

137K

1%

C651

22uF

C640

0.1uF

25V

L21

3A, 30 Ohm FB

R522 100K

C209

22uF

R207 10

C660 1.0UF

C652

0.1UF

50V

D33

CMDSH-3

C659 2.2uF

EXPOSED PAD

LTC3605EUFU46

RT1

PHMODE2

MODE3

FB4

TRACK/SS5

ITH6

RU

N7

PG

OO

D8

VO

N9

PG

ND

10

SW

11

SW

12

SW13

SW14

SW15

SW16

PVIN17

PVIN18

SV

IN19

BO

OS

T20

INT

VC

C21

SG

ND

22

CLK

OU

T23

CLK

IN24

PG

ND

25

R532 0

R221 47.5K 1%

R220 DNI

C658 3300pFC639

22uF

C621

22uF

Page 32: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Cad Note:Place near INTVCC pin

Power 3 - 2.5V HPS

Design Note:DCR = 40m ohms

CAD Note:Regulator input capsPlace near regulator controller

Design Note:Ith is tied to INTVCC forinternal compensation

CAD Note:Overlap R289 & R290pads at 1 of the pinsPlace resistor & capnear pin 6

Design Note:Added extra 1uF at INTVCC due tosourcing Vbias pin of LTC3025-1

Design Note:tss = Css x 0.6V/2uARamp rate ~990us

Cad Note:Place output caps near inductor

Design Note:Prefer 0603 size cap25V rated voltage is sufficient

PGOOD_2.5V

RUN_2.5V_HPS

LTC3605_SVIN

LTC3605_INTVCC

LTC3605_FB

LTC3605_FB

LTC3605_SW

LTC3605_BOOST

LTC3605_SS

LTC3605_RT

LTC3605_ITHLTC3605_INTVCC

EN_2.5V_HPS

2.5V_HPS_FILT2.5V_HPS

3.3V

12V

2.5V_HPS2.5V_REG_HPS

3.3V

EN_2.5V_HPS 27

2.5_HPS_VDACP427

Title

Size Document Number Rev

Date: Sheet of

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

32 40Wednesday, March 20, 2013

Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

32 40Wednesday, March 20, 2013

Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

32 40Wednesday, March 20, 2013

Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

C581

22uF

R191

4.70K, 1%

C606 3300pF

R190 47.5K 1%

C184

22uF

C191 560pF

R186

15K

1%

C178

39pFR189 DNI

C592

0.1uF

25V

C608 1.0UF

C604

22uF

R476 100K

R175 10

R188

137K

1%

C607 2.2uF

EXPOSED PAD

LTC3605EUFU40

RT1

PHMODE2

MODE3

FB4

TRACK/SS5

ITH6

RU

N7

PG

OO

D8

VO

N9

PG

ND

10

SW

11

SW

12

SW13

SW14

SW15

SW16

PVIN17

PVIN18

SV

IN19

BO

OS

T20

INT

VC

C21

SG

ND

22

CLK

OU

T23

CLK

IN24

PG

ND

25

R493 10.0K

D23

CMDSH-3

R492 0

L18

1.2uH

Isat = 11A

C605 10pF

C16322uF25V

1210

C16422uF25V

1210C594

0.1UF

50V

L17

3A, 30 Ohm FB

C591

22uF

R176 0.001

R491 178K1%

Page 33: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Power 3 - 1.5V & 1.5V FPGA

CAD Note:Regulator input capsPlace near regulator controller

Design Note:Ith is tied to INTVCC forinternal compensation

CAD Note:Overlap R289 & R290pads at 1 of the pinsPlace resistor & capnear pin 6

Design Note:Added extra 1uF at INTVCC due tosourcing Vbias pin of LTC3025-1

Design Note:tss = Css x 0.6V/2uARamp rate ~990us

Cad Note:Place output caps near inductor

Design Note:Prefer 0603 size cap25V rated voltage is sufficient

PGOOD_1.5V

RUN_1.5V_HPS

LTC3605_SVIN

LTC3605_INTVCC

LTC3605_FB

LTC3605_FB

LTC3605_SW

LTC3605_BOOST

LTC3605_SS

LTC3605_RT

LTC3605_ITHLTC3605_INTVCC

EN_1.5V_HPS

1.5V_REG_HPS 1.5V_HPS

3.3V

12V

EN_1.5V_HPS 27

1.5V_HPS_VDACP227

Title

Size Document Number Rev

Date: Sheet of

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

33 40Wednesday, March 20, 2013

Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

33 40Wednesday, March 20, 2013

Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

33 40Wednesday, March 20, 2013

Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

D19

CMDSH-3

R124169.0K

C513 2.2uF

C131

39pFR123 DNI

R122 24.0K 1%

C130

22uF

R1340.003

C565

22uFEXPOSED PAD

LTC3605EUFU33

RT1

PHMODE2

MODE3

FB4

TRACK/SS5

ITH6

RU

N7

PG

OO

D8

VO

N9

PG

ND

10

SW

11

SW

12

SW13

SW14

SW15

SW16

PVIN17

PVIN18

SV

IN19

BO

OS

T20

INT

VC

C21

SG

ND

22

CLK

OU

T23

CLK

IN24

PG

ND

25

L13

1.2uH

Isat = 11A

C541

0.1UF

50V

R148 10

C512 1.0UF

C106 1200pF

R130

15K

1%

C542

22uF

C15222uF25V

1210

R121

10.0KR454 0

R455 215.0K

C514 3300pF

C555

0.1uF

25V

C515 33pF

C556

22uF

C15122uF25V

1210

R460 100K

Page 34: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Cad Note:Place near INTVCC pin

Power 3 - 3.3V HPS

CAD Note:Regulator input capsPlace near regulator controller

Design Note:Ith is tied to INTVCC forinternal compensation

CAD Note:Overlap R289 & R290pads at 1 of the pinsPlace resistor & capnear pin 6

Design Note:Added extra 1uF at INTVCC due tosourcing Vbias pin of LTC3025-1

Design Note:tss = Css x 0.6V/2uARamp rate ~990us

Cad Note:Place output caps near inductor

Design Note:Prefer 0603 size cap25V rated voltage is sufficient

3.3V logic signal

PGOOD_3.3V

RUN_3.3V_HPS

LTC3605_SVIN

LTC3605_INTVCC

LTC3605_FB

LTC3605_FB

LTC3605_SW

LTC3605_BOOST

LTC3605_SS

LTC3605_RT

LTC3605_ITHLTC3605_INTVCC

EN_3.3V_HPS

3.3V_HPS

3.3V_REG_HPS

3.3V

12V

3.3V

EN_3.3V_HPS 27

3.3_HPS_VDACP627

Title

Size Document Number Rev

Date: Sheet of

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

34 40Wednesday, March 20, 2013

Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

34 40Wednesday, March 20, 2013

Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

150-0321003-C1 (6XX-44184R) C

Cyclone V SoC FPGA Development Kit Board

B

34 40Wednesday, March 20, 2013

Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R445 0

C467

0.1uF

25V

C485

22uF

R84 10

C489 1.0UF

R446 10.0K

C100

22uFEXPOSED PAD

LTC3605EUFU27

RT1

PHMODE2

MODE3

FB4

TRACK/SS5

ITH6

RU

N7

PG

OO

D8

VO

N9

PG

ND

10

SW

11

SW

12

SW13

SW14

SW15

SW16

PVIN17

PVIN18

SV

IN19

BO

OS

T20

INT

VC

C21

SG

ND

22

CLK

OU

T23

CLK

IN24

PG

ND

25

C94

39pF

C107 220pF

R99

90.9K

1%

C7822uF25V

1210

L8

1.2uH

Isat = 11A

R100 DNI

C487 3300pFC441

22uF

R90 0.001

R102

2.55K

1%

R101 69.8K 1%

R437 100K

D16

CMDSH-3

C488 2.2uF

C466

22uF

C7922uF25V

1210

R89

11.5K

1%

C474

0.1UF

50V

C486 5pF

R444 66.5K

Page 35: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Power - 1.1V_HPS, 5.0V, 1.8V

Fsw=1.7MHz

CAD Note:Regulator input capsPlace near regulator controller

Design Note:0.001 ohm sense resistorminimized IR drop @ 3A

CAD Note:Regulator input capsPlace near regulator controller

Design Note:Ith is tied to INTVCC forinternal compensation

CAD Note:Overlap R289 & R290pads at 1 of the pinsPlace resistor & capnear pin 6

Design Note:Added extra 1uF at INTVCC due tosourcing Vbias pin of LTC3025-1

Design Note:tss = Css x 0.6V/2uARamp rate ~990us

Cad Note:Place output caps near inductor

Design Note:Prefer 0603 size cap25V rated voltage is sufficient

CAD Note:Regulator input capsPlace near regulator controller

FB_5.0V

RUN_1.1V_HPS

LTC3605_SVIN

1.1V_HPS_INTVCC

1.1V_HPS_FB

1.1V_HPS_FB

PGOOD_1.1V_HPS

1.1V_HPS_SW

1.1V_HPS_BOOST

1.1V_HPS_SS

1.1V_HPS_ITH1.1V_HPS_INTVCC

EN_1.1V_HPS

1.1V_HPS_RT

12V

5.0V

5.0V

1V8

1.1V_HPS

1.1V_REG_HPS

3.3V

12V

12V

PGOOD_1.1V_HPS

EN_1.1V_HPS 27

1.1V_HPS_VDACP027

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

35 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

35 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

35 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

L28

6.5uHIsat = 6A

1 2

C1401.0nF

R133 DNI

C557 1000pF

R468 215.0K

EXPOSED PAD

LTC3605EUFU32

RT1

PHMODE2

MODE3

FB4

TRACK/SS5

ITH6

RU

N7

PG

OO

D8

VO

N9

PG

ND

10

SW

11

SW

12

SW13

SW14

SW15

SW16

PVIN17

PVIN18

SV

IN19

BO

OS

T20

INT

VC

C21

SG

ND

22

CLK

OU

T23

CLK

IN24

PG

ND

25

R156

10K

C16822uF25V

C20422uF25V

1210

C567

22uF

C10522uF25V

1210

D20DFLS2302 1

R467 0

R157

52.3K

R146 10.0K

C15047UF6.3V

D21 DFLS23021

D18

CMDSH-3

U36

LT3509EDE

VIN4

BOOST12

BOOST26

SW13

SW25

DA11

DA27

FB114

FB28

RUN/SS113

RUN/SS29

BD12

GND15

SYNC11

RT10

C58222uF25V

1210

C147DNI

R143

10K

C543

0.1UF

50V

L16

6.5uHIsat = 6A

1 2

C516 1.0UF

R147

12.4K

R145

15K

1%

R129

316k

1%

C55868pF

C505

0.1uF

25V

L15

1.2uH

Isat = 11A

C177 22uF25V

C566

22uF

R144

12.4K

R466 100K

C62522uF25V

1210

C148

0.1uF

R153 16.2K

C544 2.2uF

C57322uF25V

1210

C12922uF25V

1210

C161 DNI

C162

0.1uF

C141

39pF

C149

22uF4V

R161 0.001

R120 10

Page 36: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Power 4 - Linear Regulators

DDR3 FPGA VTT, VREF

DDR3 HPS VTT, VREF

3.3V

VTT_FPGA_DDR3

VREF_FPGA_DDR3

1.5V_REG_FPGA

3.3V

VREF_HPS_DDR3

VTT_HPS_DDR3

1.5V_REG_HPS

2.5V_REG_FPGA

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

36 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

36 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

36 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

C619

10uF

C293

0.1uF

C442

10uF

C616

10uF

C618

10uF

R516

10.0K

C292

1uF

C338

10uF

C620

10uF

C475

10uF

C634

1uF

C307

1.0nF

C635

10uF

C636

10uF

C646

1.0nF

U58

TPS51200

VIN10

EN7

PGOOD9

REFOUT6

GN

D_P

AD

11

PG

ND

4

GN

D8

VLDOIN2

REFIN1

VO3

VOSNS5

U61

TPS51200

VIN10

EN7

PGOOD9

REFOUT6

GN

D_P

AD

11

PG

ND

4

GN

D8

VLDOIN2

REFIN1

VO3

VOSNS5

R51310.0K

R511 10.0K

R408

10.0K

C617

10uF

R388 10.0K

C363

10uF

R40910.0K

C339

10uF

C613

0.1uF

C308

10uF

C490

10uF

R510

10.0K

Page 37: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Power 6 - Power & Temperature Monitor

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

37 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

37 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

37 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Page 38: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Power 7 - Cyclone V GX SoC Power

(2.5V)

1.1V_VCC

2.5V_FPGA

2.5V_FPGA

1.5V_FPGA

1.5V_FPGA

2.5V_FPGA

1.1V_HPS

1.5V_HPS

3.3V_HPS

2.5V_FPGA_FILT

1.1V_VCCEL

2.5V_HPS

2.5V_HPS_FILT

3.3V_HPSVREF_HPS_DDR3

VREF_FPGA_DDR3

3.3V_HPS

2.5V_HPS

2.5V_FPGA_FILT

2.5V_VCCAUX_SHARED

2.5V_VCCAUX_SHARED

2.5V_FPGA_FILT

2.5V_HPS

2.5V_HPS_FILT

1.1V_VCCL

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

38 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

38 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

38 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Cyclone V GX SoC Power

5CSXFC6D_F896

U21K

VCCIO3AAC11

VCCIO3AAD8

VCCIO3AAF7

VCCIO3AAG4

VCCIO3BAB14

VCCIO3BAD13

VCCIO3BAE15

VCCIO3BAJ13

VCCIO3BAK10

VCCIO4AAA17

VCCIO4AAD18

VCCIO4AAE25

VCCIO4AAF22

VCCIO4AAH16

VCCIO4AAH26

VCCIO4AAJ23

VCCIO4AAK20

VCCIO5AAD28VCCIO5AAG29VCCIO5AW23

VCCIO5BAA27VCCIO5BAE30

VCCIO8AA7

VCCIO8AC11VCCIO8AD8VCCIO8AE5VCCIO8AF12VCCIO8AG14VCCIO8AG9VCCIO8AH6VCCIO8AJ13

VREFB3AN0AD6

VREFB3BN0AJ15

VCCIO3BAJ8

VCCIO4AAG19

VCCIO5AAB24

VCCIO8AB4

VREFB4AN0AK17

VREFB5AN0AC24

VREFB5BN0AA29

VREFB8AN0B10

VCCIO4AAC21

Cyclone V GX SoCTransceiver & HPS Power

5CSXFC6D_F896

U21L

VCCE_GXBLAA5

VCCE_GXBLM6

VCCE_GXBLN5

VCCE_GXBLT6

VCCL_GXBLW5

VCCE_GXBLU5

VCCE_GXBLY6

VCCH_GXBLAB6VCCH_GXBLP6VCCH_GXBLV6

VCCL_GXBLL5VCCL_GXBLR5

VCCRSTCLK_HPSJ20

VCCPLL_HPSL21

VCCPD6A6B_HPSM21VCCPD6A6B_HPSN22

VCCPD6A6B_HPSR23

VCCPD6A6B_HPsP21VCCPD6A6B_HPSR20

VCCPD7A_HPSK19

VCCPD7D_HPSK16

VCCIO6A_HPSK24 VCCIO6A_HPSH26 VCCIO6A_HPSG29

VCCPD7B_HPSK18

VCCPD7C_HPSJ17

VCCIO6A_HPSK30

VCCIO6A_HPSD28

VCCIO6A_HPSN21

VCCIO6B_HPSP23

VCCIO6B_HPSP28

VCCIO6B_HPSR25

VCCIO6B_HPST22

VCCIO6A_HPSL27

VCCIO6A_HPSM24

VCC_HPST17

VCCIO7C_HPSD18

VCCIO6B_HPSV26

VCC_HPSN20

VCC_HPSM15

VCC_HPSP17

VCC_HPSU18

VCCIO7A_HPSH21VCCIO7A_HPSF22

VCC_HPSP19

VCCIO7D_HPSH16

VCCIO7B_HPSE20

VCCIO7D_HPSE15

VCC_HPSL16 VCC_HPSL20

VCCIO7B_HPSG19

VCC_HPSR16

VREFB7N0_HPSE22

VCC_HPST19

VCC_HPSU16

VCC_HPSP15

VCC_HPSL18

VCCIO6B_HPSU19

VREFB6AN0_HPSG27

VREFB6BN0_HPSU30

Cyclone V GX SoC Power

5CSXFC6D_F896

U21J

VCCM11

VCCM13

VCCM9

VCCN10

VCCN12

VCCN14

VCCP11

VCCP13

VCCR10

VCCR12

VCCR14

VCCT11

VCCT13

VCCU10

VCCPD3AAC10VCCPD3AAA10

VCCPD3B4AAC19VCCPD3B4AAC17VCCPD3B4AAC15VCCPD3B4AAC13VCCPD3B4AAB20VCCPD3B4AAB18

VCCPD3B4AAE21VCCPD3B4AAD16

VCCPD5AV24VCCPD5AV22

VCCA_FPLLAA8VCCA_FPLLV8VCCA_FPLLR7VCCA_FPLLN7

VCCA_FPLLK9

VCCA_FPLLY22

DNUE26 DNU

AD15

VCCU21 VCC

Y9 VCCY13 VCCY11 VCCW14 VCCW12 VCCW10 VCCV15 VCCV13 VCCV11 VCCU14 VCCU12 VCCPD5B

U23

VCCPD8AK11

VCCPD8AK13

VCCPD8AL10

VCCPD8AL12

VCCPD8AL14

VCCBATH9

VCCPGMJ11

VCCPGMAA23

VCCPGMAB10

VCC_AUXAB11

VCC_AUXAB16

VCC_AUXAD22

VCC_AUXH10

VCC_AUXJ16

VCC_AUX_SHAREDJ21

DNUJ15

DNUF1

DNUAA7 DNUG2

L25

3A, 30 Ohm FB

Page 39: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Power 8 - Cyclone V GX SoC Ground

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

39 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

39 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

39 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Cyclone V GX SoC GND

5CSXFC6D_F896

U21H

GNDJ6

GNDJ22

GNDD26

GNDA26

GNDA12

GNDA17

GNDA2

GNDA22

GNDA27

GNDAA11

GNDAA22

GNDAA3

GNDAA4

GNDAA6

GNDAA9

GNDAB1

GNDAB19

GNDAB2

GNDAB29

GNDAB5

GNDAB7

GNDAC16

GNDAC26

GNDAC3

GNDAC4

GNDAC6

GNDAC8

GNDAD1

GNDAD2

GNDAD23

GNDAD5

GNDAE10

GNDAE20

GNDAE3

GNDAE4

GNDAF1

GNDAF12

GNDAF17

GNDAF2

GNDAF27

GNDAF3

GNDAG14

GNDAG24

GNDAG9

GNDAH1

GNDAH11

GNDAH21

GNDAH6

GNDAJ18

GNDAJ28

GNDAJ3

GNDAJ30

GNDAK15

GNDAK25

GNDAK5

GNDB14

GNDB19

GNDB24

GNDB29

GNDB9

GNDC1

GNDC16

GNDC21

GNDC26

GNDC6

GNDD13

GNDD23

GNDD3

GNDE10

GNDE25

GNDE30

GNDF17

GNDF2

GNDF27

GNDF5

GNDF7

GNDG24

GNDG3

GNDG4

GNDH1

GNDH11

GNDH2

GNDH5

GNDJ18

GNDJ28

GNDJ3

GNDJ4

GNDJ8

GNDK1

GNDK10

GNDK15

GNDK2

GNDK20

GNDK25

Cyclone V GX SoC GND

5CSXFC6D_F896

U21I

GNDK5

GNDL11

GNDL13

GNDL15

GNDL17

GNDL19

GNDL22

GNDL3

GNDL4

GNDL6

GNDM1

GNDM10

GNDM12

GNDM14

GNDM16

GNDM18

GNDM2

GNDM20

GNDM29

GNDM5

GNDM7

GNDM8

GNDN11

GNDN13

GNDN15

GNDN17

GNDN19

GNDN26

GNDN3

GNDN4

GNDN6

GNDN8

GNDN9

GNDP1

GNDP10

GNDP12

GNDP14

GNDP16

GNDP18

GNDP2

GNDP20

GNDP5

GNDP7

GNDR11

GNDR13

GNDR15

GNDR17

GNDT20

GNDU11

GNDU13

GNDU15

GNDU17

GNDU24

GNDU29

GNDU3

GNDU4

GNDU6

GNDU9

GNDV1

GNDV10

GNDV12

GNDV14

GNDV19

GNDV2

GNDV21

GNDV5

GNDV7

GNDW11

GNDW13

GNDW18

GNDW28

GNDW3

GNDW4

GNDW6

GNDW9

GNDY1

GNDY10

GNDY12

GNDY14

GNDY15

GNDY2

GNDY20

GNDY25

GNDY30

GNDY5

GNDY7

GNDY8

GNDU22

GNDT18

GNDT7

GNDT1

GNDT12

GNDT27

GNDR8

GNDT15GNDT16

GNDR9

GNDT10

GNDT5

GNDT2

GNDT14

GNDR4

GNDR6

GNDR3

GNDR30

Page 40: Cyclone V SoC FPGA Development Kit Board · Cyclone V SoC FPGA Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Decoupling1.1V_vcc

1.1V_vccel

1.5V_vccio

1.5V_hps

2.5V_fpga

2.5V_fpga_filt

2.5V_hps

2.5V_HPS_FILT

3.3v_HPS

1.1V_VCC

1.5V_FPGA

1.1V_HPS

1.1V_VCCEL

2.5V_HPS_FILT

3.3V_HPS

2.5V_HPS

2.5V_FPGA_FILT

2.5V_FPGA

1.5V_HPS

2.5V_VCCAUX_SHARED

1.1V_VCCL

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

40 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

40 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

C

Cyclone V SoC FPGA Development Kit Board

B

40 40Wednesday, March 20, 2013

150-0321003-C1 (6XX-44184R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121

Copyright (c) 2013, Altera Corporation. All Rights Reserved.

C460

47nF

C331

0.01uF

C359

0.1uF

C382

0.47uF

C530

0.1uF

C527

0.01uF

C417

22uF4V

C432

47nF

C313

0.01uF

C480

0.47uF

C511

100uF6.3V

C538

0.1uF

C376

22nF

L26

220 Ohm FB

C523

0.1uF

C271

4.7uF

C550

330uF2.5V

C428

47nF

C415

4.7nF

C312

47nF

C427

47nF

C539

0.22uF

C302

47nF

C472

0.01uF

C416

1uF

C468

100uF6.3V

C521

0.47uF

C412

22nF

C272

1uF

C404

22nF

C473

22nF

C402

22nF

C314

330uF2.5V

C410

47nF

C400

4.7nF

C453

0.01uF

C296

0.22uF

C354

4.7nF

C329

4.7uF

C502

0.22uF

C398

47nF

SCREW3

C528

0.47uF

C375

22nF

C560

330uF2.5V

STANDOFF4

C413

22nF

C437

4.7nF

C343

4.7nF

C384

47nF

C451

0.01uF

C436

0.01uF

STANDOFF2

C378

0.01uF

SCREW6

C477

22nF

C562

330uF2.5V

C353

0.01uF

C509

4.7nF

SCREW1

C531

0.47uF

C352

0.01uF

C459

22nF

C340

22nF

C63

0.01uFC423

4.7nF

C386

47nF

C381

0.1uF C450

0.01uF

C355

47nF

C421

47nF

C299

0.1uF

C507

4.7nF

C290

1uF

C433

22nF

C349

4.7nF

C479

0.01uF

C280

330uF2.5V

C438

47nF

C536

0.1uF

C452

0.47uF

C273

1uF

C508

4.7nF

C553

4.7uF

C380

0.47uF

C303

330uF2.5V

C431

22nF

C333

4.7nF

C389

0.01uF

C498

22nF

C348

4.7nF

C440

47nF

C469

0.01uF

C533

0.1uF

C525

0.01uF

C455

22nF

C458

47nF

C330

0.01uF

C358

0.22uF

C357

47nF

C510

0.1uF

C385

0.22uF

C524

47nF

C407

22nF

SCREW4

C401

22nF

SCREW5

C430

47nF

C449

100uF6.3V

C461

4.7nF

C425

47nF

C372

0.1uF

C390

4.7uF

C278

100uF6.3V

C501

0.22uF

C301

0.01uF

SCREW2

C522

0.22uF

C411

22nF

C551

4.7uF

C408

22nF

C462

22nF

C277

100uF6.3V

C379

0.22uF

C406

47nF

C344

330uF2.5V

C377

22nF

C434

4.7nF

C295

0.47uF

C342

22nF

C347

330uF2.5V

C439

0.22uF

C275

10uF

C476

1uF

C409

22nF

C559

330uF2.5V

PCB1

C67

22nF

C274

100uF6.3V

C478

22nF

C383

47nF

C414

0.01uF

C351

4.7nF

C529

22nF

C535

0.22uF

C426

22nF

C422

22nF

C534

0.47uF

C561

330uF2.5V

C397

4.7uF

C405

22nF

C360

0.01uF

C424

47nF

C399

4.7nF

C387

0.1uF

C297

0.01uF

STANDOFF1

C298

47nF

C499

4.7nF

C554

1uF

C279

100uF6.3V

SPACER2

C429

22nF

C350

22nF

C435

0.01uF

C526

47nF

C563

330uF2.5V

C374

0.01uF

C356

0.47uF

C537

0.1uF

C373

0.1uF

C300

0.22uF

C454

4.7nF

C552

2.2uF

C456

22nF

C269

330uF2.5V

C341

4.7nF

C388

0.01uF

STANDOFF3

C471

0.01uF

C74

0.01uF

C500

0.1uF

C532

0.1uF

C276

2.2uF

C470

0.01uF

C334

4.7uF

SPACER1

C403

22nF

C457

22nF

C332

4.7nF