cyclone iv gx fpga development kit board xx parts, xx ... drawing pcb film bill of materials...
TRANSCRIPT
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E E
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
1 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
1 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
1 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
DESCRIPTIONREV DATE PAGES
PAGE DESCRIPTION
2
NOTES:
Title, Notes, Block Diagram, Revision History1
3
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12
13
14
15
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17
18
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20
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24
25
5
6
xx Parts, xx Library Parts, xx Nets, xx Pins
Cyclone IV GX FPGA Development Kit Board
1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing Schematic Drawing PCB Film Bill of Materials Schematic Design Files Functional Specification PCB Layout Guidelines Assembly Rework
C4GX FPGA Package Top
2.
100-0311003-A1110-0311003-A1120-0311003-A1130-0311003-A1140-0311003-A1150-0311003-A1160-0311003-A1170-0311003-A1180-0311003-A1210-0311003-A1220-0311003-A1320-0311003-A1
26
27
Power 1
Power 2
Power Monitor
Cyclone IV GX Power
Cyclone IV GX Clocks
MAX II
DDR2 SDRAM x32 TOP
SSRAM & FLASH
Embedded USB Blaster
10/100/1000 Ethernet
HSM Connectors
Cyclone IV GX Configuration
Decoupling
Power 3
Cyclone IV GX Banks 7 & 8
Cyclone IV GX Banks 5 & 6
Cyclone IV GX Banks 3 & 4
Cyclone IV GX Transceivers
DDR2 SDRAM x32 BOTTOM
Block Diagram
User IO & Connector
28
Clock Circuitry
5/15/2010A Initial SchematicAll
29
PCI Express Edge Connector x4
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
2 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
2 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
2 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
BANK 7(A)
( L)
1.
( K)
Notes:
BANK 6
(B)Bank 5 - HSMC PORT B
VCCIO = 1.8V
VCCIO = 2.5V/1.8V
FPGA Schematic Symbol Breakdown:
VCCIO, VREF
( I )
(F)
Bank 6 - HSMC PORT A
(H)
VCC, VCCD_PLL, VCCA, VCC_CLKIN
BANK 5
BANK 8
( J)
BANKS 4
Bank 4 - DDR2 SDRAM x32, FLASH, SSRAM, SHARED FSM BUS
VCCIO = 1.8V
(D)(C)
VCCIO = 2.5V
(E)
(G)
VCCIO = 1.8VVCCIO = 1.8V
USER DIPSWITCH, PUSH BUTTONSETHERNET, HSMC PORT B
Cyclone IV GX FPGA Package Top
(M)(N)
Bank 3 - DDR2 SDRAM x32
Some Clocks
TRANSCEIVERS - PCIE x4/HSMB and HSMA XCVRsTRANSCEIVER POWER
Configuration
GroundGround and NCs
Transceiver Channels 4-7
Bank 8 - DDR2 SDRAM x32, mDDR SDRAM x16, LCDBank 7 - DDR2 SDRAM x32, ETHERNET
PCIE
HSMC PORT A
HSMC PORT A
BANK 3
DDR2 x32
Transceiver Channels 0-3
HSMC XCVR PORT A
PCIE x4 or HSMC XCVR PORT B
DDR2 x32FLASHSSRAMSHARED FSM BUS
GRAPHIC DISPLAYHSMC PORT B
DDR2 x32DDR2 x32
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
PCIE_WAKEn_R3.3V_PCIE_AUX
PCIE_PRSNT2n_x4PCIE_PRSNT2n_x1
PCIE_PRSNT2n_x4
PCIE_PRSNT2n_x1 PCIE_TX_N0PCIE_TX_P0
PCIE_TX_N1PCIE_TX_P1
PCIE_TX_N2PCIE_TX_P2
PCIE_TX_N3PCIE_TX_P3
PCIE_RX_P0PCIE_RX_N0
PCIE_RX_P1PCIE_RX_N1
PCIE_RX_P2PCIE_RX_N2
PCIE_RX_P3PCIE_RX_N3
PCIE_T_PERSTn
PCIE_PRSNT1n
PCIE_T_SMBCLKPCIE_T_SMBDAT
USB_DISABLEn
PCIE_T_PERSTnPCIE_T_SMBCLKPCIE_T_SMBDAT
12V_PCIE 3.3V_PCIE12V_PCIE
12V_PCIE 3.3V_PCIE
3.3V_PCIE
2.5V
3.3V_PCIE 1.8V
3.3V_PCIE
PCIE_REFCLK_P9PCIE_REFCLK_N9
PCIE_JTAG_TCK8PCIE_JTAG_TDI8PCIE_JTAG_TDO8PCIE_JTAG_TMS8
PCIE_RX_N[3:0]4
PCIE_TX_N[3:0]4
PCIE_TX_P[3:0]4
PCIE_RX_P[3:0]4
USB_DISABLEn8,18
PCIE_SMBCLK7PCIE_SMBDAT7
PCIE_PERSTn7
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
3 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
3 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
3 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
PCI Express Edge Connector
Link Width DIP SwitchR98 DNIR98 DNI
C1090.1uFC1090.1uF
C3880.1uFC3880.1uF
C1080.1uFC1080.1uF
KEY
X4
X1
J14
PCIE_Slot
KEY
X4
X1
J14
PCIE_Slot
+12VB1
+12VB2
+12VB3
GNDB4
SMCLKB5
SMDATB6
GNDB7
+3_3VB8
JTAG_TRSTNB9
+3_3VAUXB10
WAKE_NB11
RSVD1B12
GNDB13
PET0PB14
PET0NB15
GNDB16
PRSNT2_N_X1B17
GNDB18
PET1PB19
PET1NB20
GNDB21
GNDB22
PET2PB23
PET2NB24
GNDB25
GNDB26
PET3PB27
PET3NB28
GNDB29
RSVD3B30
PRSNT2_N_X4B31
GNDB32
PRSNT1_N A1
+12V A2
+12V A3
GND A4
JTAG_TCK A5
JTAG_TDI A6
JTAG_TDO A7
JTAG_TMS A8
+3_3V A9
+3_3V A10
PERST_N A11
GND A12
REFCLK+ A13
REFCLK- A14
GND A15
PER0P A16
PER0N A17
GND A18
RSVD2 A19
GND A20
PER1P A21
PER1N A22
GND A23
GND A24
PER2P A25
PER2N A26
GND A27
GND A28
PER3P A29
PER3N A30
GND A31
RSVD4 A32
C3890.1uFC3890.1uF
OPEN
SW4
TDA04H0SB1
OPEN
SW4
TDA04H0SB1
1234 5
678
C1070.1uFC1070.1uF
R232 1.00KR232 1.00K
B1
PCI BRACKET
B1
PCI BRACKET
R99 DNIR99 DNI
U26
MAX3378
U26
MAX3378
VL 1
IO VL1 2
IO VL2 3
IO VL3 4
IO VL4 5
NC1 6
GND 7
VCC14
IO VCC113
IO VCC212
IO VCC311
IO VCC410
NC29
/TS8
C3870.1uFC3870.1uF
C3900.1uFC3900.1uF
R241
1.00k
R241
1.00k
C1100.1uFC1100.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
PCIE_TX_P0HSMB_RX_P0
RREF0
HSMB_TX_P0
XCVR_TX_P0
XCVR_TX_N2XCVR_TX_P2
XCVR_TX_N3XCVR_TX_P3
XCVR_TX_N0
XCVR_TX_N1XCVR_TX_P1
XCVR_TX_P0
HSMB_TX_N0
PCIE_TX_N0
HSMB_TX_P1
PCIE_TX_P1
HSMB_TX_N1
PCIE_TX_N1
HSMB_TX_P2
PCIE_TX_P2
HSMB_TX_P3
PCIE_TX_P3
HSMB_TX_N3
PCIE_TX_N3
HSMB_TX_N2
PCIE_TX_N2
HSMA_RX_N2HSMA_RX_P2
HSMA_RX_N3HSMA_RX_P3
HSMA_RX_N0HSMA_RX_P0
HSMA_RX_N1HSMA_RX_P1
XCVR_RX_P0
XCVR_RX_N2XCVR_RX_P2
XCVR_RX_N3XCVR_RX_P3
XCVR_RX_N0
XCVR_RX_N1XCVR_RX_P1
HSMA_TX_N2HSMA_TX_P2
HSMA_TX_N3HSMA_TX_P3
HSMA_TX_N0
HSMA_TX_N1HSMA_TX_P1
HSMA_TX_P0
XCVR_RX_P0 PCIE_RX_P0
XCVR_RX_N0 PCIE_RX_N0HSMB_RX_N0
XCVR_RX_P1 PCIE_RX_P1HSMB_RX_P1
XCVR_RX_N1 PCIE_RX_N1HSMB_RX_N1
XCVR_RX_P2 PCIE_RX_P2HSMB_RX_P2
XCVR_RX_P3 PCIE_RX_P3HSMB_RX_P3
XCVR_RX_N3 PCIE_RX_N3HSMB_RX_N3
XCVR_RX_N2 PCIE_RX_N2HSMB_RX_N2
XCVR_TX_N2
XCVR_TX_P3
XCVR_TX_P2
XCVR_TX_N0
XCVR_TX_P1
XCVR_TX_N1
XCVR_TX_N3
2.5V_VCCA_VCCH_GXB1.2V_VCCL_GXB
HSMB_RX_N[3:0]16
HSMB_TX_N[3:0]16
HSMB_TX_P[3:0]16
HSMB_RX_P[3:0]16
HSMA_RX_N[3:0]16
HSMA_TX_N[3:0]16
HSMA_TX_P[3:0]16
HSMA_RX_P[3:0]16
PCIE_TX_N[3:0]3
PCIE_RX_N[3:0]3
PCIE_RX_P[3:0]3
PCIE_TX_P[3:0]3
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
4 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
4 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
4 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Cyclone IV GX Transceivers
(2.5V)
(1.2V)
R95 DNIR95 DNI
QL0
QL1
Cyclone IV GXTransceivers
EP4CGX150DF896_DDR2_Swap_hsmc
U10G
Version = 0.1 Preliminary
QL0
QL1
Cyclone IV GXTransceivers
EP4CGX150DF896_DDR2_Swap_hsmc
U10G
Version = 0.1 Preliminary
GXB_TX6p K4
GXB_TX6n K3
GXB_TX7n H3GXB_TX7p H4
GXB_RX2nW1GXB_RX2pW2
GXB_TX2n V3GXB_TX2p V4
GXB_TX3n T3GXB_TX3p T4GXB_RX3pU2
GXB_RX3nU1
GXB_TX0p AB4
GXB_TX0n AB3
GXB_TX1n Y3GXB_TX1p Y4
GXB_RX6nL1GXB_RX6pL2
GXB_RX0nAC1GXB_RX0pAC2
GXB_RX1nAA1GXB_RX1pAA2
GXB_RX4nR1
GXB_RX5pN2
GXB_RX4pR2
GXB_RX5nN1
GXB_RX7nJ1GXB_RX7pJ2
GXB_TX4p P4
GXB_TX4n P3
GXB_TX5n M3GXB_TX5p M4
Cyclone IV GXTransceiver Pwr
EP4CGX150DF896_DDR2_Swap_hsmc
U10H
Version = 0.1 Preliminary
Cyclone IV GXTransceiver Pwr
EP4CGX150DF896_DDR2_Swap_hsmc
U10H
Version = 0.1 Preliminary
VCCL_GXBP6
VCCL_GXBT6
VCCL_GXBAD4
VCCA_GXB AD3VCCL_GXBAA6VCCL_GXBK5
VCCL_GXBN7
VCCL_GXBM5
VCCL_GXBY5VCCL_GXBV5
VCCA_GXB M7
VCCA_GXB R6
VCCA_GXB V7
VCCA_GXB Y6
VCCH_GXB N5
VCCH_GXB L6
VCCH_GXB W7VCCH_GXB U6
RREF0AE1
R100 0R100 0
R97 DNIR97 DNI
R89 DNIR89 DNI
R92 0R92 0 C3260.1uF C3260.1uF
R90 0R90 0
R87 DNIR87 DNI
C3430.1uF C3430.1uF
R85 0R85 0
C3280.1uF C3280.1uF
R86 DNIR86 DNI
C325DNI C325DNI
C340DNI C340DNI
C342DNI C342DNI
C3410.1uF C3410.1uF
C327DNI C327DNI
C323DNI C323DNI
R2212.00K R2212.00K
R93 0R93 0
C3450.1uF C3450.1uF
C3300.1uF C3300.1uF
C3470.1uF C3470.1uF
R101 DNIR101 DNI
C344DNI C344DNI
C329DNI C329DNI
C346DNI C346DNI
R96 0R96 0
R88 0R88 0
R94 DNIR94 DNI
R91 DNIR91 DNI
C3240.1uF C3240.1uFR84 0R84 0
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
RDN2RUP2
HSMB_RX_LED
MAX_OEn
USER_DIPSW[7:0]
USER_DIPSW[7:0]
FLASH_CLK
FSM_D[15:0]
FSM_A[25:1]
USER_LED[7:0]
FLASH_OEn
HSMB_CLK_OUT_P2
HSMB_TX_D_N16
HSMB_RX_D_P9
HSMB_RX_D_N8HSMB_RX_D_P7
HSMB_RX_D_P8
HSMB_RX_D_N9
HSMBT_CLK_IN_P2
HSMB_CLK_IN_P2 HSMBT_CLK_IN_P2
HSMB_RX_D_P6HSMB_RX_D_N12
HSMB_RX_D_P12
HSMB_RX_D_P10
HSMB_RX_D_N6
HSMB_RX_D_N10
HSMB_RX_D_N11
HSMB_RX_D_P11
HSMB_RX_D_N14
HSMB_RX_D_N16
HSMB_RX_D_N7
HSMB_RX_D_P7
HSMB_RX_D_N8
HSMB_RX_D_P8HSMB_RX_D_P9HSMB_RX_D_N9
HSMB_RX_D_P14
HSMB_RX_D_N13HSMB_TX_D_N15FSM_A18
DDR2B_DQ1
DDR2B_DQ2
DDR2B_DQ3
DDR2B_DQ4
DDR2B_DQ5
DDR2B_DQ6
DDR2B_DQ7
DDR2B_A1
DDR2B_DQS0
DDR2B_A2
DDR2B_A5
DDR2B_A11
DDR2B_A12
DDR2B_A7
DDR2B_A9
DDR2B_A8HSMB_RX_D_P15
HSMB_RX_D_N15
DDR2B_CLK_PDDR2B_CLK_N
DDR2B_DM0
FSM_A7
FSM_A17FSM_A5
HSMB_TX_D_P13
DDR2B_DQ0
FSM_A14
DDR2B_A0
DDR2B_BA0
DDR2B_BA1
DDR2B_A3
DDR2B_A4
DDR2B_A6
DDR2B_A10
FSM_D0
DDR2B_DM1
DDR2B_DQ8
DDR2B_RASnDDR2B_WEn
DDR2B_CSn
DDR2B_ODT
DDR2B_DQS1
DDR2B_DQS2
DDR2B_DQ17DDR2B_DQ18
DDR2B_DQ19
DDR2B_DQ20
DDR2B_DQ21
DDR2B_DQ22DDR2B_DQ23
DDR2B_DQ9
DDR2B_DQ10
DDR2B_DQ11DDR2B_DQ12
DDR2B_DQ13
DDR2B_DQ14
DDR2B_DQ15
DDR2B_CKE
DDR2B_DQ16
FSM_A19
FSM_D15
DDR2B_DM2
DDR2B_CASn
HSMB_RX_D_N7HSMB_RX_D_P12
HSMB_RX_D_P9
HSMB_TX_D_N7
DDR2B_DQ26
HSMB_CLK_OUT_P2
FSM_A9
FSM_D7
FSM_A6
FSM_A23
RDN2RUP2
FSM_D12
FSM_A4
FSM_D14
FSM_A11
FSM_A3
FSM_A13
FSM_D4
FSM_A25
HSMB_CLK_IN_P2
FLASH_CLK
FSM_A8
FSM_A15
FSM_A10
FSM_D8
FSM_A24
FSM_A16
FSM_A22
FSM_D10
FSM_D5
FSM_D13
HSMB_RX_D_N6
FSM_A2
FSM_D11FSM_A21
FSM_D6
FSM_D9
DDR2B_DM3
DDR2B_DQ25DDR2B_DQ27
DDR2B_DQ28
DDR2B_DQ29
DDR2B_DQ30
DDR2B_DQ31
DDR2B_DQS3
DDR2B_DQ24
HSMB_TX_D_N6
HSMB_RX_D_P10
HSMB_RX_D_N14
HSMB_RX_D_P13
HSMB_TX_D_P8
HSMB_TX_D_N14
HSMB_RX_D_P7
HSMB_RX_D_P6
HSMB_RX_D_N12
HSMB_RX_D_N10
HSMB_RX_D_N9
HSMB_TX_D_P10
HSMB_RX_D_N11
HSMB_TX_D_P7
HSMB_TX_D_P15
HSMB_TX_D_N8
HSMB_RX_D_N16
HSMB_TX_D_N16
HSMB_TX_D_P12
HSMB_RX_D_P8
HSMB_TX_D_P9
HSMB_RX_D_P11
HSMB_TX_D_N10HSMB_TX_D_N13
HSMB_TX_D_P11
HSMB_TX_D_P6
HSMB_RX_D_N8
HSMB_TX_D_P14
HSMB_TX_D_P15
HSMB_TX_D_P16
HSMB_TX_D_P9
HSMB_TX_D_N8
HSMB_TX_D_N13HSMB_TX_D_N10
HSMB_TX_D_N14
HSMB_TX_D_P14
HSMB_TX_D_N16HSMB_TX_D_P12
HSMB_TX_D_P8HSMB_TX_D_N7
HSMB_TX_D_P10
HSMB_TX_D_N6HSMB_TX_D_P7
HSMB_TX_D_P6
HSMB_T_TX_D_P16
1.8V_B3_B4
1.8V 2.5V2.5V1.8V
1.8V 2.5V
2.5V 2.5V1.8V 1.8V
2.5V1.8V
2.5V 2.5V
1.8V 1.8V
2.5V1.8V1.8V 2.5V
HSMB_RX_LED 7,17
MAX_OEn 9,14
DDR2B_RASn12
DDR2B_DQS[3:0]12
DDR2B_DQ[31:0]12
DDR2B_ODT12DDR2B_ODT12DDR2B_CLK_P12DDR2B_CLK_N12
DDR2B_A[12:0]12
DDR2B_BA[1:0]12
DDR2B_CASn12DDR2B_WEn12DDR2B_CSn12
DDR2B_DM[3:0]12
DDR2B_CKE12
USER_DIPSW[7:0] 7,17,20
PCIE_PERSTn3,7
PCIE_SMBCLK3,7PCIE_SMBDAT3,7
USER_DIPSW[7:0] 7,17,20
FSM_D[15:0] 9,13,14,20
USER_LED[7:0] 7,8,9,14,17
FLASH_CLK 13,14
FLASH_OEn 9,13,14
FSM_A[25:1] 8,9,13,14,20
HSMB_RX_D_P7HSMB_RX_D_N8HSMB_RX_D_P8HSMB_RX_D_P9HSMB_RX_D_N9
HSMB_CLK_OUT_P2 9
HSMB_TX_D_N16
HSMB_TX_D_N157
HSMBT_CLK_IN_P2 16
HSMB_T_RX_D_P616
HSMB_T_RX_D_P137,16
HSMB_T_RX_D_P147,16
HSMB_T_RX_D_P157,16
HSMB_T_RX_D_N1416
HSMB_T_RX_D_P167,16
HSMB_T_RX_D_N1616
HSMB_T_RX_D_N157,16
HSMB_T_RX_D_N137,16
HSMB_T_RX_D_N616
HSMB_T_RX_D_N1016
HSMB_T_RX_D_P1016
HSMB_T_RX_D_N1116
HSMB_T_RX_D_N1216
HSMB_T_RX_D_P1216
HSMB_T_RX_D_P1116
HSMB_T_RX_D_N716
HSMB_T_RX_D_P716
HSMB_T_RX_D_N816
HSMB_T_RX_D_P816HSMB_T_RX_D_P916HSMB_T_RX_D_N916
HSMB_T_TX_D_P117,16
HSMB_T_TX_D_P137,16HSMB_T_TX_D_N127,16
HSMB_T_TX_D_N117,16
HSMB_TX_D_P169
HSMB_TX_D_N127,9HSMB_TX_D_P117HSMB_TX_D_N117,9HSMB_RX_D_N137HSMB_RX_D_P137HSMB_TX_D_P137HSMB_RX_D_N157HSMB_RX_D_P157HSMB_RX_D_P147HSMB_RX_D_P167,9
HSMB_T_TX_D_N1316HSMB_T_TX_D_N1016
HSMB_T_TX_D_N816HSMB_T_TX_D_P1416
HSMB_T_TX_D_P916HSMB_T_TX_D_N1416HSMB_T_TX_D_P1516
HSMB_T_TX_D_P16 16
HSMB_T_TX_D_P1216HSMB_T_TX_D_N1616
HSMB_T_TX_D_P816
HSMB_T_TX_D_N616HSMB_T_TX_D_P716
HSMB_T_TX_D_P1016
HSMB_T_TX_D_P616
HSMB_T_TX_D_N716
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
5 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
5 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
5 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Cyclone IV GX Banks 3 & 4
HSMC PORT B
MAX II INTERFACE
HSMA INTERFACE
SHARED BUS INTERFACE
FLASH INTERFACE
USER INTERFACE
70 pins of translation
Inputoutput
Cyclone IV GX Bank 4
EP4CGX150DF896_DDR2_Swap_hsmc
U10B
Version = 0.1 Preliminary
Cyclone IV GX Bank 4
EP4CGX150DF896_DDR2_Swap_hsmc
U10B
Version = 0.1 Preliminary
DIFFIO_B38nAG16DIFFIO_B38pAF16
DQ2B/DIFFIO_B61p AG23
DIFFIO_B60n AK25
DIFFIO_B61n AH23
DQ2B/DIFFIO_B62p AK26
DQ2B/DIFFIO_B63p AH25
DIFFIO_B66p AJ28
DIFFIO_B68n AH26
DQ4B/DIFFIO_B39n AK15DQ4B/DIFFIO_B39p AJ15
DM2B/DIFFIO_B46n AE19
DM4B/DIFFIO_B37p Y17
DQ4B/DIFFIO_B42n AK18DQ4B/DIFFIO_B42p AK17
DIFFIO_B57nAF22DIFFIO_B57pAF21
DIFFIO_B58n AE22
DIFFIO_B59n AK24
DIFFIO_B62n AK27
DIFFIO_B63n AJ25
DIFFIO_B64nAK28
DIFFIO_B65n AH24DIFFIO_B65p AG24
DIFFIO_B66n AK29
DIFFIO_B68p AG26
DIFFIO_B70pAG27
DIFFIO_B71n AE23DIFFIO_B71p AD23
DIFFIO_B72nAH28
DM0B/DIFFIO_B64pAJ27
DQ0BAG25
DQ0B/DIFFIO_B67nY21DQ0B/DIFFIO_B67pY20
DQ0B/DIFFIO_B69pAA21
DQ0B/DIFFIO_B70nAH27
DQ0B/DIFFIO_B72pAG28
DIFFIO_B40nAE16DIFFIO_B40pAD16
DQ4B/DIFFIO_B43n AJ18
DQ0B/RDN2AE24
DQ4B/DIFFIO_B43p AH18
DQ0B/RUP2AD24
DIFFIO_B47p AG18
DIFFIO_B48nAG19
DQ4B/DIFFIO_B46p AE18
DQ2B/DIFFIO_B54n AA20
DQ4B/DIFFIO_B47n AH19
DQ2B/DIFFIO_B55n AE21
DIFFIO_B51pAJ22
DIFFIO_B52nAH20
DQ4B/DIFFIO_B54p Y19
DQ2B/DIFFIO_B59p AK23
DQ2B/DIFFIO_B60p AJ24
DIFFIO_B41nAF18DIFFIO_B41pAE17
DIFFIO_B44nAH17DIFFIO_B44pAG17
DIFFIO_B45nAK19DIFFIO_B45pAJ19
DIFFIO_B48pAF19
DIFFIO_B49nAA18DIFFIO_B49pY18
DIFFIO_B50nAK21DIFFIO_B50pAK20
DIFFIO_B51nAK22
DIFFIO_B52pAG20
DIFFIO_B53nAJ21DIFFIO_B53pAH21
DIFFIO_B55p AE20
DIFFIO_B56nAH22DIFFIO_B56pAG22
DQS4B/CQ5B/DPCLK3/DIFFIO_B37n AA17
DQS2B/CQ3B/DPCLK4/DIFFIO_B58p AD22
DQS0B/CQ1B/DPCLK5/DIFFIO_B69nAB22
C136
0.1uF
C136
0.1uF
C120
0.1uF
C120
0.1uF
U38
FXLA108
U38
FXLA108
A02
A13
A24
A35
A46
A57
A79A68
B2 17
B7 12
B5 14B4 15
B1 18B0 19
VCCB 20
B3 16
B6 13
OEn 11GND10
VCCA1
DA
P21
U33
SN74AVC1T45
U33
SN74AVC1T45
GND2
VCCA1
A3 B 4
DIR 5
VCCB 6
U36
FXLA108
U36
FXLA108
A02
A13
A24
A35
A46
A57
A79A68
B2 17
B7 12
B5 14B4 15
B1 18B0 19
VCCB 20
B3 16
B6 13
OEn 11GND10
VCCA1
DA
P21
C121
0.1uF
C121
0.1uF
U37
FXLA108
U37
FXLA108
A02
A13
A24
A35
A46
A57
A79A68
B2 17
B7 12
B5 14B4 15
B1 18B0 19
VCCB 20
B3 16
B6 13
OEn 11GND10
VCCA1
DA
P21
R165 49.9R165 49.9R166 49.9R166 49.9
C133
0.1uF
C133
0.1uF
C138
0.1uF
C138
0.1uFC135
0.1uF
C135
0.1uF
C127
0.1uF
C127
0.1uF
C134
0.1uF
C134
0.1uF
C122
0.1uF
C122
0.1uF
Cyclone IV GX Bank 3
EP4CGX150DF896_DDR2_Swap_hsmc
U10A
Version = 0.1 Preliminary
Cyclone IV GX Bank 3
EP4CGX150DF896_DDR2_Swap_hsmc
U10A
Version = 0.1 Preliminary
DM5B/BWSn5B/DIFFIO_B23n AB13
DQ1B/DIFFIO_B10pAG5
DQS5B/CQ5Bn/DPCLK2/DIFFIO_B32p AF15
DQ5B/DIFFIO_B25n AB16DIFFIO_B10nAH5
DIFFIO_B11pAK3
DQ5B/DIFFIO_B33p AK11
DQ3B/DIFFIO_B17p AG10
DQ5B/DIFFIO_B35n AH16
DQ3B/DIFFIO_B18n AJ10
DIFFIO_B30n AB14
DIFFIO_B31n AE15
DQ5B/DIFFIO_B35p AH15
DQ3B/DIFFIO_B18p AH11
DQ5B/DIFFIO_B36n AK14
DQ3B/DIFFIO_B19n AH12
DIFFIO_B4nAG4DIFFIO_B4pAF4
DQS1B/CQ1Bn/DPCLK0/DIFFIO_B7pAD9
DQ3B/DIFFIO_B21p AG13
DQS3B/CQ3Bn/DPCLK1/DIFFIO_B21n AH13
DQ3B/DIFFIO_B22n AH8
DQ1B/DIFFIO_B11nAK4
DQ1B/DIFFIO_B12pAH6
DQ1B/DIFFIO_B13pAK5
DQ1B/DIFFIO_B5nAF3
DQ1B/DIFFIO_B8nAJ3DQ1B/DIFFIO_B8pAH2
DIFFIO_B27n AK7
DIFFIO_B28p AJ9
DIFFIO_B29nAK10DIFFIO_B29pAK9
DIFFIO_B32n AG15
DIFFIO_B33n AK12
DIFFIO_B34nAK13DIFFIO_B34pAJ12
DIFFIO_B36p AJ13
DIFFIO_B3nAF10
DIFFIO_B6nAH3DIFFIO_B6pAG3
DIFFIO_B7nAD10
DIFFIO_B9pAH4
DM1B/DIFFIO_B5pAE3
DM3B/BWSn3B/DIFFIO_B12n AJ6
DQ5B/DIFFIO_B27p AJ7
DQ1B/DIFFIO_B9nAJ4
DQ5B/DIFFIO_B28n AK8
DQ3B/DIFFIO_B14p AE12
DIFFIO_B17n AH10
DIFFIO_B19p AG12
DQ5B/DIFFIO_B30p AA15
DQ3B/DIFFIO_B15p AG9
DQ5B/DIFFIO_B31p AE14
DQ3B/DIFFIO_B16p AE13
DIFFIO_B25p AA16
DIFFIO_B26nAH14
DIFFIO_B13nAK6
DIFFIO_B14n AF12
DIFFIO_B15n AH9
DIFFIO_B16n AF13
DIFFIO_B20nAB11DIFFIO_B20pAA12
DIFFIO_B22p AG8
DIFFIO_B23p AA13
DIFFIO_B24nAH7DIFFIO_B24pAG7
DIFFIO_B26pAG14
U35
FXLA108
U35
FXLA108
A02
A13
A24
A35
A46
A57
A79A68
B2 17
B7 12
B5 14B4 15
B1 18B0 19
VCCB 20
B3 16
B6 13
OEn 11GND10
VCCA1
DA
P21
C137
0.1uF
C137
0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
HSMA_TX_D_N[16:0]
HSMA_RX_D_P[16:0]
HSMA_TX_D_P[16:0]
HSMA_RX_D_N[16:0]
HSMA_CLK_IN_N[2:1]
HSMA_CLK_IN_P[2:1]
HSMB_CLK_OUT_P[2:1]
HSMB_CLK_OUT_N[2:1]
HSMA_CLK_OUT_P[2:1]
HSMA_CLK_OUT_N[2:1]
HSMB_CLK_IN_N[2:1]
HSMA_CLK_OUT0
HSMB_CLK_OUT0
HSMB_D[3:0]
HSMB_TX_LED
HSMB_CLK_IN_N1HSMB_CLK_IN_P1
HSMA_TX_D_N2HSMA_TX_D_P2
HSMA_D[3:0]
HSMB_CLK_IN_P1
HSMA_RX_D_P15
HSMA_RX_D_N16
HSMB_RX_D_P0
HSMA_RX_D_P14
HSMA_RX_D_N14
HSMA_RX_D_N13
HSMB_RX_D_N1
HSMB_CLK_IN_N1
HSMB_CLK_IN_N2
HSMB_RX_D_P1
HSMA_RX_D_P13
HSMB_RX_D_N3
HSMB_CLK_IN_P1
HSMA_RX_D_P16
HSMA_RX_D_N15
HSMB_CLK_OUT_N1
HSMB_TX_D_N2
HSMB_D1
HSMB_RX_D_P5HSMB_RX_D_P2
HSMB_RX_D_N2
HSMA_D2HSMB_CLK_OUT_N2
HSMB_TX_D_P0
HSMB_D2
HSMB_RX_D_N5
HSMB_RX_D_N4
HSMB_RX_D_P3
HSMB_TX_D_P2
HSMB_TX_D_P1
HSMB_TX_D_P3
HSMB_RX_D_P4
HSMB_D0
HSMA_CLK_OUT0HSMB_TX_D_N4
HSMB_CLK_OUT_P1
HSMA_D1
HSMA_D3
HSMB_TX_D_N5
HSMB_TX_D_N9
HSMB_RX_D_N0
HSMA_D0
HSMB_TX_D_N0
HSMB_D3
HSMA_TX_D_N2HSMA_TX_D_P2
HSMA_TX_D_P6
HSMA_CLK_OUT_P2HSMA_CLK_OUT_N2
HSMA_RX_D_P5
HSMA_RX_D_N5
HSMA_TX_D_P14
HSMA_TX_D_N16HSMA_TX_D_P16
HSMA_TX_D_N10HSMA_TX_D_P10
HSMA_TX_D_P11
HSMA_TX_D_N11
HSMA_RX_D_P6
HSMA_RX_D_N6
HSMA_TX_D_N6
HSMA_TX_D_N0
HSMA_TX_D_P0
HSMA_RX_D_N8HSMA_RX_D_P8
HSMA_TX_D_N8HSMA_TX_D_P8
HSMA_RX_D_P0
HSMA_RX_D_N0
HSMA_RX_D_P11
HSMA_RX_D_N11
HSMA_TX_D_N14
HSMA_TX_D_P12
HSMA_TX_D_N12
HSMA_TX_D_P13HSMA_TX_D_N13
HSMA_TX_D_N1HSMA_TX_D_P1
HSMA_RX_D_N4
HSMA_RX_D_P4
HSMA_RX_D_P3
HSMA_TX_D_P3
HSMA_RX_D_N2
HSMA_TX_D_N5
HSMA_CLK_OUT_P1
HSMA_RX_D_N1
HSMA_RX_D_P9
HSMA_RX_D_P1
HSMA_RX_D_P10
HSMA_TX_D_P7HSMA_TX_D_N7
HSMA_RX_D_N7HSMA_RX_D_P7
HSMA_RX_D_N9
HSMA_TX_D_P5
HSMA_RX_D_N10
HSMA_RX_D_P12
HSMA_CLK_OUT_N1
HSMA_RX_D_P2
HSMA_TX_D_N4HSMA_TX_D_P4
HSMA_RX_D_N12
HSMA_TX_D_N9HSMA_TX_D_P9
HSMA_TX_D_P15
HSMA_TX_D_N15
HSMA_RX_D_N3
HSMA_TX_D_N3
HSMB_TX_D_P5
HSMB_CLK_OUT0
HSMA_RX_D_P0 HSMA_RX_D_N0HSMA_RX_D_P1 HSMA_RX_D_N1
HSMA_RX_D_N2HSMA_RX_D_P2HSMA_RX_D_N3HSMA_RX_D_P3HSMA_RX_D_N4HSMA_RX_D_P4HSMA_RX_D_N5HSMA_RX_D_P5HSMA_RX_D_N6HSMA_RX_D_P6HSMA_RX_D_N7HSMA_RX_D_P7HSMA_RX_D_N8HSMA_RX_D_P8HSMA_RX_D_N9HSMA_RX_D_P9HSMA_RX_D_N10HSMA_RX_D_P10HSMA_RX_D_N11HSMA_RX_D_P11HSMA_RX_D_N12HSMA_RX_D_P12HSMA_RX_D_N13HSMA_RX_D_P13HSMA_RX_D_N14HSMA_RX_D_P14HSMA_RX_D_N15HSMA_RX_D_P15HSMA_RX_D_N16HSMA_RX_D_P16
HSMA_RX_D_P[16:0] 16
HSMA_TX_D_N[16:0] 16
HSMA_TX_D_P[16:0] 16
HSMA_RX_D_N[16:0] 16
HSMB_CLK_OUT_P[2:1] 5,9,16
HSMB_CLK_OUT_N[2:1] 16
HSMA_CLK_OUT_P[2:1] 16
HSMA_CLK_OUT_N[2:1] 16
HSMB_CLK_IN_N[2:1] 16
HSMA_CLK_IN_P[2:1] 9,16
HSMA_CLK_IN_N[2:1] 9,16
HSMA_CLK_OUT0 16
HSMB_CLK_OUT0 16
HSMB_D[3:0] 16
HSMB_TX_LED 7,17
HSMB_TX_D_P165,9HSMB_TX_D_N165
HSMA_TX_D_P2 16HSMA_TX_D_N2 16
HSMA_D[3:0] 16
HSMB_TX_D_P[5:0]8,16
HSMB_TX_D_N[5:0]16,20
HSMB_RX_D_P[5:0]16
HSMB_RX_D_N[5:0]16
HSMB_TX_D_N916
HSMB_CLK_IN_P1 16
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
6 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
6 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
6 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
HSMC PORT B
HSMC PORT A
MAX INTERFACE
Cyclone IV GX Banks 5 & 6
R194DNI R194DNI
R178DNI R178DNI
R176DNI R176DNI
R186DNI R186DNI
R188DNI R188DNIR179DNI R179DNI
R187DNI R187DNI
R167100, 1% R167100, 1%
Cyclone IV GX Bank 6
EP4CGX150DF896_DDR2_Swap_hsmc
U10D
Version = 0.1 Preliminary
Cyclone IV GX Bank 6
EP4CGX150DF896_DDR2_Swap_hsmc
U10D
Version = 0.1 Preliminary
DM0R/DIFFIO_R32nR29
DM2R/DIFFIO_R16pP21
DQ0R/DIFFIO_R30nR28DQ0R/DIFFIO_R30pR27
DQ2R/DIFFIO_R15pL27
DQ2R/DIFFIO_R19pH30
DQ0R/DIFFIO_R21nM28
DM4R/DIFFIO_R7n C30
DQ0R/DIFFIO_R24pN25
DQ0R/DIFFIO_R25pN27
DQ0R/DIFFIO_R26pR24
DQ0R/DIFFIO_R23pM29
DQ2R/DIFFIO_R10pK25
DQ0R/DIFFIO_R32pT28
DQ2R/DIFFIO_R13pF30
DQ2R/DIFFIO_R13nE30
DQ2R/DIFFIO_R11pK26
DQ2R/DIFFIO_R11nK27
DQ4R/DIFFIO_R1n F27
DQ2R/DIFFIO_R9pD29
DQ4R/DIFFIO_R5n H27
DQ4R/DIFFIO_R3n E28DQ4R/DIFFIO_R3p E27
DQ4R/DIFFIO_R1p F26
DIFFIO_R8p J28
DIFFIO_R9nD30
DIFFIO_R23nM30
DIFFIO_R24nM26
DQS0R/CQ1R/DPCLK9/DIFFIO_R29nP30
DQS2R/CQ3R/DPCLK10/DIFFIO_R10nJ26
DIFFIO_R29pR30
DIFFIO_R2n G27
DQS4R/CQ5R/DPCLK11/DIFFIO_R2p G26
DIFFIO_R25nN28
DIFFIO_R26nP25
DIFFIO_R28p P27
DIFFIO_R28n P28
DIFFIO_R27p N29
DIFFIO_R27n N30
DIFFIO_R31p R25
DIFFIO_R31n R26
DIFFIO_R6p J25
DIFFIO_R4p F28
DIFFIO_R8n H28
DIFFIO_R4n F29
DIFFIO_R12n G29DIFFIO_R12p G28
DIFFIO_R14n M22DIFFIO_R14p M21
DQ4R/DIFFIO_R5p J27
DIFFIO_R18n J30DIFFIO_R18p J29
DQ4R/DIFFIO_R6n H25
DQ4R/DIFFIO_R7p C29
DIFFIO_R17p K28
DIFFIO_R17n K29
DIFFIO_R16nN21
DIFFIO_R15nL28
DIFFIO_R20n K30
DIFFIO_R19nG30
DIFFIO_R22p N24
DIFFIO_R20p L30
DIFFIO_R22n M25
DIFFIO_R21pM27
R185DNI R185DNI
R189DNI R189DNI
R193DNI R193DNI
R181DNI R181DNI
R175DNI R175DNI
R180DNI R180DNI
Cyclone IV GX Bank 5
EP4CGX150DF896_DDR2_Swap_hsmc
U10C
Version = 0.1 Preliminary
Cyclone IV GX Bank 5
EP4CGX150DF896_DDR2_Swap_hsmc
U10C
Version = 0.1 Preliminary
DQ1R/DIFFIO_R36nV28DQ1R/DIFFIO_R36pV27
DQ3R/DIFFIO_R48n AB28
DQ3R/DIFFIO_R49n AC28
DQ5R/DIFFIO_R54n AF30
DQ5R/DIFFIO_R56n Y27
DM3R/BWSn3R/DIFFIO_R54p AG30
DQ1R/DIFFIO_R34pT23
DM5R/BWSn5R/DIFFIO_R61n AB26
DQ1R/DIFFIO_R34nT24
DQ1R/DIFFIO_R39pW25
DQ1R/DIFFIO_R40pU25
DQ3R/DIFFIO_R47n AD30
DQ1R/DIFFIO_R43nY30
DQ3R/DIFFIO_R46n AB30
DQ1R/DIFFIO_R42nT21 DQ3R/DIFFIO_R51p AD27DQ3R/DIFFIO_R50n Y22
DQ3R/DIFFIO_R53p AE27DQ3R/DIFFIO_R52p AE29
DQ3R/DIFFIO_R53n AE28
DQ5R Y25
DQ5R/DIFFIO_R56p AA27
DQ5R/DIFFIO_R57n AG29
DQ5R/DIFFIO_R59n AE26
DQ5R/DIFFIO_R57p AH29
DQS5R/CQ5Rn/DPCLK6/DIFFIO_R61p AC25DIFFIO_R37nW30DIFFIO_R37pW29
RDN3AD26RUP3AD25
DIFFIO_R43pAA30
DIFFIO_R44pAB29
DIFFIO_R45pAA28
DIFFIO_R45nY28
DQ5R/DIFFIO_R60n AA25
DQS1R/CQ1Rn/DPCLK8/DIFFIO_R38pW27
DQ5R/DIFFIO_R60p AB25
DQS3R/CQ3Rn/DPCLK7/DIFFIO_R50p AA22
DIFFIO_R38nW28
DIFFIO_R39nW26
DIFFIO_R41pV25
DIFFIO_R42pU21
DIFFIO_R41nV26
DIFFIO_R40nT25
DIFFIO_R51n AD28
DIFFIO_R52n AE30
DIFFIO_R33nT27DIFFIO_R33pT26
DIFFIO_R35nU28DIFFIO_R35pU27
DIFFIO_R48p AB27
DIFFIO_R49p AC27
DIFFIO_R46p AC30
DIFFIO_R47p AD29
DIFFIO_R59p AE25
DM1R/DIFFIO_R44nAA29
DIFFIO_R58nAH30DIFFIO_R58pAJ30
R191DNI R191DNI
R190DNI R190DNI
R177DNI R177DNIR169DNI R169DNI
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
RDN4RUP4
HSMA_RX_LED
HSMA_TX_LED
HSMB_SDAHSMB_SCL HSMB_T_SCL
HSMB_T_SDA
ENET_MDIO
HSMB_T_SCLHSMB_T_SDA
HSMA_SCLHSMA_SDA
SSRAM_BAn
SSRAM_ADVnSSRAM_ADSCnSSRAM_ADSPnSSRAM_E1nSSRAM_CLK
SSRAM_BBn
SSRAM_GnSSRAM_BWn
SSRAM_GWn
USER_PB[3:0]
FLASH_RESETn
FLASH_WEnFLASH_ADVnFLASH_CEn
HSMB_RX_LEDHSMB_TX_LED
USER_LED[7:0]
ENET_RESETnENET_MDIOENET_INTNENET_MDC
MAX_CSnMAX_WEn
CPU_RESETn
CLKIN_SMAPCIE_LED_X4PCIE_LED_X1
DDR2A_A9
HSMB_PSNTn
HSMB_TX_LED
ENET_TX_EN
LCD_DATA3
DDR2A_DM2
DDR2A_DQ16DDR2A_DQ17DDR2A_DQ18DDR2A_DQ19
DDR2A_DQ20
DDR2A_DQ21DDR2A_DQ22
DDR2A_DQ23
DDR2A_DQ8DDR2A_DQ9
DDR2A_DQ10DDR2A_DQ11
DDR2A_DQ12
DDR2A_DQ13
DDR2A_DQ14
DDR2A_DQ15
DDR2A_DQS2
DDR2A_CKE
DDR2A_DQS1DDR2A_DM1
HSMA_SDA
HSMA_PSNTn
CPU_RESETn
DDR2A_A7
DDR2A_A0
DDR2A_CASn
DDR2A_A10
DDR2A_A11
FLASH_RESETn
HSMA_TX_LED
FLASH_CEn
HSMA_RX_LED
DDR2A_ODT
DDR2A_CSn
FLASH_ADVn
RDN4RUP4
HSMB_SCL
DDR2A_DQ0
DDR2A_DQ1DDR2A_DQ2
DDR2A_DQ3
DDR2A_DQ4DDR2A_DQ5
DDR2A_DQ6DDR2A_DQ7
DDR2A_CLK_PDDR2A_CLK_N
ENET_MDC
DDR2A_DQS0
DDR2A_A1
DDR2A_A2
DDR2A_A3
DDR2A_A4
DDR2A_A5
DDR2A_A6
DDR2A_RASn
DDR2A_WEn
DDR2A_A12
DDR2A_BA0DDR2A_BA1
DDR2A_A8
DDR2A_DM0
HSMA_SCL
USER_LED5
LCD_D_Cn
USER_DIPSW4
MAX_WEn
MAX_CSn
ENET_TX_D3
FLASH_RDYBSYn
SSRAM_CLK
USER_DIPSW0
USER_LED7
ENET_RX_DV
LCD_DATA1
PCIE_SMBCLK
PCIE_SMBDATENET_INTN
ENET_RESETn
ENET_RX_D1
PCIE_LED_X1
USER_DIPSW2
HSMB_SDA
LCD_DATA6
ENET_RX_D3
USER_LED0
USER_DIPSW6
ENET_GTX_CLK
CLKIN_SMA
ENET_TX_D2
USER_DIPSW7
LCD_CSn
USER_PB0
ENET_RX_D0
HSMB_RX_LED
USER_LED4 LCD_DATA0
LCD_DATA5
LCD_WEn
LCD_DATA2
SSRAM_E1n
ENET_RX_D2
USER_DIPSW5
SSRAM_BAn
USER_DIPSW1
PCIE_LED_X4
PCIE_PERSTn
DDR2A_DQ24
DDR2A_DQ26DDR2A_DQ27
DDR2A_DQ28
DDR2A_DQ29DDR2A_DQ25DDR2A_DQ30
DDR2A_DQ31
DDR2A_DQS3
DDR2A_DM3
USER_LED6
ENET_TX_D0
USER_PB3
USER_PB2
USER_PB1
FLASH_WEn
ENET_TX_D1
LCD_DATA7
USER_LED1
LCD_DATA1
LCD_CSnLCD_WEnLCD_DATA0
ENET_RX_DVENET_TX_ENENET_GTX_CLK
LCD_DATA5LCD_DATA6LCD_DATA7
LCD_DATA3LCD_DATA2
LCD_T_DATA3LCD_T_DATA2
LCD_T_DATA5
LCD_T_DATA7LCD_T_DATA6
ENET_T_TX_ENENET_T_RX_DV
ENET_T_GTX_CLK
ENET_TX_D2ENET_TX_D1
ENET_TX_D3
ENET_RX_D1
ENET_TX_D0
ENET_RX_D2
ENET_RX_D0
ENET_RX_D3
ENET_T_TX_D3
ENET_T_RX_D0
ENET_T_TX_D1
ENET_T_TX_D0
ENET_T_TX_D2
ENET_T_RX_D1
ENET_T_RX_D3ENET_T_RX_D2
FSM_D1
HSMB_RX_D_P16
FSM_A1
FSM_A20
FSM_D1
HSMB_RX_D_P16
FSM_A1FSM_A201.8V_B7_B8
2.5V2.5V 1.8V1.8V
2.5V
1.8V 2.5V
1.8V
1.8V
2.5V
2.5V
1.8V
2.5V
1.8V
2.5V2.5V
1.8V 1.8V
1.8V 2.5V1.8V 2.5V
DDR2A_DQS[3:0]11
DDR2A_DQ[31:0]11
DDR2A_RASn11FLASH_RDYBSYn13,14DDR2A_WEn11DDR2A_CSn11DDR2A_ODT11DDR2A_ODT11DDR2A_CLK_P11DDR2A_CLK_N11
DDR2A_BA[1:0]11
DDR2A_A[12:0]11
DDR2A_DM[3:0]11
DDR2A_CKE11
ENET_MDIO9,15
ENET_T_RX_DV15
ENET_INTn15
ENET_T_GTX_CLK15
ENET_T_TX_D[3:0]15
ENET_T_RX_D[3:0]15
ENET_T_TX_EN15
ENET_RESETn15
ENET_T_RX_CLK9,15
USER_DIPSW[7:0]17,20
LCD_T_DATA[3:2]17
HSMA_RX_LED 17
HSMA_PSNTn14,16
HSMA_TX_LED 17
HSMB_PSNTn14,16
DDR2A_CASn11
PCIE_SMBCLK3PCIE_SMBDAT3
PCIE_PERSTn3
ENET_MDIO 9,15
HSMB_T_SDA 16HSMB_T_SCL 16
HSMA_T_SDA 16HSMA_T_SCL 16
SSRAM_E1n 13SSRAM_CLK 13
SSRAM_BAn 13
SSRAM_ADVn 13SSRAM_BBn 9,13
SSRAM_ADSCn 13SSRAM_ADSPn 13
SSRAM_Gn 9,13SSRAM_BWn 9,13
SSRAM_GWn 13,14
USER_PB[3:0] 17
FLASH_RESETn 13,14
FLASH_ADVn 13,14FLASH_CEn 13,14
FLASH_WEn 13,14
HSMB_RX_LED 17HSMB_TX_LED 17
USER_LED[7:0] 8,9,14,17
MAX_CSn 14MAX_WEn 14
ENET_RESETn 15ENET_MDIO 9,15ENET_INTN 15ENET_MDC 15
LCD_D_Cn17
CPU_RESETn 17
CLKIN_SMA 9
LCD_T_DATA[7:5]17
PCIE_LED_X4 17PCIE_LED_X1 17
LCD_CSn 17LCD_WEn 17LCD_DATA0 17LCD_DATA1 17
HSMB_RX_D_N15 5HSMB_RX_D_P15 5HSMB_RX_D_P14 5
HSMB_RX_D_P16 9
HSMB_RX_D_P7 5HSMB_RX_D_N8 5HSMB_RX_D_P8 5HSMB_RX_D_P9 5HSMB_RX_D_N9 5
HSMB_TX_D_N16 5
HSMB_TX_D_N15 5 HSMB_T_TX_D_N1516HSMB_T_RX_D_P1616HSMB_T_RX_D_N1516HSMB_T_RX_D_P1516HSMB_T_RX_D_P1416
HSMB_T_RX_D_N1316HSMB_T_TX_D_P1316HSMB_T_TX_D_N1216HSMB_T_TX_D_N1116HSMB_T_TX_D_P1116HSMB_T_RX_D_P1316
HSMB_TX_D_N12 9
HSMB_TX_D_P11 5HSMB_TX_D_N11 9
HSMB_RX_D_N13 5
HSMB_RX_D_P13 5
HSMB_TX_D_P13 5
FSM_D1 9,15FSM_A1 9,15FSM_A20 9,15
HSMB_RX_D_P16 9,15
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
7 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
7 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
7 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Cyclone IV GX Banks 7 & 8
ETHERNET CONTROL INTERFACE
ETHERNET RGMII INTERFACE
DDR2A x32 INTERFACE
removed ENET_CRS
SHARED BUS INTERFACE
LCD DISPLAY INTERFACE
HSMC INTERFACE
Cyclone IV GX Bank 8
EP4CGX150DF896_DDR2_Swap_hsmc
U10F
Version = 0.1 Preliminary
Cyclone IV GX Bank 8
EP4CGX150DF896_DDR2_Swap_hsmc
U10F
Version = 0.1 Preliminary
DIFFIO_T12pC6
DIFFIO_T13nC4
DQ5T/DIFFIO_T29n A12
DIFFIO_T33p G14
DIFFIO_T35n F16
DQ5T/DIFFIO_T32n A13DQ5T/DIFFIO_T32p A14
DQ1T/DIFFIO_T10pE6
DQ1T/DIFFIO_T5pF9
DQ5T/DIFFIO_T34p D16
DQS1T/CQ1Tn/DPCLK17/DIFFIO_T9pG10
DQ1T/DIFFIO_T9nF10
DQ3T/DIFFIO_T10nD5
DQS3T/CQ3Tn/DPCLK16/DIFFIO_T15nD7
DQS5T/CQ5Tn/DPCLK15/DIFFIO_T34n C16
DIFFIO_T30p F14
DIFFIO_T31n E16DIFFIO_T31p F15
DIFFIO_T33n G13
DIFFIO_T35p G15
DIFFIO_T3nE3DIFFIO_T3pE4
DIFFIO_T5nE9
DM3T/BWSn3T/DIFFIO_T16nA5
DM5T/DIFFIO_T20n A8
DQ1T/DIFFIO_T6nC9DQ1T/DIFFIO_T6pD9
DQ1T/DIFFIO_T7nD10DQ1T/DIFFIO_T7pE10
DQ1T/DIFFIO_T8nC3DQ1T/DIFFIO_T8pD3
DQ3T/DIFFIO_T11nC7DQ3T/DIFFIO_T11pD6
DQ3T/DIFFIO_T12nC5
DQ3T/DIFFIO_T13pD4
DQ3T/DIFFIO_T14pF11
DQ3T/DIFFIO_T17pD11
DIFFIO_T14nE12
DIFFIO_T15pE7
IO1_B8 D8
DQ3T/DIFFIO_T18pB6
DQ3T/DIFFIO_T19pB9DIFFIO_T21n C12
DIFFIO_T21p D12
DQ5T/DIFFIO_T22n F12
DQ5T/DIFFIO_T24p F13
DIFFIO_T26p D14
DIFFIO_T27n A10
DQ5T/DIFFIO_T26n C14
DQ5T/DIFFIO_T28p D15
DIFFIO_T16pA6
DIFFIO_T17nC11
DIFFIO_T18nA7
DIFFIO_T19nA9
DIFFIO_T1pJ9
DIFFIO_T20p B7
DIFFIO_T22p G12
DIFFIO_T23n B10DIFFIO_T23p C10
DIFFIO_T24n E13
DIFFIO_T25n C13DIFFIO_T25p D13
DIFFIO_T27p A11
DIFFIO_T28n C15
DIFFIO_T29p B12
DIFFIO_T2nF4DIFFIO_T2pF5
DIFFIO_T30n E15
U49
FXLA108
U49
FXLA108
A02
A13
A24
A35
A46
A57
A79A68
B2 17
B7 12
B5 14B4 15
B1 18B0 19
VCCB 20
B3 16
B6 13
OEn 11GND10
VCCA1
DA
P21
U46
FXLA108
U46
FXLA108
A02
A13
A24
A35
A46
A57
A79A68
B2 17
B7 12
B5 14B4 15
B1 18B0 19
VCCB 20
B3 16
B6 13
OEn 11GND10
VCCA1
DA
P21
R171 49.9R171 49.9
Cyclone IV GX Bank 7
EP4CGX150DF896_DDR2_Swap_hsmc
U10E
Version = 0.1 Preliminary
Cyclone IV GX Bank 7
EP4CGX150DF896_DDR2_Swap_hsmc
U10E
Version = 0.1 Preliminary
DQ0T/DIFFIO_T68pH24
DQ0T/DIFFIO_T69nC28
DQS2T/CQ3T/DPCLK13/DIFFIO_T47p G17
DIFFIO_T36n A16
DIFFIO_T38nC17
DQ4T/DIFFIO_T43p D19
DQ4T/DIFFIO_T45n E18
DIFFIO_T58p D25
DIFFIO_T59n A25
DQ4T/DIFFIO_T45p E19
DQ4T/DIFFIO_T49p C22
DM0T/DIFFIO_T64pG22
DM2T/DIFFIO_T54n A24
DQ4T/DIFFIO_T51p A23
DQS0T/CQ1T/DPCLK12/DIFFIO_T65nA29
DQ0T/DIFFIO_T69pD28
DQ2T/DIFFIO_T55n F19
DQ2T/DIFFIO_T56n D21
DQ2T/DIFFIO_T57n D22
DQ2T/DIFFIO_T59p A26
DQ2T/DIFFIO_T60p D26
DIFFIO_T55p G20
DIFFIO_T56p E21
DIFFIO_T57p E22
DIFFIO_T58n C25
DIFFIO_T60n C26
DIFFIO_T61n D24
DIFFIO_T62n A27
DIFFIO_T63n A28
DIFFIO_T67nK22DIFFIO_T67pK21
DM4T/DIFFIO_T36p B16
DQ0T/DIFFIO_T64nF22
DQ0T/DIFFIO_T65pB30
DQ0T/DIFFIO_T66nF23DQ0T/DIFFIO_T66pG23
DQ0T/DIFFIO_T68nG24
DQS4T/CQ5T/DPCLK14/DIFFIO_T37p K19
DQ2T/DIFFIO_T61p E24
IO1_B7E25
DQ2T/DIFFIO_T62p B27
DIFFIO_T41p D18
DIFFIO_T42nA19
IO2_B7F24
DQ2T/DIFFIO_T63p B28
IO3_B7K17
DQ4T/DIFFIO_T37n K18
DIFFIO_T47n F17
DIFFIO_T48nA21
RDN4F25
DQ4T/DIFFIO_T39n A17
RUP4G25
DQ4T/DIFFIO_T41n C18
DIFFIO_T52pD23
DIFFIO_T53nB24
DIFFIO_T38pD17
DIFFIO_T39p A18
DIFFIO_T40nF18DIFFIO_T40pG18
DIFFIO_T42pB18
DIFFIO_T43n C19
DIFFIO_T44nA20DIFFIO_T44pB19
DIFFIO_T46nC20DIFFIO_T46pD20
DIFFIO_T48pB21
DIFFIO_T49n B22
DIFFIO_T50nF20DIFFIO_T50pF21
DIFFIO_T51n A22
DIFFIO_T52nC23
DIFFIO_T53pC24
DIFFIO_T54p B25
C281
0.1uF
C281
0.1uFC319
0.1uF
C319
0.1uF
U29
FXLA108
U29
FXLA108
A02
A13
A24
A35
A46
A57
A79A68
B2 17
B7 12
B5 14B4 15
B1 18B0 19
VCCB 20
B3 16
B6 13
OEn 11GND10
VCCA1
DA
P21
C130
0.1uF
C130
0.1uFC129
0.1uF
C129
0.1uF
C116
0.1uF
C116
0.1uF
R170 49.9R170 49.9
C115
0.1uF
C115
0.1uF
C119
0.1uF
C119
0.1uF
U31
MAX3373
U31
MAX3373
VCCIO2 1
GND 2
VL3
VL_IO24VL_IO15 VCCIO1 8
VCC 7
TRI_STATE6
U39
MAX3373
U39
MAX3373
VCCIO2 1
GND 2
VL3
VL_IO24VL_IO15 VCCIO1 8
VCC 7
TRI_STATE6
C280
0.1uF
C280
0.1uF
C320
0.1uF
C320
0.1uF
C118
0.1uF
C118
0.1uF
U28
FXLA108
U28
FXLA108
A02
A13
A24
A35
A46
A57
A79A68
B2 17
B7 12
B5 14B4 15
B1 18B0 19
VCCB 20
B3 16
B6 13
OEn 11GND10
VCCA1
DA
P21
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
JTAG_BLASTER_TDIJTAG_TMS
JTAG_BLASTER_TDO
JTAG_TCK
MSEL1MSEL0
MSEL2
JTAG_FPGA_TDOJTAG_BLASTER_TDO
JTAG_TCKJTAG_TMS
FPGA_STATUSn
FPGA_CEn
FPGA_DATA0
FPGA_DCLK
USB_DISABLEn
JTAG_PCIE_TDI
JTAG_FPGA_TDOEPM2210_JTAG_EN
HSMA_JTAG_EN
HSMA_JTAG_TDI
HSMB_JTAG_EN
HSMB_JTAG_TDI
JTAG_EPM2210_TDO
FPGA_DATA1FPGA_DATA2FPGA_DATA3FPGA_DATA4FPGA_DATA5FPGA_DATA6FPGA_DATA7
HSMA_JTAG_TDO
HSMB_JTAG_TDO
SYS_RESETn
MSEL3
EPCS_DATA
FPGA_DCLK
EPCS_ASDIFPGA_CSOn
EPCS_DATA
FPGA_CEn
FPGA_DATA0
FPGA_CONFIGnFPGA_CONF_DONE
FPGA_DCLK
EPCS_ASDI
FPGA_CSOn
FPGA_DATA1
PCIE_JTAG_EN
JTAG_TMSJTAG_PCIE_TDOJTAG_PCIE_TDIJTAG_TCK
PCIE_JTAG_ENJTAG_BLASTER_TDI
JTAG_PCIE_TDO
EPM2210_JTAG_EN
HSMB_JTAG_ENHSMA_JTAG_EN
PCIE_JTAG_EN
FPGA_CSOn
USER_LED2
HSMB_TX_D_P4USER_LED2
MSEL0
MSEL3MSEL2
EPCS_DATA
EPCS_ASDI
FPGA_DCLK
FPGA_CSOn
HSMB_TX_D_P4
FPGA_CONFIGn
FPGA_CONF_DONE
2.5V
2.5V
2.5V
2.5V
3.3V
3.3V
2.5V 3.3V_PCIE
2.5V
2.5V
2.5V
3.3V
FPGA_CONF_DONE14,17FPGA_STATUSn14,18
FPGA_DCLK14
FPGA_CONFIGn14
JTAG_TMS14,16,18JTAG_TCK14,16,18
JTAG_FPGA_TDO14JTAG_BLASTER_TDO18
SYS_RESETn14,17
USB_DISABLEn3,18
HSMA_JTAG_TDI16HSMB_JTAG_TDI16JTAG_BLASTER_TDI18
JTAG_EPM2210_TDO14HSMA_JTAG_TDO16HSMB_JTAG_TDO16
FPGA_DATA[7:0]14
PCIE_JTAG_TCK3
PCIE_JTAG_TMS3PCIE_JTAG_TDO3PCIE_JTAG_TDI3
FPGA_CEn18
HSMB_TX_D_P4 16USER_LED2 14,17
MSEL0 14MSEL2 14MSEL3 14
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
8 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
8 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
8 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Cyclone IV GX Configuration
(uses JTAG mode only)USB Blaster Programming Header
CONFIGURATION INTERFACE
JTAG
Place at end of chain
Logic 0 = pin 5 --> pin 3 (EPM2210 Enabled)Logic 1 = pin 2 --> pin 3 (EPM2210 Bypass)
When Pins 4 & 8 are:
LOW --> Pins 5 & 7 = ON and Pins 2 & 10 = OFF
NLAS4717 Switch Functions
HIGH --> Pins 2 &10 = ON and Pins 5 & 7 = OFF
FPGA Not Installed Jumper
ON = not-in-chainOFF = in-chain
JTAG Chain Control
U51
DNI
U51
DNI
VCCA1
A12
A23
A34
A45
NC16
GND 7
VCCY 14
Y1 13
Y2 12
Y3 11
Y4 10
NC2 9
EN8
Cyclone IV GX Configuration
Bank 5
Bank 8
Bank 8
Bank 9
Bank 9
Bank 9Bank 3
Bank 3
Bank 9
EP4CGX150DF896_DDR2_Swap_hsmc
U10J
Version = 0.1 Preliminary
Cyclone IV GX Configuration
Bank 5
Bank 8
Bank 8
Bank 9
Bank 9
Bank 9Bank 3
Bank 3
Bank 9
EP4CGX150DF896_DDR2_Swap_hsmc
U10J
Version = 0.1 Preliminary
MSEL0 AD7
MSEL1 AD8
MSEL2 AC7
nCEC1
nCEO/DIFFIO_B1n AE7
nCONFIGB1
nCSO B4
nSTATUSAJ1
TCK F2
TDI E2TDO F1
MSEL3 AC8
TMS E1
DATA2/DIFFIO_T1nH9
DATA3/DIFFIO_T4pD1
DATA6/DIFFIO_B2nAE5
DATA7/DIFFIO_B3pAE10
CLKUSRA4
DATA0A3
DATA1/ASDOG9
DATA4/DM1T/BWSn1T/DIFFIO_T4nC2
DATA5/DIFFIO_B2pAE4
INIT_DONEAE8
CRC_ERROR/DIFFIO_B1pAD6
CONF_DONEAB9
DCLKB3
DEV_OE/DIFFIO_R55nAF28DEV_CLRn/DIFFIO_R55pAF27
R21410.0K R21410.0K
C31010pF C31010pF
R21510.0K R21510.0K
R243 1.00kR243 1.00k
C30910pF C30910pF
C331 DNIC331 DNI
C2
0.1uF
C2
0.1uF
R244 1.00kR244 1.00k
J6
70247-1051
J6
70247-1051
2468
10
13579
R222 24.9R222 24.9
C3480.1uF C3480.1uF
C1
0.1uF
C1
0.1uF
OPEN
SW5
TDA04H0SB1OPEN
SW5
TDA04H0SB1
1234 5
678
U2
NLAS4717EPMTR2G
U2
NLAS4717EPMTR2G
1
2
34
5
6
7
89
10
R230 10.0KR230 10.0K
R21910.0K R21910.0K
R224 24.9R224 24.9
R50 10.0KR50 10.0K
U1
NLAS4717EPMTR2G
U1
NLAS4717EPMTR2G
1
2
34
5
6
7
89
10
R228 100, 1%R228 100, 1%
C31110pF C31110pF
R225 10.0KR225 10.0K
R229 DNIR229 DNI
U18
EPCS128
U18
EPCS128
VC
C01
1
VC
C02
2
NC013
NC024
NC035
NC046
nCS 7
DATA 8
DCLK 16
ASDI 15NC0511
NC0612
NC0713
NC0814
GN
D10
VC
C03
9
D37
CMDSH2_3
D37
CMDSH2_3
C30810pF C30810pF
D38
CMDSH2_3
D38
CMDSH2_3
R53 10.0KR53 10.0K
R245 1.00kR245 1.00k
C3580.1uF C3580.1uF
R156 10.0KR156 10.0K
R54
1.00k
R54
1.00k
D40
CMDSH2_3
D40
CMDSH2_3D39
CMDSH2_3
D39
CMDSH2_3
R242 10.0KR242 10.0K
R22010.0K R22010.0K
R3
100, 1%
R3
100, 1%
J16
DNI
J16
DNI
11
33
55
77
2 2
4 4
6 6
8 8
99 10 10
R8
100, 1%
R8
100, 1%
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
HSMA_CLK_IN_P[2:1]
HSMA_CLK_IN_N[2:1]
HSMB_CLK_IN_N[2:1]
USER_DIPSW[7:0]
HSMA_CLK_OUT_N[2:1]
HSMA_CLK_OUT_P[2:1]
HSMA_TX_LED
HSMA_TX_D_N[16:0]
HSMA_TX_D_P[16:0]
HSMB_CLK_OUT_N[2:1]
HSMB_CLK_OUT_P[2:1]
HSMA_CLK_IN0
HSMB_CLK_IN0
HSMA_CLK_IN_N1HSMA_CLK_IN_P1
CLKOUT_SMA
CLKIN_SMA
PCIE_REFCLK_P PCIE_REFCK_PPCIE_REFCLK_N PCIE_REFCK_N
ENET_RX_CLK ENET_T_RX_CLK
HSMBT_CLK_IN0
HSMAT_CLK_IN0
HSMB_CLK_IN0
HSMA_CLK_IN0
CLKIN_50CLKIN_T_50
ENET_MDIO
USER_LED3
FLASH_OEn
SSRAM_Gn
SSRAM_BWnMAX_OEn
FSM_D3SSRAM_BBn
LCD_DATA4
HSMB_TX_D_N12HSMB_TX_D_P16
HSMB_TX_D_N11
HSMB_CLK_OUT_P2HSMB_T_CLK_OUT_P2
HSMB_CLK_OUT_P2HSMB_T_CLK_OUT_P2
CLKIN_SMA
HSMB_CLK_IN_P1
HSMA_CLK_IN_P2 HSMA_CLK_IN_N2
HSMB_TX_D_P16CLKIN_T_50
HSMA_CLK_IN_N1HSMA_CLK_IN_P1
PCIE_REFCK_NPCIE_REFCK_P
ENET_RX_CLK
HSMA_CLK_IN_N2HSMA_CLK_IN_P2
HSMAT_CLK_IN0
CLKA_IN_C_P0CLKA_IN_C_N0
HSMBT_CLK_IN0
FLASH_OEn
FSM_D3
SSRAM_GnUSER_LED3
SSRAM_BBnLCD_DATA4
CLKOUT_SMA
SSRAM_BWn
ENET_MDIO
MAX_OEn
HSMB_TX_D_N12
HSMB_TX_D_N11
CLKA_IN_C_P0
CLKA_IN_C_N0
CLKA_IN_P0
CLKA_IN_N0
N66134802
CLKA_IN_P1
N66160004
CLKA_IN_N1
CLKA_IN_C_P1
CLKA_IN_C_N1
CLKA_IN_C_P1CLKA_IN_C_N1
N66186150
CLKIN_125M_P
CLKIN_125M_N CLKIN_C_125M_N
CLKIN_C_125M_PCLKIN_C_125M_NCLKIN_C_125M_P
2.5V1.8V
2.5V1.8V
1.8V 2.5V
2.5V1.8V
1.8V2.5V
1.8V2.5V
1.8V2.5V
1.8V2.5V
1.8V2.5V
1.8V2.5V
2.5V
2.5V
2.5V
ENET_MDIO 15
HSMA_CLK_IN_P[2:1] 16
HSMA_CLK_IN_N[2:1] 16
HSMB_CLK_IN_N[2:1] 6,16
USER_DIPSW[7:0] 7,17,20
HSMA_CLK_OUT_N[2:1] 6,16
HSMA_CLK_OUT_P[2:1] 6,16
HSMA_TX_LED 7,17
HSMA_TX_D_N[16:0] 6,16
HSMA_TX_D_P[16:0] 6,16
HSMB_CLK_OUT_N[2:1] 6,16
HSMB_CLK_OUT_P[2:1] 5,6,16
HSMB_CLK_IN0 16
HSMA_CLK_IN0 16
PCIE_REFCLK_P3PCIE_REFCLK_N3
CLKA_IN_P010CLKA_IN_N010CLKA_IN_P110
CLKIN_5010,14
CLKA_IN_N110
CLKIN_125M_P10CLKIN_125M_N10
USER_LED3 14,17
ENET_T_RX_CLK 15
SSRAM_Gn 13
FLASH_OEn 13,14MAX_OEn 14SSRAM_BWn 13
FSM_D3 13,14SSRAM_BBn 13LCD_DATA4 17
HSMB_TX_D_N11 7HSMB_TX_D_N12 7HSMB_TX_D_P16 5
HSMB_CLK_OUT_P2 5HSMB_T_CLK_OUT_P2 16
CLKIN_SMA 7
HSMB_CLK_IN_P1 6,16
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
9 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
9 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
9 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Cyclone IV GX Clocks
HSMC PORT B
HSMC PORT A
USER INTERFACE
SMA Connector
(external clock source)
CLOCK INTERFACE
Input
Input
Input
Input
output
output
output
output
Input
output
U20
SN74AVC1T45
U20
SN74AVC1T45
GND2
VCCA1
A3 B 4
DIR 5
VCCB 6
R216 1.00kR216 1.00k
C383
0.1uF
C383
0.1uFR208
49.9
R208
49.9
U32
SN74AVC1T45
U32
SN74AVC1T45
GND2
VCCA1
A3 B 4
DIR 5
VCCB 6
C355
0.1uF
C355
0.1uF
R168100, 1% R168100, 1%
R210 1.00kR210 1.00k
R2680
R2680
C86
0.1uF
C86
0.1uF
C384
0.1uF
C384
0.1uF
R198
49.9
R198
49.9
R206
49.9
R206
49.9
C123
0.1uF
C123
0.1uF
C385
0.1uF
C385
0.1uF
R196 1.00kR196 1.00k
R212 1.00kR212 1.00k
J9J9
1
2345
C128
0.1uF
C128
0.1uF
C132
0.1uF
C132
0.1uF
C125
0.1uF
C125
0.1uF
C126
0.1uF
C126
0.1uF
Bank 3
Cyclone IV GX Clocks
Bank 3A
Bank 4
Bank 6
Bank 8A
Bank 8
Bank 3B
Bank 8B
Bank 7
Bank 5
EP4CGX150DF896_DDR2_Swap_hsmc
U10I
Version = 0.1 Preliminary
Bank 3
Cyclone IV GX Clocks
Bank 3A
Bank 4
Bank 6
Bank 8A
Bank 8
Bank 3B
Bank 8B
Bank 7
Bank 5
EP4CGX150DF896_DDR2_Swap_hsmc
U10I
Version = 0.1 Preliminary
PLL1_CLKOUTn AF6
REFCLK3n/CLKIO10/DIFFCLK_4nK15
REFCLK3p/CLKIO11/DIFFCLK_4pL15
PLL2_CLKOUTp G6
PLL3_CLKOUTn AF25
PLL2_CLKOUTn F6
REFCLK4p/DIFFCLK_8p/CLKIO17L11
REFCLK5n/DIFFCLK_9nL10
PLL3_CLKOUTp AF24
PLL4_CLKOUTn C27
REFCLK1n/DIFFCLK_1nW12REFCLK1p/DIFFCLK_1p/CLKIO22V12
REFCLK0p/DIFFCLK_0p/CLKIO20V11
REFCLK4n/DIFFCLK_8nK11
PLL5_CLKOUTn AG6
PLL4_CLKOUTp D27
PLL5_CLKOUTp AF7
PLL6_CLKOUTn AF9
REFCLK5p/DIFFCLK_9p/CLKIO19M10
PLL7_CLKOUTn F7
PLL6_CLKOUTp AE9
PLL7_CLKOUTp G7
PLL8_CLKOUTn F8PLL8_CLKOUTp G8
REFCLK0n/DIFFCLK_0nW11
REFCLK2p/CLKIO12/DIFFCLK_7pV15
REFCLK2n/CLKIO13/DIFFCLK_7nW15
CLKIO14/DIFFCLK_6pAJ16
CLKIO15/DIFFCLK_6nAK16
CLKIO4/DIFFCLK_2nV30
CLKIO5/DIFFCLK_2pV29
CLKIO6/DIFFCLK_3nT30
CLKIO7/DIFFCLK_3pT29
CLKIO8/DIFFCLK_5nA15
CLKIO9/DIFFCLK_5pB15
PLL1_CLKOUT9 AE6
R209
49.9
R209
49.9
U30
SN74AVC1T45
U30
SN74AVC1T45
GND2
VCCA1
A3 B 4
DIR 5
VCCB 6
C117
0.1uF
C117
0.1uF
R205
49.9
R205
49.9
R174100, 1% R174100, 1%
C70
0.1uF
C70
0.1uF
R67
49.9
R67
49.9
R207 1.00kR207 1.00k
R2670
R2670
R195 1.00kR195 1.00k
C85
0.1uF
C85
0.1uF
C69
0.1uF
C69
0.1uF
C354
0.1uF
C354
0.1uFU22
SN74AVC1T45
U22
SN74AVC1T45
GND2
VCCA1
A3 B 4
DIR 5
VCCB 6
U34
SN74AVC1T45
U34
SN74AVC1T45
GND2
VCCA1
A3 B 4
DIR 5
VCCB 6
J10J10
1
2345
C386
0.1uF
C386
0.1uF
R197
49.9
R197
49.9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
CLKIN_125M_P
CLKIN_125M_N
CLKIN_SMA_CNCLKIN_SMA_CP
CLKA_SEL
CLKIN_SMA_NCLKIN_SMA_CNCLKIN_SMA_CP
CLKIN_SMA_P
CLKA_IN_N0CLKA_IN_P0
CLKA_IN_P1CLKA_IN_N1
CLK125_EN
CLKIN_50
CLK50_EN
CLKA_EN
USER_FACTORYCLK125_EN
CLKA_SEL
100M_OSC_N
100M_OSC_PCLKA_SDA
CLKA_SCL
CLKA_EN
2.5V
3.3V
3.3V
3.3V
3.3V
2.5V
2.5V2.5V
2.5V
2.5V
CLKIN_509,14
CLKA_SDA14CLKA_SCL14CLKA_EN14
CLKIN_125M_N9CLKIN_125M_P9
CLK125_EN14CLK50_EN
CLKA_IN_N19CLKA_IN_P19CLKA_IN_N09CLKA_IN_P09
USER_FACTORY9,14
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
10 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
10 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
10 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
General Clock Circuitry
CLOCK INTERFACE
From EPM2210 and DIP SW1
To Board SettingsDIP Switch
LVDS
LVPECL INPUT CLOCK
To FPGA andEPM2210
Clock Enable
CLKA_SEL Settings:
CLKp/n
Setting
PCLKp/nHigh
SWx, DIP4
Low
From EPM2210 and DIP SW1
NIOS CPU Clock
From EPM2210
From EPM2210
C376
2.2uF
C376
2.2uF
C930.1uFC930.1uF
U25
ICS8543
U25
ICS8543
GN
D1
CLK_EN2
CLK_SEL3
CLKp4
CLKn5
PCLKp6
PCLKn7
OE8
GN
D9
VD
D10
Q3n 11Q3p 12
GN
D13
Q2n 14Q2p 15
Q1n 16Q1p 17
VD
D18
Q0n 19Q0p 20
R75100, 1% R75100, 1%R74100, 1% R74100, 1%
X2
125.0MHz
X2
125.0MHz
EN1
NC2
GND 3
OUT 4
OUTn 5
VCC6
X4
100MHz
X4
100MHz
OE2
NC 1GND3
CLK+ 4
CLK- 5
VCC 6
SDA7
SCL8
R112 1.00kR112 1.00k
C96
0.1uF
C96
0.1uF
R79100, 1%R79100, 1%
C90
0.1uF
C90
0.1uFR111 1.00kR111 1.00k
R69124 R69124
R110 1.00kR110 1.00k
J11LTI-SASF546-P26-X1
J11LTI-SASF546-P26-X1
1
2345
R65 4.7KR65 4.7K
C76
0.1uF
C76
0.1uF
C75
10uF
C75
10uF
C95
0.1uF
C95
0.1uF
R7284.5 R7284.5
R68124 R68124
C89
0.1uF
C89
0.1uF
C101
0.1uF
C101
0.1uF
R70 4.7KR70 4.7K
C106
0.1uF
C106
0.1uF
J12LTI-SASF546-P26-X1
J12LTI-SASF546-P26-X1
1
2345
R109 1.00kR109 1.00k
X3
ECS-3525-500-B
X3
ECS-3525-500-B
VCC 4
GND2 OUT 3
EN1
C17
2.2uF
C17
2.2uF
OPEN
SW1
TDA04H0SB1
OPEN
SW1
TDA04H0SB1
12345
678
C940.1uFC940.1uF
R260 4.7KR260 4.7KR259 4.7KR259 4.7K
C88
10uF
C88
10uF
R7384.5 R7384.5
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
DDR2A_CLK_P
DDR2A_CLK_N
DDR2A_A0
DDR2A_CKE
DDR2A_DQS2
DDR2A_CLK_PDDR2A_CLK_N
DDR2A_BA0DDR2A_BA1
DDR2A_RASn
DDR2A_DM1
DDR2A_CKEDDR2A_CLK_PDDR2A_CLK_N
DDR2A_CASnDDR2A_WEnDDR2A_CSn
DDR2A_ODT
DDR2A_DQS1
DDR2A_DM2
DDR2A_A1DDR2A_A2DDR2A_A3DDR2A_A4DDR2A_A5DDR2A_A6DDR2A_A7DDR2A_A8DDR2A_A9DDR2A_A10DDR2A_A11DDR2A_A12
DDR2A_A10DDR2A_A11DDR2A_A12
DDR2A_BA0DDR2A_BA1
DDR2A_RASnDDR2A_CASnDDR2A_WEnDDR2A_CSn
DDR2A_ODT
DDR2A_A1DDR2A_A2DDR2A_A3DDR2A_A4DDR2A_A5DDR2A_A6DDR2A_A7DDR2A_A8DDR2A_A9
DDR2A_A0
DDR2A_DQ27DDR2A_DQ28DDR2A_DQ29DDR2A_DQ30DDR2A_DQ31
DDR2A_DQ25DDR2A_DQ26
DDR2A_DQ24
DDR2A_DQ19DDR2A_DQ20DDR2A_DQ21DDR2A_DQ22DDR2A_DQ23
DDR2A_DQ0
DDR2A_DQ2DDR2A_DQ3
DDR2A_DQ1
DDR2A_DQ4DDR2A_DQ5DDR2A_DQ6DDR2A_DQ7
DDR2A_DQ8DDR2A_DQ9DDR2A_DQ10
DDR2A_DQ17DDR2A_DQ18
DDR2A_DQ11DDR2A_DQ12
DDR2A_DQ16
DDR2A_DQS0DDR2A_DQS1
DDR2A_DM1DDR2A_DM0
DDR2A_CKE
DDR2A_A1DDR2A_A2
DDR2A_A10
DDR2A_A3
DDR2A_A11
DDR2A_A4
DDR2A_A12
DDR2A_A5DDR2A_A6DDR2A_A7
DDR2A_A8
DDR2A_BA0DDR2A_BA1
DDR2A_RASnDDR2A_CASnDDR2A_WEnDDR2A_CSnDDR2A_ODT
DDR2A_A9
DDR2A_A0
DDR2A_DQ16DDR2A_DQ17DDR2A_DQ18DDR2A_DQ19DDR2A_DQ20DDR2A_DQ21DDR2A_DQ22DDR2A_DQ23
DDR2A_DQ8DDR2A_DQ9DDR2A_DQ10DDR2A_DQ11DDR2A_DQ12DDR2A_DQ13DDR2A_DQ14DDR2A_DQ15
DDR2A_DQS2DDR2A_DQS3
DDR2A_DM2DDR2A_DM3
DDR2A_DQS0
DDR2A_DQS3
DDR2A_DM0DDR2A_DM3
DDR2A_DQ0
DDR2A_DQ2DDR2A_DQ3DDR2A_DQ4
DDR2A_DQ1
DDR2A_DQ5DDR2A_DQ6DDR2A_DQ7
DDR2A_DQ26DDR2A_DQ27
DDR2A_DQ24
DDR2A_DQ28
DDR2A_DQ25
DDR2A_DQ29DDR2A_DQ30DDR2A_DQ31
DDR2A_DQ13DDR2A_DQ14DDR2A_DQ15
VREF_B7_B8VREF_B7_B8
1.8V1.8V
1.8V
1.8V
VTT_B7_B8
VTT_B7_B8
VTT_B7_B8
DDR2A_RASn7
DDR2A_ODT7DDR2A_CSn7DDR2A_WEn7
DDR2A_CKE7
DDR2A_CASn7
DDR2A_BA[1:0]7
DDR2A_A[12:0]7
DDR2A_CLK_P7DDR2A_CLK_N7
DDR2A_DQS[3:0]7
DDR2A_DQ[31:0]7
DDR2A_DM[3:0]7
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
11 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
11 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
11 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
PLACE CAPS NEAR U12
PLACE CAPS NEAR U11
DDR2 SDRAM x32 TOP
RN16C DNIRN16C DNI3 14
C255
0.1uF
C255
0.1uF
RN6A 56RN6A 561 16
V21V21
C218
4.7nF
C218
4.7nF
RN3D DNIRN3D DNI4 13
RN10F 56RN10F 566 11
RN17H DNIRN17H DNI8 9
U8B
MT47H16M16
U8B
MT47H16M16
VSS A3
VSS E3
VSS J3
VSS N1
VSS P9
VSSDL J7
VSSQ A7
VSSQ B2
VSSQ B8
VSSQ D2
VSSQ D8
VSSQ E7
VSSQ F2
VSSQ F8
VSSQ H2
VSSQ H8
VDDA1
VDDE1
VDDM9
VDDR1
VDDLJ1
VDDQA9
VDDQC1
VDDQC3
VDDQC7
VDDQC9
VDDQE9
VDDQG1
VDDQG3
VDDQG7
VDDQG9
NC1 A2
NC2 E2
VDDJ9
C260
0.1uF
C260
0.1uF
V16V16
RN5B 56RN5B 562 15
RN12E 56RN12E 565 12
C284
0.1uF
C284
0.1uF
C301
0.01uF
C301
0.01uF
RN2E DNIRN2E DNI5 12
CN9 0.1uf x 4CN9 0.1uf x 4
17
3546
28
RN16F DNIRN16F DNI6 11
RN4C DNIRN4C DNI3 14
CN11 0.1uf x 4CN11 0.1uf x 4
17
3546
28
C300
0.1uF
C300
0.1uF
C229
0.01uF
C229
0.01uF
V15V15
RN4E DNIRN4E DNI5 12
V6V6
RN17A DNIRN17A DNI1 16
V10V10
RN4A DNIRN4A DNI1 16
CN4 0.1uf x 4CN4 0.1uf x 4
17
3546
28
RN2F DNIRN2F DNI6 11
RN2H DNIRN2H DNI8 9
RN5F 56RN5F 566 11
V19V19
C276
0.1uF
C276
0.1uF
RN6H 56RN6H 568 9
RN16B DNIRN16B DNI2 15
V17V17
V13V13
RN15C DNIRN15C DNI3 14
RN3E DNIRN3E DNI5 12
RN5A 56RN5A 561 16
CN17 0.1uf x 4CN17 0.1uf x 4
17
3546
28
C213
0.01uF
C213
0.01uF
RN15F DNIRN15F DNI6 11
C215
0.1uF
C215
0.1uF
RN3A DNIRN3A DNI1 16
RN16G DNIRN16G DNI7 10
RN10C 56RN10C 563 14
RN5E 56RN5E 565 12
V9V9
C252
0.1uF
C252
0.1uF
RN3B DNIRN3B DNI2 15
RN17D DNIRN17D DNI4 13
RN12H 56RN12H 568 9
RN4D DNIRN4D DNI4 13
RN5C 56RN5C 563 14
RN2D DNIRN2D DNI4 13
RN6F 56RN6F 566 11
RN6G 56RN6G 567 10
RN10E 56RN10E 565 12
C262
0.1uF
C262
0.1uF
RN12C 56RN12C 563 14
C305
0.01uF
C305
0.01uF
C241
0.1uF
C241
0.1uF
RN15D DNIRN15D DNI4 13
RN6C 56RN6C 563 14
C272
4.7nF
C272
4.7nF
RN15A DNIRN15A DNI1 16
C282
0.1uF
C282
0.1uF
V14V14
V23V23C244
0.1uF
C244
0.1uF
V12V12
CN15 0.1uf x 4CN15 0.1uf x 4
17
3546
28
RN2A DNIRN2A DNI1 16
C263
0.1uF
C263
0.1uF
RN15E DNIRN15E DNI5 12
RN6B 56RN6B 562 15
V22V22 RN10H 56RN10H 568 9
CN1 0.1uf x 4CN1 0.1uf x 4
17
3546
28
CN3 0.1uf x 4CN3 0.1uf x 4
17
3546
28
C261
0.01uF
C261
0.01uF
V25V25
RN4F DNIRN4F DNI6 11
C214
0.1uF
C214
0.1uF
C230
0.1uF
C230
0.1uF
V18V18
RN5D 56RN5D 564 13
RN12G 56RN12G 567 10
RN10B 56RN10B 562 15
C303
0.1uF
C303
0.1uF
RN10D 56RN10D 564 13
RN12D 56RN12D 564 13
RN17G DNIRN17G DNI7 10
V24V24
C254
0.01uF
C254
0.01uF
RN6E 56RN6E 565 12
RN15B DNIRN15B DNI2 15
RN12F 56RN12F 566 11
V20V20
C283
0.1uF
C283
0.1uF
R213
100, 1%
R213
100, 1%
RN16E DNIRN16E DNI5 12
RN16D DNIRN16D DNI4 13
C287
0.1uF
C287
0.1uF
CN2 0.1uf x 4CN2 0.1uf x 4
17
3546
28
C256
4.7nF
C256
4.7nF
CN8 0.1uf x 4CN8 0.1uf x 4
17
3546
28
RN4B DNIRN4B DNI2 15
U8A
MT47H16M16
U8A
MT47H16M16
ODTK9
CSnL8
RASnK7
CASnL7
WEnK3
LDMF3
UDMB3
BA0L2
BA1L3 UDQS_P B7
UDQS_N A8
LDQS_P F7
LDQS_N E8
VREF J2
RFUL1
A0M8
A1M3
A2M7
A3N2
A4N8
A5N3
A6N7
A7P2
A8P8
A9P3
A10M2
A11P7
A12R2
RFU/A14R3
RFU/A15R7
DQ0 G8
DQ1 G2
DQ2 H7
DQ3 H3
DQ4 H1
DQ5 H9
DQ6 F1
DQ7 F9
DQ8 C8
DQ9 C2
DQ10 D7
DQ11 D3
DQ12 D1
DQ13 D9
DQ14 B1
DQ15 B9
CK_P J8
CK_N K8
CKE K2
RFU/A13R8
RN17C DNIRN17C DNI3 14
RN15H DNIRN15H DNI8 9
RN6D 56RN6D 564 13
U15A
MT47H16M16
U15A
MT47H16M16
ODTK9
CSnL8
RASnK7
CASnL7
WEnK3
LDMF3
UDMB3
BA0L2
BA1L3 UDQS_P B7
UDQS_N A8
LDQS_P F7
LDQS_N E8
VREF J2
RFUL1
A0M8
A1M3
A2M7
A3N2
A4N8
A5N3
A6N7
A7P2
A8P8
A9P3
A10M2
A11P7
A12R2
RFU/A14R3
RFU/A15R7
DQ0 G8
DQ1 G2
DQ2 H7
DQ3 H3
DQ4 H1
DQ5 H9
DQ6 F1
DQ7 F9
DQ8 C8
DQ9 C2
DQ10 D7
DQ11 D3
DQ12 D1
DQ13 D9
DQ14 B1
DQ15 B9
CK_P J8
CK_N K8
CKE K2
RFU/A13R8
RN16H DNIRN16H DNI8 9
RN16A DNIRN16A DNI1 16
V5V5
RN17E DNIRN17E DNI5 12
RN2C DNIRN2C DNI3 14 RN17B DNIRN17B DNI2 15
RN4G DNIRN4G DNI7 10
RN5G 56RN5G 567 10
C302
0.1uF
C302
0.1uF
RN12A 56RN12A 561 16
RN17F DNIRN17F DNI6 11
U15B
MT47H16M16
U15B
MT47H16M16
VSS A3
VSS E3
VSS J3
VSS N1
VSS P9
VSSDL J7
VSSQ A7
VSSQ B2
VSSQ B8
VSSQ D2
VSSQ D8
VSSQ E7
VSSQ F2
VSSQ F8
VSSQ H2
VSSQ H8
VDDA1
VDDE1
VDDM9
VDDR1
VDDLJ1
VDDQA9
VDDQC1
VDDQC3
VDDQC7
VDDQC9
VDDQE9
VDDQG1
VDDQG3
VDDQG7
VDDQG9
NC1 A2
NC2 E2
VDDJ9
RN10G 56RN10G 567 10
RN3C DNIRN3C DNI3 14
C264
4.7nF
C264
4.7nF
CN16 0.1uf x 4CN16 0.1uf x 4
17
3546
28
V7V7
C304
0.1uF
C304
0.1uF
RN15G DNIRN15G DNI7 10
RN10A 56RN10A 561 16
RN3G DNIRN3G DNI7 10
C211
0.1uF
C211
0.1uF
C212
0.1uF
C212
0.1uF
RN12B 56RN12B 562 15
RN3H DNIRN3H DNI8 9
C253
0.1uF
C253
0.1uF
RN3F DNIRN3F DNI6 11
C231
0.1uF
C231
0.1uF
V11V11
RN2B DNIRN2B DNI2 15
V8V8
RN2G DNIRN2G DNI7 10
C219
0.1uF
C219
0.1uF
RN5H 56RN5H 568 9
RN4H DNIRN4H DNI8 9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
DDR2B_CLK_P
DDR2B_CLK_N
DDR2B_A0
DDR2B_DQS3
DDR2B_CKE
DDR2B_DQS2
DDR2B_CLK_PDDR2B_CLK_N
DDR2B_BA0DDR2B_BA1
DDR2B_RASn
DDR2B_DM0DDR2B_DM1
DDR2B_DQS0
DDR2B_CKEDDR2B_CLK_PDDR2B_CLK_N
DDR2B_CASnDDR2B_WEnDDR2B_CSn
DDR2B_ODT
DDR2B_DQS1
DDR2B_DM2DDR2B_DM3
DDR2B_A1DDR2B_A2DDR2B_A3DDR2B_A4DDR2B_A5DDR2B_A6DDR2B_A7DDR2B_A8DDR2B_A9DDR2B_A10DDR2B_A11DDR2B_A12
DDR2B_A10DDR2B_A11DDR2B_A12
DDR2B_BA0DDR2B_BA1
DDR2B_RASnDDR2B_CASnDDR2B_WEnDDR2B_CSn
DDR2B_ODT
DDR2B_A1DDR2B_A2DDR2B_A3DDR2B_A4DDR2B_A5DDR2B_A6DDR2B_A7DDR2B_A8DDR2B_A9
DDR2B_A0
DDR2B_DQ27DDR2B_DQ28DDR2B_DQ29DDR2B_DQ30DDR2B_DQ31
DDR2B_DQ25DDR2B_DQ26
DDR2B_DQ24
DDR2B_DQ19DDR2B_DQ20DDR2B_DQ21DDR2B_DQ22DDR2B_DQ23
DDR2B_DQ0
DDR2B_DQ2DDR2B_DQ3
DDR2B_DQ1
DDR2B_DQ4DDR2B_DQ5DDR2B_DQ6DDR2B_DQ7
DDR2B_DQ8DDR2B_DQ9DDR2B_DQ10
DDR2B_DQ17DDR2B_DQ18
DDR2B_DQ11DDR2B_DQ12
DDR2B_DQ16
DDR2B_DQS0DDR2B_DQS1
DDR2B_DM1DDR2B_DM0
DDR2B_CKE
DDR2B_A1DDR2B_A2
DDR2B_A10
DDR2B_A3
DDR2B_A11
DDR2B_A4
DDR2B_A12
DDR2B_A5DDR2B_A6DDR2B_A7
DDR2B_A8
DDR2B_BA0DDR2B_BA1
DDR2B_RASnDDR2B_CASnDDR2B_WEnDDR2B_CSnDDR2B_ODT
DDR2B_A9
DDR2B_A0
DDR2B_DQ16DDR2B_DQ17DDR2B_DQ18DDR2B_DQ19DDR2B_DQ20DDR2B_DQ21DDR2B_DQ22DDR2B_DQ23DDR2B_DQ24DDR2B_DQ25DDR2B_DQ26DDR2B_DQ27DDR2B_DQ28
DDR2B_DQ0DDR2B_DQ1DDR2B_DQ2
DDR2B_DQ29DDR2B_DQ30
DDR2B_DQ3DDR2B_DQ4DDR2B_DQ5DDR2B_DQ6DDR2B_DQ7DDR2B_DQ8DDR2B_DQ9DDR2B_DQ10DDR2B_DQ11DDR2B_DQ12DDR2B_DQ13DDR2B_DQ14DDR2B_DQ15 DDR2B_DQ31
DDR2B_DQS2DDR2B_DQS3
DDR2B_DM2DDR2B_DM3
DDR2B_DQ13DDR2B_DQ14DDR2B_DQ15
VREF_B3_B4VREF_B3_B4
1.8V1.8V
1.8V
1.8V
VTT_B3_B4
VTT_B3_B4
VTT_B3_B4
DDR2B_RASn5
DDR2B_ODT5DDR2B_CSn5DDR2B_WEn5
DDR2B_CKE5
DDR2B_CASn5
DDR2B_BA[1:0]5
DDR2B_A[12:0]5
DDR2B_CLK_P5DDR2B_CLK_N5
DDR2B_DQS[3:0]5
DDR2B_DQ[31:0]5
DDR2B_DM[3:0]5
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
12 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
12 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
12 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
PLACE CAPS NEAR U12
PLACE CAPS NEAR U11
DDR2 SDRAM x32 Bottom
RN11A 56RN11A 561 16
C368
4.7nF
C368
4.7nF
RN21G DNIRN21G DNI7 10
RN11F 56RN11F 566 11
C274
0.1uF
C274
0.1uF
RN19C DNIRN19C DNI3 14
U19A
MT47H16M16
U19A
MT47H16M16
ODTK9
CSnL8
RASnK7
CASnL7
WEnK3
LDMF3
UDMB3
BA0L2
BA1L3 UDQS_P B7
UDQS_N A8
LDQS_P F7
LDQS_N E8
VREF J2
RFUL1
A0M8
A1M3
A2M7
A3N2
A4N8
A5N3
A6N7
A7P2
A8P8
A9P3
A10M2
A11P7
A12R2
RFU/A14R3
RFU/A15R7
DQ0 G8
DQ1 G2
DQ2 H7
DQ3 H3
DQ4 H1
DQ5 H9
DQ6 F1
DQ7 F9
DQ8 C8
DQ9 C2
DQ10 D7
DQ11 D3
DQ12 D1
DQ13 D9
DQ14 B1
DQ15 B9
CK_P J8
CK_N K8
CKE K2
RFU/A13R8
RN21F DNIRN21F DNI6 11
RN18F 56RN18F 566 11
C322
0.01uF
C322
0.01uF
CN14 0.1uf x 4CN14 0.1uf x 4
17
3546
28
U17B
MT47H16M16
U17B
MT47H16M16
VSS A3
VSS E3
VSS J3
VSS N1
VSS P9
VSSDL J7
VSSQ A7
VSSQ B2
VSSQ B8
VSSQ D2
VSSQ D8
VSSQ E7
VSSQ F2
VSSQ F8
VSSQ H2
VSSQ H8
VDDA1
VDDE1
VDDM9
VDDR1
VDDLJ1
VDDQA9
VDDQC1
VDDQC3
VDDQC7
VDDQC9
VDDQE9
VDDQG1
VDDQG3
VDDQG7
VDDQG9
NC1 A2
NC2 E2
VDDJ9
RN21E DNIRN21E DNI5 12
V34V34
RN8F DNIRN8F DNI6 11
C295
0.1uF
C295
0.1uF
RN20C DNIRN20C DNI3 14
RN7F DNIRN7F DNI6 11
V30V30
RN13B 56RN13B 562 15V33V33
C315
0.1uF
C315
0.1uF
RN20E DNIRN20E DNI5 12
RN9B DNIRN9B DNI2 15
C317
0.1uF
C317
0.1uF
V44V44
RN7D DNIRN7D DNI4 13
RN14F 56RN14F 566 11
V31V31
RN9H DNIRN9H DNI8 9
RN13C 56RN13C 563 14
C370
0.1uF
C370
0.1uF
RN13G 56RN13G 567 10
RN19G DNIRN19G DNI7 10
RN8B DNIRN8B DNI2 15
V38V38
C268
0.1uF
C268
0.1uF
RN11G 56RN11G 567 10
RN9C DNIRN9C DNI3 14
RN7E DNIRN7E DNI5 12
RN19F DNIRN19F DNI6 11
RN7G DNIRN7G DNI7 10
RN7B DNIRN7B DNI2 15
C296
0.1uF
C296
0.1uFRN18B 56RN18B 562 15
RN18C 56RN18C 563 14
R223
100, 1%
R223
100, 1%
CN19 0.1uf x 4CN19 0.1uf x 4
17
3546
28
RN7C DNIRN7C DNI3 14
C339
0.1uF
C339
0.1uF
RN18E 56RN18E 565 12
CN6 0.1uf x 4CN6 0.1uf x 4
17
3546
28
RN20D DNIRN20D DNI4 13
RN20B DNIRN20B DNI2 15
C293
0.01uF
C293
0.01uF
C294
0.1uF
C294
0.1uF
V26V26
V45V45 RN14D 56RN14D 564 13
RN14H 56RN14H 568 9
RN14A 56RN14A 561 16
C353
0.1uF
C353
0.1uF
V32V32
RN21H DNIRN21H DNI8 9
C278
0.1uF
C278
0.1uF
RN8E DNIRN8E DNI5 12
V27V27
CN13 0.1uf x 4CN13 0.1uf x 4
17
3546
28
C267
0.01uF
C267
0.01uF
U19B
MT47H16M16
U19B
MT47H16M16
VSS A3
VSS E3
VSS J3
VSS N1
VSS P9
VSSDL J7
VSSQ A7
VSSQ B2
VSSQ B8
VSSQ D2
VSSQ D8
VSSQ E7
VSSQ F2
VSSQ F8
VSSQ H2
VSSQ H8
VDDA1
VDDE1
VDDM9
VDDR1
VDDLJ1
VDDQA9
VDDQC1
VDDQC3
VDDQC7
VDDQC9
VDDQE9
VDDQG1
VDDQG3
VDDQG7
VDDQG9
NC1 A2
NC2 E2
VDDJ9
C338
0.1uF
C338
0.1uF
RN14G 56RN14G 567 10
RN11E 56RN11E 565 12
RN13D 56RN13D 564 13
V35V35
C318
0.01uF
C318
0.01uF
V40V40
RN18D 56RN18D 564 13
CN10 0.1uf x 4CN10 0.1uf x 4
17
3546
28
RN8G DNIRN8G DNI7 10
C269
4.7nF
C269
4.7nF
CN5 0.1uf x 4CN5 0.1uf x 4
17
3546
28
RN13H 56RN13H 568 9
RN21C DNIRN21C DNI3 14
C292
0.1uF
C292
0.1uF
C352
0.1uF
C352
0.1uF
RN9E DNIRN9E DNI5 12
RN18G 56RN18G 567 10
C286
4.7nF
C286
4.7nF
RN11B 56RN11B 562 15
RN21A DNIRN21A DNI1 16
RN19D DNIRN19D DNI4 13
C312
0.1uF
C312
0.1uF
RN20G DNIRN20G DNI7 10
V43V43
RN11D 56RN11D 564 13C279
0.1uF
C279
0.1uF
RN14C 56RN14C 563 14
RN8C DNIRN8C DNI3 14
CN20 0.1uf x 4CN20 0.1uf x 4
17
3546
28
RN20F DNIRN20F DNI6 11
CN18 0.1uf x 4CN18 0.1uf x 4
17
3546
28
RN21D DNIRN21D DNI4 13
C371
0.1uF
C371
0.1uF
RN8A DNIRN8A DNI1 16
CN7 0.1uf x 4CN7 0.1uf x 4
17
3546
28
RN19H DNIRN19H DNI8 9
RN9F DNIRN9F DNI6 11
V46V46
C313
0.1uF
C313
0.1uF
RN19E DNIRN19E DNI5 12
RN9D DNIRN9D DNI4 13
RN7A DNIRN7A DNI1 16
C351
0.1uF
C351
0.1uF
V39V39
U17A
MT47H16M16
U17A
MT47H16M16
ODTK9
CSnL8
RASnK7
CASnL7
WEnK3
LDMF3
UDMB3
BA0L2
BA1L3 UDQS_P B7
UDQS_N A8
LDQS_P F7
LDQS_N E8
VREF J2
RFUL1
A0M8
A1M3
A2M7
A3N2
A4N8
A5N3
A6N7
A7P2
A8P8
A9P3
A10M2
A11P7
A12R2
RFU/A14R3
RFU/A15R7
DQ0 G8
DQ1 G2
DQ2 H7
DQ3 H3
DQ4 H1
DQ5 H9
DQ6 F1
DQ7 F9
DQ8 C8
DQ9 C2
DQ10 D7
DQ11 D3
DQ12 D1
DQ13 D9
DQ14 B1
DQ15 B9
CK_P J8
CK_N K8
CKE K2
RFU/A13R8
V37V37
RN13F 56RN13F 566 11
RN18H 56RN18H 568 9
C369
0.01uF
C369
0.01uF
RN8D DNIRN8D DNI4 13
V41V41
V36V36
RN19B DNIRN19B DNI2 15
RN9G DNIRN9G DNI7 10
C314
0.01uF
C314
0.01uF
RN14E 56RN14E 565 12
RN20A DNIRN20A DNI1 16
RN9A DNIRN9A DNI1 16
V29V29
RN7H DNIRN7H DNI8 9
C257
0.1uF
C257
0.1uF
RN11H 56RN11H 568 9
RN13A 56RN13A 561 16
CN12 0.1uf x 4CN12 0.1uf x 4
17
3546
28
RN14B 56RN14B 562 15
C367
0.1uF
C367
0.1uF
V28V28C273
0.1uF
C273
0.1uF
RN20H DNIRN20H DNI8 9
RN18A 56RN18A 561 16
RN8H DNIRN8H DNI8 9
V42V42
C316
4.7nF
C316
4.7nF
RN11C 56RN11C 563 14
C266
0.1uF
C266
0.1uF
RN21B DNIRN21B DNI2 15
RN13E 56RN13E 565 12
C258
0.1uF
C258
0.1uF
RN19A DNIRN19A DNI1 16
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FLASH_RESETn
FLASH_RDYBSYn
FLASH_WEnFLASH_OEnFLASH_CEn
FLASH_RDYBSYn
FLASH_WPn
FLASH_RESETnFLASH_CEnFLASH_OEnFLASH_WEn
FLASH_WPn
FLASH_CLK
FLASH_ADVn
FSM_D11FSM_D12FSM_D13FSM_D14FSM_D15
FSM_D9FSM_D10
FSM_D8
FSM_D0FSM_D1FSM_D2FSM_D3FSM_D4FSM_D5FSM_D6FSM_D7
FSM_D[15:0]
FLASH_RDYBSYn
FLASH_RESETnFLASH_WEnFLASH_OEn
FSM_A[25:1]
FLASH_CEnFLASH_CLKFLASH_ADVn
SSRAM_BWn
SSRAM_ADSCnSSRAM_ADVn
SSRAM_CLK
SSRAM_ADSPn
FSM_A9FSM_A10FSM_A11FSM_A12FSM_A13FSM_A14FSM_A15FSM_A16FSM_A17FSM_A18FSM_A19FSM_A20
FSM_A1FSM_A2FSM_A3FSM_A4
FSM_A21
FSM_A5
FSM_A22
FSM_A6
FSM_A23
FSM_A7
FSM_A24
FSM_A8
FSM_A25
SSRAM_GWn
SSRAM_E2SSRAM_E3nSSRAM_FTnSSRAM_LBOn
SSRAM_E1n
SSRAM_BAnSSRAM_BBn
SSRAM_Gn
FSM_A9
FSM_A10
FSM_A11FSM_A12
FSM_A13
FSM_A14
FSM_A15FSM_A16
FSM_A17
FSM_A18FSM_A19
FSM_A20
FSM_A2
FSM_A3
FSM_A4
FSM_A21
FSM_A6
FSM_A7
FSM_A8
FSM_A1FSM_A5
FSM_D14
FSM_D3
FSM_D1
FSM_D4
FSM_D5
FSM_D10FSM_D11FSM_D13
SSRAM_ZZ
SSRAM_ADSCnSSRAM_ADSPn
SSRAM_CLK
SSRAM_ADVn
SSRAM_BWnSSRAM_GWn
SSRAM_Gn
SSRAM_E3nSSRAM_E2
SSRAM_FTn
SSRAM_BBnSSRAM_BAn
SSRAM_DQP1SSRAM_DQP0
SSRAM_LBOn
SSRAM_E1n
FSM_D15
FSM_D2
FSM_D0
FSM_D8
FSM_D7
FSM_D6
FSM_D9
FSM_D12
SSRAM_GWnSSRAM_ADVnSSRAM_ADSPn
SSRAM_ADSCn
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
FSM_D[15:0] 5,9,14,20
FLASH_RDYBSYn 7,14
FLASH_RESETn 7,14FLASH_WEn 7,14
FSM_A[25:1] 5,8,9,14,20
FLASH_OEn 9,14
FLASH_CEn 7,14FLASH_CLK 5,14FLASH_ADVn 7,14
SSRAM_BWn 9
SSRAM_ADSCn 7SSRAM_ADVn 7
SSRAM_CLK 7
SSRAM_ADSPn 7SSRAM_GWn 7,14
SSRAM_E1n 7
SSRAM_BAn 7SSRAM_BBn 9
SSRAM_Gn 9
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
13 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
13 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
13 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
SSRAM & FLASHFLASH 512Mb (32M X 16)
SSRAM INTERFACE
SHARED BUS
FLASH INTERFACE
PLACE NEAR FLASH
SSRAM
FLASH
assign ssram_gwn = 1'b1; // HIGH Global Write Enable—Writes all bytes; active low
assign ssram_advn = 1'b1; // HIGH
assign ssram_adscn = 1'b0; // LOW
assign ssram_adspn = 1'b1; // HIGH
C42
0.1uF
C42
0.1uF
R23 10KR23 10K
C12
0.1uF
C12
0.1uF
C34
0.1uF
C34
0.1uF
R17 1.00KR17 1.00K
R32 10KR32 10K
C14
0.1uF
C14
0.1uF
R22 1.00KR22 1.00K
C28
0.1uF
C28
0.1uF
R44 10KR44 10K
R15 10KR15 10K
C19
0.1uF
C19
0.1uF
R26 10KR26 10K
R45 1.00KR45 1.00K
C35
4.7nF
C35
4.7nF
R31 0R31 0
PC28FxxxP30B85FLASH
U6
PC28F512P30BF
PC28FxxxP30B85FLASH
U6
PC28F512P30BF
A1A1
A2B1
A3C1
A4D1
A5D2
A6A2
A7C2
A8A3
A9B3
A10C3
A11D3
A12C4
A13A5
A14B5
A15C5
A16D7
A17D8
A18A7
A19B7
A20C7
A21C8
A22A8
NC(64M)/A23G1
CE#B4
OE#F8
WE#G8
WP#C6
VCC A6
RESET#D4
VCC H3
D0 F2
D1 E2
D2 G3
D3 E4
D4 E5
D5 G5
D6 G6
D7 H7
D8 E1
D9 E3
D10 F3
D11 F4
D12 F5
D13 H5
D14 G7
D15 E7
WAIT F7
GND B2
GND H4GND H2
CLKE6
ADV#F6
RFU4 B8RFU3 E8RFU2 F1RFU1 G2RFU0 H1
NC(64M,128M)/A24H8
NC/A25(512M)B6
VPP A4
VCCQ D6VCCQ D5
VCCQ G4
GND H6
C20
0.1uF
C20
0.1uF
R14 1.00KR14 1.00K
C16
0.1uF
C16
0.1uF
C6
0.1uF
C6
0.1uF
R19 10KR19 10K
C32
0.1uF
C32
0.1uF
R24 10KR24 10K
R25 10KR25 10K
R47 10KR47 10K
C33
0.1uF
C33
0.1uF
C27
0.1uF
C27
0.1uF
R18 1.00KR18 1.00K
R21 1.00KR21 1.00K
C23
0.1uF
C23
0.1uF
U44
GS832018GT_TQFP100
U44
GS832018GT_TQFP100
A1999
E198
E297
E392
BA93
CLK89
DQ0 58
DQ1 59
DQ10 12
DQ11 13
DQ12 18
DQ13 19
DQ14 22
DQ15 23
A20100
NC3 3
VS
S5
NC5 7
NC6 16
NC7 25
NC8 28
NC9 29
VD
D15
VD
D41
VD
D65
VD
D91
DQ2 62
NC17 66
NC18 75
NC19 78
NC20 79
NC21 95
NC22 96
DQ3 63
DQ4 68
DQ5 69
DQ6 72
DQ7 73
DQ9 9
DQPA 74
DQPB 24
GWn88
NC11 38
NC12 51
NC13 52
NC14 53
NC1 1
VS
S10
NC10 30
NC4 6
NC2 2V
SS
17
VS
S21
VS
S26
VS
S40
VS
S55
VS
S60
VS
S67
VS
S71
VS
S76
VS
S90
ZZ64
A037
A136
A945
A1035
A1134
A1233
NC16 57
A1332
A1439
A1542
A1680
A1781
A246
A1882
A347
A448
A549
NC15 56
A650
A743
A844
ADSCn85
ADSPn84
ADVn83
BWn87
FTn14
LBOn31
DQ8 8
VD
DQ
4
VD
DQ
11
VD
DQ
20
VD
DQ
27
VD
DQ
54
VD
DQ
61
VD
DQ
70
VD
DQ
77
Gn86
BB94
R300
R300
C15
0.1uF
C15
0.1uF
C13
0.1uF
C13
0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
JTAG_TCKJTAG_FPGA_TDOJTAG_EPM2210_TDOJTAG_TMS
CLKIN_MAX_100
FLASH_RDYBSYn
FLASH_RESETnFLASH_WEn
FLASH_CLK
FLASH_OEn
FLASH_CEn
MAX_CSnMAX_OEnMAX_WEn
FPGA_DCLKFPGA_CONF_DONEFPGA_STATUSn
FPGA_DATA0
FPGA_CONFIGn
FLASH_ADVn
SENSE_SDISENSE_SCKSENSE_CSn
FPGA_DATA1
MAX_USERMAX_FACTORY
HSMA_PSNTnHSMB_PSNTn
FAN_CNTL
CLK125_ENCLKA_SCLCLKA_SDACLKA_EN
SENSE_SDO
USER_LED[7:0]CLKIN_MAX_100CLKIN_50
FPGA_DATA7
FPGA_DATA2FPGA_DATA3FPGA_DATA4FPGA_DATA5FPGA_DATA6
USER_LED0USER_LED1USER_LED2USER_LED3
USER_LED5USER_LED6USER_LED7
USER_LED4
SYS_RESETn
PGM_SELPGM_LOAD
MSEL0
MSEL3MSEL2
MSEL0
MSEL3
MSEL2
FSM_A9
FSM_A23
FSM_A25
FSM_A10
FSM_A11
FSM_A24
FSM_A15
FSM_A12
FSM_A14
FSM_A13
FSM_A6
FSM_A1
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A16
FSM_A7
FSM_A17
FSM_A19
FSM_A18
FSM_A20
FSM_A21
FSM_A22
FSM_D10
FSM_D11FSM_D14
FSM_D15
FSM_D12
FSM_D13
FSM_D1
FSM_D2
FSM_D3
FSM_D8FSM_D9
FSM_D0
FSM_D4
FSM_D5
FSM_D6
FSM_D7
FSM_A8
MAX_EPCSMAX_ERROR
MAX_FAN
USER_FACTORY
1.8V
1.8V1.8V
2.5V 2.5V
2.5V
1.8V
2.5V
PGM_SEL17
JTAG_EPM2210_TDO8
FPGA_CONF_DONE8,17FPGA_STATUSn8,18
FPGA_DCLK8
FPGA_CONFIGn8
FLASH_RDYBSYn7,13
FLASH_RESETn7,13FLASH_WEn7,13FLASH_OEn9,13
FLASH_CLK5,13FLASH_CEn7,13
MAX_CSn7MAX_OEn9MAX_WEn7
JTAG_FPGA_TDO8
PGM_LOAD17
MAX_FAN17MAX_ERROR17
MAX_USER17MAX_FACTORY17
FLASH_ADVn7,13
FSM_D[15:0]5,9,13,20
FSM_A[25:1]5,8,9,13,20
HSMA_PSNTn7,16HSMB_PSNTn7,16
JTAG_TMS8,16,18JTAG_TCK8,16,18
SENSE_SDI19SENSE_SCK19SENSE_CSn19
SENSE_SDO19
FPGA_DATA[7:0]8
CLK50_EN10CLKA_EN10CLKA_SCL10CLKA_SDA10
CLK125_EN10
SYS_RESETn8,17
MAX_CLK8
FAN_CNTL19
CLKIN_509,10
FAN_CNTL19
USER_LED[7:0] 7,8,9,17
MSEL0 8MSEL2 8MSEL3 8
MAX_EPCS17
USER_FACTORY19
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
14 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
14 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
14 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
MAX II
Place near MAX II
CLOCK INTERFACE
SHARED BUS
CONFIGURATION INTERFACE
FLASH INTERFACE
USER I/O's
CURRENT SENSE
USER INTERFACE
C216
0.1uF
C216
0.1uF
C70.01uF
C70.01uF
C173
0.1uF
C173
0.1uF
C4
0.01uF
C4
0.01uF
C198
0.1uF
C198
0.1uF
C191
0.1uF
C191
0.1uF
MAX IIBANK3
U7C
EPM2210GF256FBGA
MAX IIBANK3
U7C
EPM2210GF256FBGA
IOB3/GLCK2J12
IOB3/GCLK3H12
IOB3_103P14
IOB3_104N13
IOB3_105P15
IOB3_106M14
IOB3_107N14
IOB3_108M13
IOB3_109N15
IOB3_110L14
IOB3_111N16
IOB3_112L13
IOB3_113M15
IOB3_114L12
IOB3_115M16
IOB3_116L11
IOB3_117L15
IOB3_118K14
IOB3_119L16
IOB3_120K13
IOB3_121K15
IOB3_122K12
IOB3_123K16
IOB3_125J15
IOB3_126J14
IOB3_127 J16
IOB3_128 J13
IOB3_129 H16
IOB3_130 H13
IOB3_131 H15
IOB3_132 H14
IOB3_133 G16
IOB3_134 G12
IOB3_135 G15
IOB3_137 F16
IOB3_138 G13
IOB3_139 F15
IOB3_140 G14
IOB3_141 E16
IOB3_142 F11
IOB3_143 E15
IOB3_144 F12
IOB3_145 D16
IOB3_146 F13
IOB3_147 D15
IOB3_148 F14
IOB3_149 D14
IOB3_150 E12
IOB3_151 C15
IOB3_152 E13
IOB3_153 C14
IOB3_154 E14
IOB3_155 D13
C217
0.1uF
C217
0.1uF
C175
0.1uF
C175
0.1uF
R131.00KR131.00K
C199
0.1uF
C199
0.1uFC204
0.1uF
C204
0.1uF
C226
0.1uF
C226
0.1uF
MAX IIBANK1
U7A
EPM2210GF256FBGA
MAX IIBANK1
U7A
EPM2210GF256FBGA
IOB1_24H1
IOB1/GCLK0H5
IOB1/GCLK1J5
IOB1_1D3
IOB1_2C2
IOB1_3E3
IOB1_4C3
IOB1_5E4
IOB1_6D2
IOB1_7E5
IOB1_8D1
IOB1_9F3
IOB1_10E2
IOB1_11F4
IOB1_12E1
IOB1_13F5
IOB1_14F2
IOB1_15F6
IOB1_16F1
IOB1_17G3
IOB1_18G2
IOB1_19G4
IOB1_20G1
IOB1_21G5
IOB1_22H2
IOB1_25 H3
IOB1_26 J1
IOB1_27 H4
IOB1_28 J2
IOB1_29 J4
IOB1_30 K1
IOB1_31 J3
IOB1_32 K2
IOB1_34 L1
IOB1_35 K5
IOB1_36 L2
IOB1_37 K4
IOB1_38 M1
IOB1_39 K3
IOB1_40 M2
IOB1_41 L5
IOB1_42 M3
IOB1_43 L4
IOB1_44 N1
IOB1_45 L3
IOB1_46 N2
IOB1_47 M4
IOB1_48 N3
IOB1_49 P2
TMS N4TDO M5TDI L6
TCK P3
C84.7uFC84.7uF
C195
0.1uF
C195
0.1uFC174
0.1uF
C174
0.1uF
C165
0.1uF
C165
0.1uFC196
0.1uF
C196
0.1uF
C208
0.1uF
C208
0.1uF
C164
0.1uF
C164
0.1uF
MAX IIBANK4
U7D
EPM2210GF256FBGA
MAX IIBANK4
U7D
EPM2210GF256FBGA
IOB4/DEV_CLRnM9
IOB4/DEV_OEM8
IOB4_156P4
IOB4_157R1
IOB4_158P5
IOB4_159T2
IOB4_160N5
IOB4_161R3
IOB4_162P6
IOB4_163R4
IOB4_164N6
IOB4_165T4
IOB4_166M6
IOB4_167R5
IOB4_168P7
IOB4_169T5
IOB4_170N7
IOB4_171R6
IOB4_172M7
IOB4_173T6
IOB4_175R7
IOB4_176P8
IOB4_177T7
IOB4_178N8
IOB4_179R8
IOB4_180 N9
IOB4_181 T8
IOB4_182 T9
IOB4_183 R9
IOB4_184 P9
IOB4_185 T10
IOB4_187 R10
IOB4_188 M10
IOB4_189 T11
IOB4_190 N10
IOB4_191 R11
IOB4_192 P10
IOB4_193 T12
IOB4_194 M11
IOB4_195 R12
IOB4_196 N11
IOB4_197 T13
IOB4_198 P11
IOB4_199 R13
IOB4_200 M12
IOB4_201 R14
IOB4_202 N12
IOB4_203 T15
IOB4_204 P12
IOB4_205 R16
IOB4_206 P13
C197
0.1uF
C197
0.1uF
L1
BLM15AG221SN1
L1
BLM15AG221SN1
C163
0.1uF
C163
0.1uF
C206
0.1uF
C206
0.1uF
Y1
100MHz
Y1
100MHz
VCC 4
GND2 OUT 3
EN1
C207
0.1uF
C207
0.1uF
C227
0.1uF
C227
0.1uF
MAX IIBANK2
U7B
EPM2210GF256FBGA
MAX IIBANK2
U7B
EPM2210GF256FBGA
IOB2_50C13
IOB2_51B16
IOB2_52C12
IOB2_53A15
IOB2_54D12
IOB2_55B14
IOB2_56C11
IOB2_57B13
IOB2_58D11
IOB2_59A13
IOB2_60E11
IOB2_61B12
IOB2_62C10
IOB2_63A12
IOB2_64D10
IOB2_65B11
IOB2_66E10
IOB2_67A11
IOB2_69B10
IOB2_70C9
IOB2_71A10
IOB2_72D9
IOB2_73B9
IOB2_74 E9
IOB2_75 A9
IOB2_76 A8
IOB2_77 B8
IOB2_78 E8
IOB2_79 A7
IOB2_80 D8
IOB2_81 B7
IOB2_82 C8
IOB2_83 A6
IOB2_85 B6
IOB2_86 E7
IOB2_87 A5
IOB2_88 D7
IOB2_89 B5
IOB2_90 C7
IOB2_91 A4
IOB2_92 E6
IOB2_93 B4
IOB2_94 D6
IOB2_95 C4
IOB2_96 C6
IOB2_97 B3
IOB2_98 C5
IOB2_99 A2
IOB2_100 D5
IOB2_101 B1
IOB2_102 D4
MAX IIPower
U7E
EPM2210GF256FBGA
MAX IIPower
U7E
EPM2210GF256FBGA
GNDINTH7
GNDINTH9
GNDINTJ8
GNDINTJ10
GNDIOA1
GNDIOA16
GNDIOB2
GNDIOB15
GNDIOG7
GNDIOG8
GNDIOG9
GNDIOG10
GNDIOK7
GNDIOK8
GNDIOK9
GNDIOK10
GNDIOR2
GNDIOR15
GNDIOT1
GNDIOT16
VCCINT J9VCCINT J7VCCINT H10VCCINT H8
VCCIO1 C1
VCCIO1 H6
VCCIO1 J6
VCCIO1 P1
VCCIO2 A3
VCCIO2 A14
VCCIO2 F8
VCCIO2 F9
VCCIO3 C16
VCCIO3 H11
VCCIO3 J11
VCCIO3 P16
VCCIO4 L8
VCCIO4 L9
VCCIO4 T3
VCCIO4 T14
GNDINTG6 VCCINT K6
VCCINT F10
GNDINTF7
GNDINTK11 VCCINT G11VCCINT L7
GNDINTL10
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
MDI_P1MDI_N1MDI_P2MDI_N2MDI_P3MDI_N3
ENET_XTAL_25MHZ
MDI_N0MDI_P0
MDI_P1MDI_N1MDI_P2MDI_N2MDI_P3MDI_N3
MDI_N0MDI_P0
ENET_LED_LINK10
ENET_LED_LINK100
ENET_LED_LINK1000
ENET_LED_DUPLEX
ENET_T_RESETn
ENET_LED_LINK10
ENET_LED_TX
ENET_LED_LINK10
ENET_T_RESETn
ENET_LED_RX
ENET_LED_LINK1000ENET_LED_LINK100
ENET_LED_DUPLEX
ENET_LED_LINK10
ENET_LED_RX
ENET_LED_TX
ENET_RSET
ENET_LED_TX
ENET_LED_RX
ENET_XTAL_25MHZ
ENET_T_INTN
ENET_T_MDIO
ENET_T_RX_CLK
ENET_T_GTX_CLK
ENET_T_TX_D1
ENET_T_TX_D3
ENET_T_TX_D0
ENET_T_TX_D2
ENET_T_TX_EN
ENET_T_RX_D1
ENET_T_RX_D3
ENET_T_RX_D0
ENET_T_RX_D2
ENET_T_RX_DV
ENET_T_INTN
ENET_T_MDIOENET_T_MDC
ENET_T_MDC
ENET_T_MDIO
ENET_T_INTN
ENET_T_MDC
ENET_T_RESETnENET_RESETn
ENET_MDIO
ENET_INTN
ENET_MDC
1.1V 2.5V
2.5V
2.5V
2.5V
3.3V
3.3V
1.1V
2.5V
2.5V
1.8V
1.8V
2.5V
2.5V
ENET_T_RX_CLK9
ENET_RESETn7
ENET_MDIO9
ENET_T_RX_DV7
ENET_INTn7
ENET_T_GTX_CLK7
ENET_T_TX_D[3:0]7
ENET_T_RX_D[3:0]7
ENET_T_TX_EN7
ENET_MDC7
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
15 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
15 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
15 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
10/100/1000 Ethernet
Place near PHY
RGMII Mode (default)
removed ENET_LED_ACTIVITY with r445 and D6
removed ENET_RX_CRS and ENET_RX_COL signals
removed ENET_TX_CLK signal, Atached to ground
removed ENET_CRS
ETHERNET CONTROL INTERFACE
ETHERNET RGMII INTERFACE
C382
0.1uF
C382
0.1uF
U9
MAX3373
U9
MAX3373
VCCIO2 1
GND 2
VL3
VL_IO24VL_IO15 VCCIO1 8
VCC 7
TRI_STATE6
R80 49.9R80 49.9
C71
0.1uF
C71
0.1uF
C83
0.1uF
C83
0.1uF
D24Green_LEDD24Green_LED
R263 220R263 220
D26Green_LEDD26Green_LED
R265 220R265 220
R58 49.9R58 49.9
C360
0.1uF
C360
0.1uF
D31Green_LEDD31Green_LED
GMII/MII/TBI INTERFACE
TEST
SGMII INTERFACE
JTAG
MDI INTERFACE
MGMT
U21A
88E1111
GMII/MII/TBI INTERFACE
TEST
SGMII INTERFACE
JTAG
MDI INTERFACE
MGMT
U21A
88E1111
COMA27
RESET_N28
CONFIG658CONFIG559CONFIG460CONFIG361CONFIG263CONFIG164CONFIG065
125CLK22
XTAL155
XTAL254
VSSC53
RSET30
SEL_FREQ56
MDI3_P42
MDI3_N43
MDI2_P39
MDI2_N41
MDI1_P33
MDI1_N34
MDI0_P29
MDI0_N31
MDIO24
MDC25
INT_N23
HSDAC_P37
HSDAC_N38
GTX_CLK 8
TX_CLK 4
TX_EN 9
RXCLK 2
RX_DV 94
CRS 84
COL 83
S_CLK_P 79
S_CLK_N 80
S_IN_P 82
S_IN_N 81
S_OUT_P 77
S_OUT_N 75
LED_TX 68
LED_RX 69
LED_DUPLEX 70
LED_LINK1000 73
LED_LINK100 74
LED_LINK10 76
RXD0 95
RXD1 92
RXD2 93
RXD3 91
RXD4 90
RXD5 89
RXD6 87
RXD7 86
RX_ER 3
TXD0 11
TXD1 12
TXD2 14
TXD3 16
TXD4 17
TXD5 18
TXD6 19
TXD7 20
TX_ER 7
TMS46TDO50TDI44TCK49TRST_N47
D27Green_LEDD27Green_LED
R57 49.9R57 49.9
U14
MAX3373
U14
MAX3373
VCCIO2 1
GND 2
VL3
VL_IO24VL_IO15 VCCIO1 8
VCC 7
TRI_STATE6
R60 49.9R60 49.9
C74
0.1uF
C74
0.1uF
C97
0.1uF
C97
0.1uF
C68 0.01uFC68 0.01uF
C98
0.1uF
C98
0.1uF
C105 0.01uFC105 0.01uF
C67 0.01uFC67 0.01uF
R264 220R264 220
C82
0.1uF
C82
0.1uF
R81 49.9R81 49.9
C73
0.1uF
C73
0.1uF
R76
10.0K
R76
10.0K
D25Green_LEDD25Green_LED
C91
0.1uF
C91
0.1uF
R82 49.9R82 49.9
X5
25MHz
X5
25MHz
EN1
NC12
GND3
OUT 4
NC2 5
VCC 6
J7
HFJ11-1G02E
J7
HFJ11-1G02E
TD0_P 1
TD0_N 2
TD1_P 3
TD1_N 6
TD2_P 4
TD2_N 5
TD3_P 7
TD3_N 8
VCC 9
GND 10
GN
D_T
AB
11
GN
D_T
AB
12
R261 220R261 220
C72
0.1uF
C72
0.1uF
D30Green_LEDD30Green_LED
R62 4.7KR62 4.7K
R266 220R266 220
R63 4.7KR63 4.7K
U21B
88E1111
U21B
88E1111
NC113
VSS97
DVDD 1
DVDD 6
DVDD 10
DVDD 15
DVDD 57
DVDD 62
DVDD 67
DVDD 71
DVDD 85
AVDD32
AVDD36
AVDD35
AVDD40
AVDD45
AVDD78
VD
DO
X26
VD
DO
X48
VD
DO
5
VD
DO
21
VD
DO
88
VD
DO
96
VD
DO
H72
VD
DO
H66
VD
DO
H52
NC251
C361
0.1uF
C361
0.1uF
C104 0.01uFC104 0.01uF
R66
4.99K
R66
4.99K
C87
0.1uF
C87
0.1uF
R59 49.9R59 49.9
R71
4.7K
R71
4.7K
R64 4.7KR64 4.7K
R61 4.7KR61 4.7K
R83 49.9R83 49.9
R262 220R262 220
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
HSMA_PSNTnHSMB_PSNTn
HSMA_RX_D_P0HSMA_RX_D_N0
HSMA_RX_D_P1HSMA_RX_D_N1
HSMA_RX_D_P2HSMA_RX_D_N2
HSMA_RX_D_P3HSMA_RX_D_N3
HSMA_RX_D_P4HSMA_RX_D_N4
HSMA_RX_D_P5HSMA_RX_D_N5
HSMA_RX_D_P6HSMA_RX_D_N6
HSMA_RX_D_P7HSMA_RX_D_N7
HSMA_CLK_IN_P1HSMA_CLK_IN_N1
HSMA_RX_D_P8HSMA_RX_D_N8
HSMA_RX_D_P9HSMA_RX_D_N9
HSMA_RX_D_P10HSMA_RX_D_N10
HSMA_RX_D_P11HSMA_RX_D_N11
HSMA_RX_D_P12HSMA_RX_D_N12
HSMA_RX_D_P13HSMA_RX_D_N13
HSMA_RX_D_P14HSMA_RX_D_N14
HSMA_RX_D_P15HSMA_RX_D_N15
HSMA_RX_D_P16HSMA_RX_D_N16
HSMA_CLK_IN_P2HSMA_CLK_IN_N2HSMA_PSNTn
HSMA_TX_D_P0HSMA_TX_D_N0
HSMA_TX_D_P1HSMA_TX_D_N1
HSMA_TX_D_P2HSMA_TX_D_N2
HSMA_TX_D_P3HSMA_TX_D_N3
HSMA_TX_D_P4HSMA_TX_D_N4
HSMA_TX_D_P5HSMA_TX_D_N5
HSMA_TX_D_P6HSMA_TX_D_N6
HSMA_TX_D_P7HSMA_TX_D_N7
HSMA_CLK_OUT_P1HSMA_CLK_OUT_N1
HSMA_TX_D_P8HSMA_TX_D_N8
HSMA_TX_D_P9HSMA_TX_D_N9
HSMA_TX_D_P10HSMA_TX_D_N10
HSMA_TX_D_P11HSMA_TX_D_N11
HSMA_TX_D_P12HSMA_TX_D_N12
HSMA_TX_D_P13HSMA_TX_D_N13
HSMA_TX_D_P14HSMA_TX_D_N14
HSMA_TX_D_P15HSMA_TX_D_N15
HSMA_TX_D_P16HSMA_TX_D_N16
HSMA_CLK_OUT_P2HSMA_CLK_OUT_N2
HSMA_CLK_IN0HSMA_JTAG_TDIJTAG_TMS
HSMA_CLK_OUT0HSMA_JTAG_TDOJTAG_TCK
HSMB_TX_D_P0HSMB_TX_D_N0
HSMB_CLK_OUT_P1HSMB_CLK_OUT_N1
HSMB_CLK_OUT_N2
HSMB_D0HSMB_D2
HSMB_CLK_IN_P1HSMB_CLK_IN_N1
HSMB_CLK_IN_N2
HSMB_D1HSMB_D3
HSMB_PSNTn
HSMB_JTAG_TDOJTAG_TCK
HSMB_CLK_OUT0HSMB_JTAG_TDIJTAG_TMS
HSMB_CLK_IN0
HSMA_TX_CN1HSMA_TX_CP1
HSMA_TX_CN0HSMA_TX_CP0
HSMA_TX_CN3HSMA_TX_CP3
HSMA_TX_CN2HSMA_TX_CP2
HSMA_TX_N1HSMA_TX_P1
HSMA_TX_N0HSMA_TX_P0
HSMA_TX_N3HSMA_TX_P3
HSMA_TX_N2HSMA_TX_P2
HSMB_RX_N1HSMB_RX_P1
HSMB_RX_N0HSMB_RX_P0
HSMB_RX_N3HSMB_RX_P3
HSMB_RX_N2HSMB_RX_P2
HSMA_RX_N1HSMA_RX_P1
HSMA_RX_N0HSMA_RX_P0
HSMA_RX_N3HSMA_RX_P3
HSMA_RX_N2HSMA_RX_P2
HSMB_TX_N1HSMB_TX_P1
HSMB_TX_N0HSMB_TX_P0
HSMB_TX_N3
HSMB_TX_N2HSMB_TX_P2
HSMB_TX_P3
HSMA_D[3:0]
HSMA_D3
HSMB_T_SCL
HSMA_D2HSMA_D1HSMA_D0
HSMB_TX_D_N2HSMB_TX_D_P2
HSMB_TX_D_N1HSMB_TX_D_P1
HSMB_TX_D_N5HSMB_TX_D_P5
HSMB_TX_D_N4
HSMB_TX_D_N3HSMB_TX_D_P3
HSMB_TX_D_P4
HSMB_RX_D_P3HSMB_RX_D_N3
HSMB_RX_D_N0HSMB_RX_D_P0
HSMB_RX_D_P2HSMB_RX_D_N2
HSMB_RX_D_N4HSMB_RX_D_P4
HSMB_RX_D_N1HSMB_RX_D_P1
HSMB_T_SCLHSMB_T_SDA
HSMA_T_SDAHSMA_T_SCL
HSMA_T_SDA HSMA_T_SCL HSMB_T_SDA
HSMBT_CLK_IN_P2
HSMB_RX_D_N5HSMB_RX_D_P5
3.3V3.3V
12V_HSMC 3.3V
12V_HSMC
12V_HSMC 3.3V
3.3V 12V_HSMC3.3V
HSMB_CLK_OUT06
HSMB_CLK_IN09
HSMB_D[3:0]6
HSMB_TX_D_P[5:0]6,8
HSMB_TX_D_N[5:0]6,20
HSMB_RX_D_P[5:0]6
HSMB_RX_D_N[5:0]6
HSMB_CLK_OUT_P[2:1]5,6,9
HSMB_CLK_OUT_N[2:1]6
HSMB_CLK_IN_N[2:1]6
HSMB_PSNTn7,14
JTAG_TCK8,14,18
JTAG_TMS8,14,18
HSMA_JTAG_TDI8
HSMB_JTAG_TDI8
HSMA_JTAG_TDO8HSMB_JTAG_TDO8
HSMA_RX_P[3:0]4
HSMA_TX_P[3:0]4
HSMA_TX_N[3:0]4
HSMA_RX_N[3:0]4
HSMB_TX_N[3:0]4
HSMB_RX_N[3:0]4
HSMB_RX_P[3:0]4
HSMB_TX_P[3:0]4
HSMA_CLK_OUT06HSMA_CLK_IN09
HSMA_TX_D_P[16:0]6
HSMA_TX_D_N[16:0]6
HSMA_RX_D_P[16:0]6
HSMA_RX_D_N[16:0]6
HSMA_CLK_OUT_P[2:1]6
HSMA_CLK_OUT_N[2:1]6
HSMA_CLK_IN_N[2:1]9
HSMA_CLK_IN_P[2:1]9
HSMA_PSNTn7,14
HSMA_D[3:0] 6
HSMB_T_TX_D_P15 5
HSMB_T_TX_D_N14 5
HSMB_TX_D_P165,9HSMB_TX_D_N165
HSMB_T_TX_D_P11 7
HSMB_T_TX_D_P12 5
HSMB_T_TX_D_P13 7
HSMB_T_TX_D_N12 7
HSMB_T_TX_D_N13 5
HSMB_T_TX_D_N11 7
HSMB_T_TX_D_N6 5
HSMB_T_TX_D_P8 5
HSMB_T_TX_D_P7 5
HSMB_T_TX_D_P9 5
HSMB_T_TX_D_N10 5HSMB_T_TX_D_P10 5
HSMB_T_TX_D_N8 5
HSMB_T_TX_D_P6 5
HSMB_T_RX_D_P137
HSMB_T_RX_D_P147
HSMB_T_RX_D_P157
HSMB_T_RX_D_N145
HSMB_T_RX_D_P167HSMB_T_RX_D_N165
HSMB_T_RX_D_N157
HSMB_T_RX_D_N137
HSMB_T_RX_D_N65
HSMB_T_RX_D_N105HSMB_T_RX_D_P105
HSMB_T_RX_D_N115
HSMB_T_RX_D_N125HSMB_T_RX_D_P125
HSMB_T_RX_D_P115
HSMB_T_RX_D_P65
HSMB_T_SDA 7HSMB_T_SCL 7
HSMA_T_SDA 7HSMA_T_SCL 7
HSMB_T_RX_D_P75
HSMB_T_RX_D_N85HSMB_T_RX_D_P85
HSMB_T_RX_D_P95HSMB_T_RX_D_N95
HSMB_T_RX_D_N75
HSMB_T_TX_D_P16 5
HSMB_T_TX_D_P14 5
HSMB_T_TX_D_N7 5
HSMB_T_CLK_OUT_P2 9
HSMB_T_TX_D_N16 5
HSMB_T_TX_D_N15 7
HSMBT_CLK_IN_P2 5
HSMB_TX_D_N9 6
HSMB_CLK_IN_P16
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
16 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
16 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
16 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
High Speed Mezzanine (HSM) Interface
HSMC PORT A
A
HSMC PORT B
HSMC JTAG INTERFACE
B
C114
10uF
C114
10uF
BANK 1
BANK 2
BANK 3
J2
ASP-122953-01
BANK 1
BANK 2
BANK 3
J2
ASP-122953-01
11
33
55
77
99
1111
1313
1515
1717
1919
2121
2323
2525
2727
2929
3131
3333
3535
3737
3939
4141
4343
3.3V45
4747
4949
3.3V51
5353
5555
3.3V57
5959
6161
3.3V63
6565
6767
3.3V69
7171
7373
3.3V75
7777
7979
3.3V81
8383
8585
3.3V87
8989
9191
3.3V93
9595
9797
3.3V99
101101
103103
3.3V105
107107
109109
3.3V111
113113
115115
3.3V117
119119
2 2
4 4
6 6
8 8
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
42 42
44 44
12V 46
48 48
50 50
12V 52
54 54
56 56
12V 58
60 60
62 62
12V 64
66 66
68 68
12V 70
72 72
74 74
12V 76
78 78
80 80
12V 82
84 84
86 86
12V 88
90 90
92 92
12V 94
96 96
98 98
12V 100
102 102
104 104
12V 106
108 108
110 110
12V 112
114 114
116 116
12V 118
120 120
GN
D_1_1
161
GN
D_1_2
162
GN
D_1_3
163
GN
D_1_4
164
GN
D_2_1
165
GN
D_2_2
166
GN
D_2_3
167
GN
D_3_1
169
GN
D_2_4
168
GN
D_3_2
170
GN
D_3_3
171
GN
D_3_4
172
121121
3.3V123
125125
127127
3.3V129
131131
133133
3.3V135
137137
139139
3.3V141
143143
145145
3.3V147
149149
151151
3.3V153
155155
157157
3.3V159
122 122
12V 124
126 126
128 128
12V 130
132 132
134 134
12V 136
138 138
140 140
12V 142
144 144
146 146
12V 148
150 150
152 152
12V 154
156 156
158 158
PSNTn 160
D2Green_LEDD2Green_LED
R37 0R37 0R41 0R41 0
R1 56.2R1 56.2
D1Green_LEDD1Green_LED
R42 0R42 0R38 0R38 0
R2 56.2R2 56.2
C112
10uF
C112
10uF
C111
10uF
C111
10uF
R35 0R35 0
R43 0R43 0
BANK 1
BANK 2
BANK 3
J1
ASP-122953-01
BANK 1
BANK 2
BANK 3
J1
ASP-122953-01
11
33
55
77
99
1111
1313
1515
1717
1919
2121
2323
2525
2727
2929
3131
3333
3535
3737
3939
4141
4343
3.3V45
4747
4949
3.3V51
5353
5555
3.3V57
5959
6161
3.3V63
6565
6767
3.3V69
7171
7373
3.3V75
7777
7979
3.3V81
8383
8585
3.3V87
8989
9191
3.3V93
9595
9797
3.3V99
101101
103103
3.3V105
107107
109109
3.3V111
113113
115115
3.3V117
119119
2 2
4 4
6 6
8 8
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
42 42
44 44
12V 46
48 48
50 50
12V 52
54 54
56 56
12V 58
60 60
62 62
12V 64
66 66
68 68
12V 70
72 72
74 74
12V 76
78 78
80 80
12V 82
84 84
86 86
12V 88
90 90
92 92
12V 94
96 96
98 98
12V 100
102 102
104 104
12V 106
108 108
110 110
12V 112
114 114
116 116
12V 118
120 120
GN
D_1_1
161
GN
D_1_2
162
GN
D_1_3
163
GN
D_1_4
164
GN
D_2_1
165
GN
D_2_2
166
GN
D_2_3
167
GN
D_3_1
169
GN
D_2_4
168
GN
D_3_2
170
GN
D_3_3
171
GN
D_3_4
172
121121
3.3V123
125125
127127
3.3V129
131131
133133
3.3V135
137137
139139
3.3V141
143143
145145
3.3V147
149149
151151
3.3V153
155155
157157
3.3V159
122 122
12V 124
126 126
128 128
12V 130
132 132
134 134
12V 136
138 138
140 140
12V 142
144 144
146 146
12V 148
150 150
152 152
12V 154
156 156
158 158
PSNTn 160
C113
10uF
C113
10uF
R40 0R40 0R36 0R36 0
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FPGA_CONF_DONE
RESn_LED0USER_LED0
RESn_LED1
RESn_LED2
RESn_LED3
USER_PB[3:0]
PGM_SELSYS_RESETn
USER_DIPSW[7:0]
FPGA_CONF_DONE
RESn_HSMA_RX_LEDHSMA_RX_LED
HSMA_TX_LED RESn_HSMA_TX_LED
HSMB_RX_LED RESn_HSMB_RX_LED
HSMB_TX_LED RESn_HSMB_TX_LED
HSMB_RX_LEDHSMB_TX_LED
HSMA_RX_LEDHSMA_TX_LED
USER_LED1
USER_LED2
USER_LED3
PGM_LOAD
MAX_FACTORY
MAX_USER
RES_MAX_FACTORY
RES_MAX_USER
MAX_FACTORYMAX_USER
MAX_FANMAX_ERROR
USER_LED[7:0]
CPU_RESETn
LCD_T_DATA1LCD_T_DATA2 LCD_T_DATA3
LCD_T_D_Cn
LCD_T_DATA5LCD_T_DATA6 LCD_T_DATA7
LCD_T_WEnLCD_T_DATA0
LCD_T_CSn
USER_DIPSW5
USER_DIPSW1
USER_DIPSW7
USER_DIPSW0
USER_DIPSW2
USER_DIPSW4USER_DIPSW3
USER_DIPSW6
RESn_LED4USER_LED4
RESn_LED5USER_LED5
RESn_LED6USER_LED6
RESn_LED7USER_LED7
PGM_SEL
SYS_RESETn
PGM_LOAD
CPU_RESETn
USER_PB0
USER_PB1
USER_PB2
USER_PB3
LCD_T_D_Cn LCD_D_Cn
RESn_PCIEX1
RESn_PCIEX4
PCIE_LED_X1
PCIE_LED_X4LCD_DATA1
LCD_CSnLCD_WEn
LCD_DATA0
LCD_T_CSnLCD_T_WEn
LCD_T_DATA0LCD_T_DATA1
LCD_DATA1
LCD_CSnLCD_WEnLCD_DATA0
MAX_EPCS
MAX_FAN RES_MAX_FAN
RES_MAX_ERRORMAX_ERROR
MAX_EPCS RES_MAX_EPCS
2.5V
5.0V
2.5V
2.5V
1.8V2.5V
1.8V2.5V
1.8V
2.5V2.5V
2.5V
1.8V
2.5V1.8V
1.8V
USER_PB[3:0] 7
USER_DIPSW[7:0] 7,20
FPGA_CONF_DONE 8,14
PGM_SEL 14SYS_RESETn 8,14
HSMA_RX_LED 7
HSMB_RX_LED 7HSMA_TX_LED 7
HSMB_TX_LED 7
PGM_LOAD 14
MAX_ERROR 14MAX_FAN 14MAX_FACTORY 14MAX_USER 14
USER_LED[7:0] 7,8,9,14
CPU_RESETn 7
LCD_D_Cn7
LCD_DATA4 9
LCD_T_DATA[7:5]7
LCD_T_DATA[3:2]7
PCIE_LED_X1 7
PCIE_LED_X4 7
LCD_WEn 7LCD_DATA0 7LCD_DATA1 7
LCD_CSn 7
MAX_EPCS 14
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
17 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
17 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
17 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
User IO & Connector
USER I/O's
HSMC INTERFACE
2 x 16 Display ConnectorUSER DIPSWITCH
ON = 0OFF = 1
Inputoutput
LCD DISPLAY INTERFACE
R4 10.0KR4 10.0K
C103
0.1uF
C103
0.1uF
S4
PB Switch
S4
PB Switch
1 32 4
RN1H 10KRN1H 10K8 9
R103 56.2R103 56.2
R11 10.0KR11 10.0K
R5 10.0KR5 10.0K
R7756.2
R7756.2
D21
Green_LED
D21
Green_LED
B3
2x7 HDR
B3
2x7 HDR
R7856.2
R7856.2
C377
0.1uF
C377
0.1uF
RN1F 10KRN1F 10K6 11
S7
PB Switch
S7
PB Switch
1 32 4
D14
Green_LED
D14
Green_LED
C102
0.1uF
C102
0.1uF
C366
0.1uF
C366
0.1uF
RN1D 10KRN1D 10K4 13
SPACER2
MSPM-7-01
SPACER2
MSPM-7-01
D18
Red_LED
D18
Red_LED
D4
Green_LED
D4
Green_LED
R120 56.2R120 56.2
RN1B 10KRN1B 10K2 15
D5
Green_LED
D5
Green_LED
S2
PB Switch
S2
PB Switch
1 32 4
D13
Green_LED
D13
Green_LED
R9 10.0KR9 10.0K
D8
Green_LED
D8
Green_LED
R106 10.0KR106 10.0K
R113 56.2R113 56.2
D7
Green_LED
D7
Green_LED
D16
Green_LED
D16
Green_LED
U27
MAX3373
U27
MAX3373
VCCIO2 1
GND 2
VL3
VL_IO24VL_IO15 VCCIO1 8
VCC 7
TRI_STATE6
D12
Green_LED
D12
Green_LED
R104 56.2R104 56.2
S8
PB Switch
S8
PB Switch
1 32 4
D9
Green_LED
D9
Green_LED
C99
0.1uF
C99
0.1uF
R122 56.2R122 56.2
B4
LCM-S01602DSR/C
B4
LCM-S01602DSR/C
D3
Green_LED
D3
Green_LED
R121 56.2R121 56.2
D29
Green_LED
D29
Green_LED
R119 56.2R119 56.2
SW2
TDA08H0SB1
SW2
TDA08H0SB1
12345678
161514131211109
U23
SN74AVC1T45
U23
SN74AVC1T45
GND2
VCCA1
A3 B 4
DIR 5
VCCB 6
D28
Green_LED
D28
Green_LED
R133 56.2R133 56.2
RN1G 10KRN1G 10K7 10
RN1E 10KRN1E 10K5 12
R131 56.2R131 56.2
D17
Red_LED
D17
Red_LED
R134 56.2R134 56.2
D15
Green_LED
D15
Green_LED
D19
Green_LED
D19
Green_LED
RN1C 10KRN1C 10K3 14
R7 10.0KR7 10.0K
S1
PB Switch
S1
PB Switch
1 32 4
RN1A 10KRN1A 10K1 16
R115 56.2R115 56.2
R116 56.2R116 56.2
C100
0.1uF
C100
0.1uF
R132 100, 1%R132 100, 1%
J13
HDR2X7
J13
HDR2X7
11
33
55
77
99
1111
1313
2 2
4 4
6 6
8 8
10 10
12 12
14 14
S5
PB Switch
S5
PB Switch
1 32 4
D20
Green_LED
D20
Green_LED
S3
PB Switch
S3
PB Switch
1 32 4
R10 10.0KR10 10.0K
D10
Green_LED
D10
Green_LED
D6
Green_LED
D6
Green_LED
U24
MAX3373
U24
MAX3373
VCCIO2 1
GND 2
VL3
VL_IO24VL_IO15 VCCIO1 8
VCC 7
TRI_STATE6
S6
PB Switch
S6
PB Switch
1 32 4
R105 56.2R105 56.2
R102 56.2R102 56.2
SPACER1
MSPM-7-01
SPACER1
MSPM-7-01
R6 10.0KR6 10.0K
R130 56.2R130 56.2
R114 56.2R114 56.2
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
USB_D1
USB_SI_WU
USB_RESETn
USB_XTAL2USB_XTAL1
USB_D0
USB_XTAL1
USB_XTAL2
USB_PWR_ENn
USB_EEDATA
USB_RDnUSB_WR
USB_TXEnUSB_RXFn
USB_EECSUSB_EESKEEDATA
USB_D2USB_D3USB_D4USB_D5USB_D6USB_D7
USB_MAX_TDOUSB_MAX_TMS
USB_MAX_TCK
USB_MAX_TDICLKIN_24MHZ
USB_RDn
USB_D2USB_D3USB_D4
USB_D7
USB_D5USB_D6
USB_RXFn
USB_TXEn
USB_WR
JTAG_TMSJTAG_BLASTER_TDI
USB_LEDJTAG_BLASTER_TDO
USB_MAX_TCKUSB_MAX_TDIUSB_MAX_TDOUSB_MAX_TMS
USB_SI_WU
USB_EESK
CLKIN_24MHZ
USB_D0
JTAG_TCK
USB_D1
FPGA_CEn
FPGA_STATUSn
USB_EECS
EEDATA
USB_DISABLEn
USB_PWR_ENn
USB_RESETn
2.5V_USB
5V_USB5V_USB
5V_USB
5V_USB
5V_USB
5V_USB
2.5V_USB
2.5V_USB2.5V_USB2.5V_USB2.5V_USB
2.5V_USB
2.5V_USB
2.5V_USB
JTAG_BLASTER_TDO8
USB_DISABLEn3,8
JTAG_TMS8,14,16JTAG_BLASTER_TDI8
JTAG_TCK8,14,16
FPGA_STATUSn8,14FPGA_CEn8
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
18 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
18 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
18 1Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Embedded USB Blaster
DECOUPLING CAPS
USB
PLACE NEAR MAX II
MAXII USB INTERFACE
R151 10.0KR151 10.0K
C34.7uFC34.7uF
C152
0.1uF
C152
0.1uF
MAX IIPower
U3C
EPM240M100
MAX IIPower
U3C
EPM240M100
GNDIOD5
GNDIOD7
GNDIOE4
GNDIOE8
GNDIOG4
GNDIOG8
GNDIOH5
GNDIOH7
VCCINT G3VCCINT E9
VCCIO1 E3
VCCIO1 J4
VCCIO1 J8
VCCIO2 C4
VCCIO2 C8
VCCIO2 G9
R29 27R29 27
C21
0.01uF
C21
0.01uFC25
0.01uFC25
0.01uF
R183 10.0KR183 10.0K
U4
FT245BL
U4
FT245BL
D0 25
D1 24
D2 23
D3 22
D4 21
D5 20
D6 19RSTOUT#5
XTOUT28
RESET#4
EECS32
EESK1
EEDATA2
AG
ND
29
GN
D1
9
D7 18
GN
D2
17
TEST31
TXE# 14
WR 15RD# 16
RXF# 12
PWREN# 10
VC
C-I
O13
3V3OUT6
AV
CC
30
VC
C2
26
VC
C1
3
USBDM8
USBDP7
XTIN27
SI/WU 11
C153
0.1uF
C153
0.1uF
C185
33nF
C185
33nF
C150
0.1uF
C150
0.1uF
C168
0.1uF
C168
0.1uF
D22
Green_LED
D22
Green_LED
R182
2.2K
R182
2.2K
J4USB CONJ4USB CON
1234
5
6
R149470R149470
C149
0.1uF
C149
0.1uF
X1
24MHz
X1
24MHz
VCC 4
GND2 OUT 3
EN1
Y2
6.000MHz
Y2
6.000MHz
12
R158
1.00k
R158
1.00k
R108 1.00KR108 1.00K
U11
SN65220DBV
U11
SN65220DBV
NC11
NC23
GND2B 4A 6
GND 5
C167
10uF
C167
10uF
L7
BLM21PG331SN1
L7
BLM21PG331SN1
MAX IIBANK1
U3A
EPM240M100
MAX IIBANK1
U3A
EPM240M100
IOB1_23 K7
IOB1_24 K9
IOB1/CLK0F2
IOB1/CLK1E1
IOB1_1B1
IOB1_2C1
IOB1_3C2
IOB1_4D1
IOB1_5D2
IOB1_6D3
IOB1_7E2
IOB1_8F1
IOB1_9F3
IOB1_10G1
IOB1_11G2
IOB1_12H1
IOB1_13H2
IOB1_14H3
IOB1_15J5
IOB1_16J6
IOB1_17 J7
IOB1_18 K10
IOB1_19 K3
IOB1_20 K4
IOB1_21 K5
IOB1_22 K6
IOB1_25 L1
IOB1_26 L10
IOB1_27 L11
IOB1_28 L2
IOB1_29 L3
IOB1_30 L4
IOB1_31 L5
IOB1_32 L6
IOB1_33 L7
IOB1_34 L9
TMS J1TDO K2TDI J2
TCK K1
IOB1/DEV_OEL8IOB1/DEV_CLRnK8
J15
DNI
J15
DNI
11
33
55
77
2 2
4 4
6 6
8 8
99 10 10
MAX IIBANK2
U3B
EPM240M100
MAX IIBANK2
U3B
EPM240M100
IOB2_35A1
IOB2_36A10
IOB2_37A11
IOB2_38A2
IOB2_39A3
IOB2_40A4
IOB2_41A5
IOB2_42A6
IOB2_43A7
IOB2_44A8
IOB2_45A9
IOB2_46B10
IOB2_47B11
IOB2_48B2
IOB2_49B3
IOB2_50B4
IOB2_51 B5
IOB2_52 B6
IOB2_53 B7
IOB2_54 B8
IOB2_55 B9
IOB2_56 C10
IOB2_57 C11
IOB2_58 C5
IOB2_59 C6
IOB2_60 C7
IOB2_61 D10
IOB2_62 D11
IOB2_63 D9
IOB2_64 E10
IOB2_65 E11
IOB2_66 F11
IOB2_67 F9
IOB2_68 G10
IOB2_69 H10
IOB2_70 H11
IOB2_71 H9
IOB2_72 J10
IOB2_73 J11
IOB2_74 K11IOB2/CLK2F10
IOB2/CLK3G11
C154 18pFC154 18pF
R27 1.5KR27 1.5K
C169
0.1uF
C169
0.1uFR107 1.00KR107 1.00K
U5
AT93C46DN-SH-B
U5
AT93C46DN-SH-B
CS1
SK2
DIN3
DOUT4
VCC 8
NC1 7
NC2 6
GND 5
R48 27R48 27
C5110uFC5110uF
R1250 R1250
C184
0.1uF
C184
0.1uF
C186
0.1uF
C186
0.1uF
R1400 R1400
C151
0.1uF
C151
0.1uF
R192
56.2
R192
56.2
C170 18pFC170 18pF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
SENSE5_CSnSENSE5_SCKSENSE5_SDISENSE5_SDO
1.2V_VCCL_GXB_N
1.2V_VCCL_GXB_P
1.8V_B3_B4_N
1.8V_B3_B4_P
1.8V_B7_B8_N
1.8V_B7_B8_P
2.5V_B5_B6_N
2.5V_B5_B6_P
VCCA_N
VCCA_P
VCCD_PLL_N
VCCD_PLL_P
VCC_N
VCC_P
2.5V_VCCA_VCCH_GXB_N
2.5V_VCCA_VCCH_GXB_P
1.8V_B3_B4_N1.8V_B3_B4_P
2.5V_VCCA_VCCH_GXB_N2.5V_VCCA_VCCH_GXB_P
VCCD_PLL_NVCCD_PLL_P
2.5V_B5_B6_N2.5V_B5_B6_P
VCCA_NVCCA_P
1.8V_B7_B8_N1.8V_B7_B8_P
VCC_NVCC_P
1.2V_VCCL_GXB_N1.2V_VCCL_GXB_P
5V_MONITOR
5.0V 2.5V
2.5V
12V
5.0V
5V_MONITOR12V
2.5V
1.2V
2.5V_B5_B6
1.8V_B3_B4
2.5V_VCCA_VCCH_GXB
VCCD_PLL
1.2V
VCC
1.8V_FPGA
1.8V_B7_B8
FAN_CNTL14
VCCA_SNS 21
VCCL_SNS 21
SENSE_CSn14SENSE_SCK14
SENSE_SDO14SENSE_SDI14
2.5V_B5_B6_POS 23
1.8V_B3_B4_SNS 23
VCCA_VCCH_SNS 21
VCCD_PLL_SNS 21
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
19 25Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
19 25Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
19 25Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Power Monitor
REF=5.0V
Fan Power Header
A/D #0
R52590KR52590K
V58
SENSE_PAD
V58
SENSE_PAD
RSNS1 SNS 2
C53
10uF
C53
10uF
R202 10.0KR202 10.0K
V1
SENSE_PAD
V1
SENSE_PAD
RSNS1 SNS 2
V54
SENSE_PAD
V54
SENSE_PAD
RSNS1 SNS 2
V56
SENSE_PAD
V56
SENSE_PAD
RSNS1 SNS 2
R2110 R2110
V57
SENSE_PAD
V57
SENSE_PAD
RSNS1 SNS 2
U12
MAX3378
U12
MAX3378
VL 1
IO VL1 2
IO VL2 3
IO VL3 4
IO VL4 5
NC1 6
GND 7
VCC14
IO VCC113
IO VCC212
IO VCC311
IO VCC410
NC29
/TS8
V50
SENSE_PAD
V50
SENSE_PAD
RSNS1 SNS 2
C24510uFC24510uF
V52
SENSE_PAD
V52
SENSE_PAD
RSNS1 SNS 2
U16
LT3009xDC
U16
LT3009xDC
ADJ/NC 1
OUT1 2
OUT2 3
SHDN4
VIN5
GND 6
GND_TAB 7
V53
SENSE_PAD
V53
SENSE_PAD
RSNS1 SNS 2
B2
FAN
B2
FAN
V3
SENSE_PAD
V3
SENSE_PAD
RSNS1 SNS 2
Q2
FDV305N
Q2
FDV305N
V51
SENSE_PAD
V51
SENSE_PAD
RSNS1 SNS 2
R1
99
10
KR
19
91
0K
R51 4.70MR51 4.70M
V55
SENSE_PAD
V55
SENSE_PAD
RSNS1 SNS 2
R2
00
10
KR
20
01
0K
R203DNI
R203DNI
V2
SENSE_PAD
V2
SENSE_PAD
RSNS1 SNS 2
R204
0
R204
0V48
SENSE_PAD
V48
SENSE_PAD
RSNS1 SNS 2
C2460.1uFC2460.1uF
J8
22_23_2021
J8
22_23_2021
12
U13
LTC2418
U13
LTC2418
CH021
CH122
CH223
CH324
CH425
CH526
CH627
CH728
CH81
CH92
CH103
CH114
CH125
CH136
CH147
CH158
COM10 GND 15
VCC 9
REF+ 11
REF- 12
F0 19
CSn 16SCK 18SDI 20
SDO 17
NC1 13
NC2 14
C58
10uF
C58
10uF
V47
SENSE_PAD
V47
SENSE_PAD
RSNS1 SNS 2
V4
SENSE_PAD
V4
SENSE_PAD
RSNS1 SNS 2
R2
01
10
KR
20
11
0K
V49
SENSE_PAD
V49
SENSE_PAD
RSNS1 SNS 2
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FSM_D2FSM_A12
HSMB_TX_D_N3HSMB_TX_D_N1
USER_DIPSW3
FSM_D2
USER_DIPSW3
FSM_A12
HSMB_TX_D_N1HSMB_TX_D_N3
VCC
VCCA
VCC
VCCD_PLL
VREF_B3_B4VREF_B7_B8
2.5V_B5_B6
2.5V
1.8V_B7_B8
VREF_B7_B8
1.8V_B3_B4
VREF_B3_B4
2.5V_B5_B6
USER_DIPSW3 17
FSM_D2 13,14FSM_A12 13,14
HSMB_TX_D_N1 16HSMB_TX_D_N3 16
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
20 25Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
20 25Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
20 25Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Cyclone IV GX Power
(1.2V)
(1.2V)
PLACE NEAR FPGA
(1.2V)
(2.5V)
TP3TP3
TP6TP6
C237
0.1uF
C237
0.1uFC238
0.1uF
C238
0.1uF
C251
0.1uF
C251
0.1uF
C235
0.1uF
C235
0.1uF
C242
0.1uF
C242
0.1uF
C44
0.1uF
C44
0.1uF
TP2TP2
Cyclone IV GX GND
EP4CGX150DF896_DDR2_Swap_hsmc
U10N
Version = 0.1 Preliminary
Cyclone IV GX GND
EP4CGX150DF896_DDR2_Swap_hsmc
U10N
Version = 0.1 Preliminary
GNDL26
GNDL29
GNDL3
GNDL4
GNDL5
GNDL7
GNDL9
GNDM1
GNDM12
GNDM14
GNDM16
GNDM18
GNDM2
GNDM20
GNDM6
GNDN11
GNDN13
GNDN15
GNDN17
GNDN19
GNDN3
GNDN4
GNDN6
GNDN9
GNDP1
GNDP10
GNDP12
GNDP14
GNDP16
GNDP18
GNDP2
GNDP20
GNDP23
GNDP26
GNDP29
GNDP5
GNDP8
GNDR11
GNDR13
GND R15
GND R17
GND R19
GND R21
GND R3
GND R4
GND R5
GND R7
GND R9
GND T1
GND T10
GND T12
GND T14
GND T16
GND T18
GND T2
GND T20
GND T22
GND T5
GND T7
GND U11
GND U13
GND U15
GND U17
GND U19
GND U23
GND U26
GND U29
GND U3
GND U4
GND U5
GND U9
GND V1
GND V10
GND V14
GND V16
GND V18
GND V2
GND V20
NC_2AG1NC_3 AH1
NC_4 AK2
GND V24
GND V6
GND V8
GND W13
NC_1A2
GND W17
GND W19
GND W21
GND W3
GND W4
GND W5
GND W6GNDW9GNDY1GNDY10GNDY14GNDY16
GNDY2
GNDY23
GNDY26
GNDY29
GNDY9
C210
0.1uF
C210
0.1uF
TP5TP5
C240
0.1uF
C240
0.1uFTP7TP7
C239
0.1uF
C239
0.1uF
TP1TP1
Cyclone IV GX I/O Power
EP4CGX150DF896_DDR2_Swap_hsmc
U10L
Version = 0.1 Preliminary
Cyclone IV GX I/O Power
EP4CGX150DF896_DDR2_Swap_hsmc
U10L
Version = 0.1 Preliminary
VCCIO3AB12
VCCIO3AB15
VCCIO3AC9
VCCIO3AD11
VCCIO3AD12
VCCIO3AD13
VCCIO3AD14
VCCIO3AD15
VCCIO4AB18
VCCIO4AB19
VCCIO4AB20
VCCIO6 M24VCCIO6 N22
VCCIO3AC10
VCCIO3AC12
VCCIO6 N23
VCCIO6 P22
VCCIO3AC13
VCCIO3AC15
VCCIO6 L24
VCCIO6 M23
VCCIO6 L22
VCCIO5Y24
VCCIO5W24
VCCIO5W23
VCCIO5W22
VCCIO5V23
VCCIO5V22
VCCIO4AC18
VCCIO4AC19
VCCIO4AC21
VCCIO4AC22
VCCIO4AD17
VCCIO4AD18
VCCIO5U24
VCCIO5U22VCCIO5AA24VCCIO5AA23
VCCIO4AD21VCCIO4AD20VCCIO4AD19
VCCIO6 P24
VCCIO6 R22VCCIO6 R23
VCCIO7 G19VCCIO7 H18VCCIO7 H19VCCIO7 H21VCCIO7 H22
VCCIO7 J17VCCIO7 J18VCCIO7 J19VCCIO7 J20
VCCIO7 J21VCCIO7 J22
VCCIO8 H10VCCIO8 H12
VCCIO8 H13VCCIO8 H15
VCCIO8 H16VCCIO8 J10VCCIO8 J11
VCCIO8 J12
VCCIO8 J13
VCCIO8 J14
VCCIO8 J15
VCCIO8 J16
IO/VREFB3N0AC16
IO/VREFB3N1AG11
IO/VREFB3N2AE11
IO/VREFB4N0AB21
IO/VREFB4N1AG21
IO/VREFB4N2AB17
IO/VREFB5N0U30
IO/VREFB5N1V21
IO/VREFB5N2AA26
IO/VREFB6N0 K24
IO/VREFB6N1 L25
IO/VREFB6N2 N26
IO/VREFB7N0 G21
IO/VREFB7N1 C21
IO/VREFB7N2 G16
IO/VREFB8N0 B13
IO/VREFB8N1 G11
IO/VREFB8N2 C8
VCCIO9 H7
C234
0.1uF
C234
0.1uF
C236
0.1uF
C236
0.1uF
Cyclone IV GX Power
EP4CGX150DF896_DDR2_Swap_hsmc
U10K
Version = 0.1 Preliminary
Cyclone IV GX Power
EP4CGX150DF896_DDR2_Swap_hsmc
U10K
Version = 0.1 Preliminary
VCCINTAA10
VCCINTAA14
VCCINTAB8
VCCINTK13
VCCINTK9
VCCINTL12
VCCINTL14
VCCINTL16
VCCINTL18
VCCINTL20
VCCINTM11
VCCINTM13
VCCINT M15
VCCINT M17
VCCINT M19
VCCINT M9
VCCINT N10
VCCINT N12
VCCINT N14
VCCINT N16VCCINT N18VCCINT N20VCCINT N8VCCINT P11VCCINT P13VCCINT P15VCCINT P17VCCINT P19VCCINT P9VCCINT R10
VCCINT R12
VCCINT R14
VCCINT R16
VCCINT R18
VCCINT R20
VCCINT T11
VCCINT T13
VCCINT T15
VCCINT T17
VCCINT T19
VCCINT T9
VCCINT U10VCCINTU12VCCINTU14VCCINTU16VCCINTU18VCCINTU20VCCINTU8VCCINTV13VCCINTV17
VCCINTW18
VCCINTW20
VCCINTW8
VCCINTY11
VCCINTY13VCCINTY15
VCCINTV19VCCINTV9
VCCINTW10
VCCINTW14
VCC_CLKIN3AW16
VCC_CLKIN3BY12
VCC_CLKIN8AK16
VCC_CLKIN8BK10
VCCAAB24
VCCAK23
VCCD_PLL AB23
VCCD_PLL J23
VCCD_PLL U7
VCCD_PLL Y7
VCCD_PLL Y8
VCCD_PLL K6VCCD_PLL P7VCCD_PLL M8
VCCAAA7
VCCAAA9
VCCAT8
VCCAJ6
VCCAL8
VCCAR8
TP4TP4
C259
0.1uF
C259
0.1uF
Cyclone IV GX GND
EP4CGX150DF896_DDR2_Swap_hsmc
U10M
Version = 0.1 Preliminary
Cyclone IV GX GND
EP4CGX150DF896_DDR2_Swap_hsmc
U10M
Version = 0.1 Preliminary
GNDAA11
GNDAA19
GNDAA3
GNDAA4
GNDAA5
GNDAA8
GNDAB1
GNDAB10
GNDAB2
GNDAB5
GNDAB6
GNDAB7
GNDAC11
GNDAC14
GNDAC17
GNDAC20
GNDAC23
GNDAC24
GNDAC26
GNDAC29
GNDAC3
GNDAC4
GNDAC5
GNDAC6
GNDAD1
GNDAD2
GNDAD5
GNDAE2
GND AF1
GND AF11
GND AF14
GNDAF17GNDAF2GNDAF20GNDAF23GNDAF26GNDAF29GNDAF5GNDAF8
GND AG2
GND AJ11
GND AJ14
GND AJ17
GND AJ2
GND AJ20
GND AJ23
GND AJ26
GND AJ29
GND AJ5
GND AJ8
GND B11
GND B14
GND B17
GND B2
GND B20
GND B23
GND B26
GND B29
GND B5
GND B8
GND D2
GND E11
GND E14
GND E17
GND E20
GND E23
GND E26
GND E29
GND E5
GND E8
GND F3
GND G1
GNDG2
GNDG3
GNDG4
GNDG5
GNDH1
GNDH11
GNDH14
GNDH17
GNDH2
GNDH20
GNDH23
GNDH26
GNDH29
GNDH5
GNDH6
GND H8GND J24GND J3GND J4GND J5GND J7GND J8GND K1
GND K12
GND K14
GND K2
GND K20
GND K7
GND K8
GND L13
GND L17
GND L19GNDL21GNDL23
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
TG1
BG1
BOOST1
VCCA_SNS
VCCA_VCCH_SNSITH1VFB1
VCCD_PLL_SNS
BOOST2TG2
BG2VCCL_SNS
BOOST3TG3
BG3
VFB2ITH2
VFB3ITH3
RUN_SW
RUN_SW
SW2
SW1
SW3
SW2
SW1
SW3
A
B
DC_INPUT
12V
3.3V
12V_PCIE
12V
12V
INTVCC
12V2.5V
VCCA
2.5V_VCCA_VCCH_GXB
INTVCC
INTVCC
2.5V12V
1.2VINTVCC
VCC
1.2V_VCCL_GXB
VCCD_PLL
12V
12V_HSMC
INTVCC
1.2V
12V_HSMC
INTVCCINTVCC
RUN_SW22,23VCCA_SNS19VCCA_VCCH_SNS19VCCL_SNS19VCCD_PLL_SNS19
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
21 25Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
21 25Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
21 25Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Power 1, (2.5V, 1.2V and 12V)14V-20V DC INPUT
POWER LED
Switching Freq = 450kHz
Forced Continuous
C37
10uF
C37
10uF
C223
4.7uF
C223
4.7uF
L51.2uH L51.2uH
12
C203
2.2uF
C203
2.2uF
C205
0.1uF
C205
0.1uF
R20 68.1KR20 68.1K
R1630 R1630
D32
CMDSH2_3
D32
CMDSH2_3
C171220pF C171220pF
R330.003 R330.003
R172140.0K R172140.0K CH2
CH1
Q4
SI4816BDY-T1
CH2
CH1
Q4
SI4816BDY-T1
5
8
2
43
71
6
L11BLM15AG221SN1L11BLM15AG221SN1
R491.37K R491.37K
D11
Blue_Led
D11
Blue_Led
C1610.1uF C1610.1uF
+ C187
4V
Tantalum
330uF+ C187
4V
Tantalum
330uF
12
R1421.00M R1421.00M
L6 8.2uHL6 8.2uH
1 2
C225
4.7uF
C225
4.7uF
L45.6uH L45.6uH
12
C43
10uF
C43
10uF
C29
22uF
C29
22uF
R159100K R159100K
C222
0.1uF
C222
0.1uF
C190
0.01uF
C190
0.01uF
C1421500pFC1421500pF
C221
4.7uF
C221
4.7uF
R12
100, 1%
R12
100, 1%
R392.61K R392.61K
C14310pF C14310pF
U52
LTC4357xDCB
U52
LTC4357xDCB
OUT 1IN2GATE3
GND4 NC 5
VDD 6
OPEN_EPAD 7
C202
4.7uF
C202
4.7uF
R155
3.24K
R155
3.24K
R15410.0K R15410.0K
Q3FDS8880
Q3FDS88804
5167
23
8
D34
CMDSH2_3
D34
CMDSH2_3
R12620.0K R12620.0K
L3BLM15AG221SN1L3BLM15AG221SN1
C24
220uF
C24
220uF
R12943.2K R12943.2K
C224
0.1uF
C224
0.1uF
R2400.003 R2400.003
J5
RAPC712X
J5
RAPC712X3
21
C36
22uF
C36
22uF
L12
BLM15AG221SN1
L12
BLM15AG221SN1
C1580.1uFC1580.1uF
C54
150uF
C54
150uF
R16110.0K R16110.0K
R15243.2K R15243.2K
R15020.0K R15020.0K
R2380.003 R2380.003
C15710pF C15710pF
R162DNI R162DNI
R280.003 R280.003
R160100K R160100K
U48
LTC4357xDCB
U48
LTC4357xDCB
OUT 1IN2GATE3
GND4 NC 5
VDD 6
OPEN_EPAD 7
L2
BLM15AG221SN1
L2
BLM15AG221SN1
C193
0.1uF
C193
0.1uF
R2390.003 R2390.003
C39
10uF
C39
10uF
C156470pFC156470pF
C1720.1uF C1720.1uF
C192
0.1uF
C192
0.1uF
C30
10uF
C30
10uF
R1611.5KR1611.5K
R15310.0K R15310.0K
R1431.62K R1431.62K
R464.32K R464.32K
R1415.49K R1415.49K
R34
0
R34
0
C194
0.1uF
C194
0.1uF
C1590.1uFC1590.1uF
C220
0.1uF
C220
0.1uF
Q1FDS8880
Q1FDS88804
5167
23
8
R1842.20R1842.20
CH2
CH1
Q5
SI4816BDY-T1
CH2
CH1
Q5
SI4816BDY-T1
5
8
2
43
71
6
C18910pF C18910pF
C144330pF C144330pF
U43
LTC3853xUJ
U43
LTC3853xUJ
TK/SS140
TK/SS21
TK/SS32
VFB19ITH110
VFB212ITH213
VFB314ITH315
RUN136
RUN235
RUN334
MODE/PLLIN37
FREQ/PLLFLTR38
ILIM39
PGOOD1217PGOOD316
VIN
24
EX
TV
CC
23
INT
VC
C22
DR
VC
C12
29
TG1 32
SW1 31
BG1 30
BOOST1 33
SNSP1 3
SNSN1 4
TG2 26
SW2 27
BG2 28
BOOST2 25
SNSP2 5
SNSN2 6
TG3 19
SW3 20
BG3 21
BOOST3 18
SNSP3 7
SNSN3 8
SGND 11
EPAD_GND 41
C1620.1uF C1620.1uFD33
CMDSH2_3
D33
CMDSH2_3
C188680pFC188680pF
R1445.36K R1445.36K
SW3EG2201ASW3EG2201A
1 2 3
654
R164
11.5K
R164
11.5K
D23
FM540
D23
FM540
R17310.0K R17310.0K
C155330pF C155330pF
C1600.1uFC1600.1uF
CH2
CH1
Q6
SI4816BDY-T1
CH2
CH1
Q6
SI4816BDY-T1
5
8
2
43
71
6
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
TG1_B
BG1_B
BOOST1_B
ITH1_BVFB1_B
RUN_SW
BOOST2_BTG2_B
BG2_B
VFB2_BITH2_B
SW2_B
SW1_B
SW1_B
SW2_B
12V
INTVCC
12V
1.8V
INTVCC
INTVCC
1.8V12V
3.3V
INTVCC
3.3V
INTVCC
RUN_SW21,23
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
22 25Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
22 25Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
22 25Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Power 2, (3.3V and 1.8V)
Switching Freq = 450kHz
Forced Continuous
C374DNI C374DNI
C77
10uF
C77
10uF
C3753300pF C3753300pF
C62
10uF
C62
10uF
R25320.0K R25320.0K
L93.3uH L93.3uH
1 2
R553.90K R553.90K
C373DNI C373DNI
R2340 R2340
R248DNI R248DNI
C3650.1uF C3650.1uF
C3570.1uFC3570.1uF
+ C61
4V
Tantalum
330uF+ C61
4V
Tantalum
330uF
12
C290
4.7uF
C290
4.7uF
C80
10uF
C80
10uFR2462.21K R2462.21K
+ C81
4V
Tantalum
330uF+ C81
4V
Tantalum
330uF
12
C63
10uF
C63
10uF
R23510.2K R23510.2K
R25625.5K R25625.5K
R2582.15K R2582.15K
D36
CMDSH2_3
D36
CMDSH2_3
C3560.1uFC3560.1uF
R2471.62K R2471.62K
C3641000pF C3641000pF
CH2
CH1
Q8
SI4816BDY-T1
CH2
CH1
Q8
SI4816BDY-T1
5
8
2
43
71
6
R25220.0K R25220.0K
D35
CMDSH2_3
D35
CMDSH2_3
C289
0.1uF
C289
0.1uF
R2312.20R2312.20
C3725600pF C3725600pF
C56
150uF
C56
150uFC337
4.7uF
C337
4.7uF
C3620.1uF C3620.1uF
C349
0.1uF
C349
0.1uF
C78
10uF
C78
10uF
R2512.15K R2512.15K
R25763.4K R25763.4K
C363560pF C363560pF
L83.3uH L83.3uH
1 2
R236100K R236100K
R562.20K R562.20K
C335
2.2uF
C335
2.2uF
CH2
CH1
Q7
SI4816BDY-T1
CH2
CH1
Q7
SI4816BDY-T1
5
8
2
43
71
6
C291
0.1uF
C291
0.1uF
C321
0.1uF
C321
0.1uF
U50
LTC3850xUF
U50
LTC3850xUF
TK/SS11
VFB13ITH12
VFB24ITH25
RUN126
RUN29
MODE/PLLIN24
FREQ/PLLFLTR25
ILIM10
PGOOD12
PGND 16
EPAD_GND 29
VIN
19
EX
TV
CC
11
INT
VC
C18
TG1 22
SW1 23
BG1 20
BOOST1 21
SENSE_P1 27
SENSE_N1 28
TG2 14
SW2 13
BG2 17
BOOST2 15
SENSE_P2 8
SENSE_N2 7
TK/SS26
R23710.0K R23710.0K
C79
10uF
C79
10uF
C336
0.1uF
C336
0.1uF
R2332.55KR2332.55K
C288
4.7uF
C288
4.7uF
C334
0.1uF
C334
0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
1.8V_B3_B4_SNS
RUN_SW
2.5V_B5_B6_POS
VREF_B3_B4
VTT_B3_B4
5.0V
1.8V_B3_B4
VREF_B7_B8
VTT_B7_B8
5.0V
1.8V_B7_B8
2.5V
1.8V_FPGA
5.0V
1.8V_B7_B8
1.8V_B3_B4
1.8V_FPGA
5V_USB
2.5V_USB
5.0V12V
5.0V 1.1V3.3V
1.1V
5.0V3.3V
2.5V_B5_B6
RUN_SW21,22
1.8V_B3_B4_SNS19
2.5V_B5_B6_POS 19
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
23 25Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
23 25Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
23 25Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Power 3, (DDR2 (VREF/VTT), 5.0V, 1.8V FPGA VCCIO,1.1V Ethernet)
0.9V VTT (3A Sink/Src)
0.9V VTT (3A Sink/Src)
SHUNT INSTALLED 2.5V
SHUNT NOT INSTALLED 1.8V
C306
10uF
C306
10uF
R128261KR128261K R138
100K
R138
100K
R146 .009R146 .009
C178
10uF
C178
10uF
C275
0.1uF
C275
0.1uF
L10
BLM15AG221SN1
L10
BLM15AG221SN1
LT3027
U41
LT3027
LT3027
U41
LT3027
BYP2 1
ADJ2 2
ADJ1 4BYP1 5
OUT1 6
SHDN1n7IN18
IN29
SHDN2n3 OUT2 10
GND11
C277
0.1uF
C277
0.1uF
U53
LTC3026
U53
LTC3026
IN11
IN22
GN
D3
SW4
BST 5
SHDN6
PG 7ADJ 8
OUT1 9OUT2 10
GN
D11
C379
10uF
C379
10uF
R249 2.87KR249 2.87K
R227 10.0KR227 10.0K
C140
10uF
C140
10uF
C332
10uF
C332
10uF
C146
0.01uF
C146
0.01uF
R136
3.0K
R136
3.0K
R145 .009R145 .009
C141
10uF
C141
10uF
C148
10uF
C148
10uF
R255 100KR255 100K
R124 100KR124 100K
J3
HDR2X1
J3
HDR2X1
1 1
2 2
C381 1uFC381 1uF
R123 4.7KR123 4.7K
U45 TPS51100DGQU45 TPS51100DGQ
VDDQSNS 1VLDOIN 2
VTT 3
PG
ND
4
VTTSNS 5
VTTREF6
S37
GN
D8
S59
VIN10
GN
D11
C247
10uF
C247
10uF
C201
10uF
C201
10uF
C359
10uF
C359
10uF
R217 10.0KR217 10.0K
C131 1uFC131 1uF
C200
10uF
C200
10uF
R148 4.7KR148 4.7K
R135
1.50K
R135
1.50K
C270
1uF
C270
1uF
C147
10uF
C147
10uF
C180 1uFC180 1uF
R226 10.0KR226 10.0K
U47 TPS51100DGQU47 TPS51100DGQ
VDDQSNS 1VLDOIN 2
VTT 3
PG
ND
4
VTTSNS 5
VTTREF6
S37
GN
D8
S59
VIN10
GN
D11
R254 5.11KR254 5.11K
C350
10uF
C350
10uF
C285
10uF
C285
10uF
C139
0.01uF
C139
0.01uF
C333
10uF
C333
10uF
C248
10uF
C248
10uF
C232
10uF
C232
10uF
R117 5.23KR117 5.23K
C265
10uF
C265
10uF
C166
10uF
C166
10uF
R139316K R139316K
R127
249K
R127
249K
R137 .009R137 .009
+ C92
10V
Tantalum
470uF+ C92
10V
Tantalum
470uF
12
U40
LTC3026
U40
LTC3026
IN11
IN22
GN
D3
SW4
BST 5
SHDN6
PG 7ADJ 8
OUT1 9OUT2 10
GN
D11
C145
10uF
C145
10uF
C378
10uF
C378
10uF
C380
10uF
C380
10uF
R118
1.50K
R118
1.50KU42
LTC3026
U42
LTC3026
IN11
IN22
GN
D3
SW4
BST 5
SHDN6
PG 7ADJ 8
OUT1 9OUT2 10
GN
D11
R218 10.0KR218 10.0K
C307
1uF
C307
1uF
R250 4.7KR250 4.7K
R147 5.23KR147 5.23K
C124
10uF
C124
10uF
C249
10uF
C249
10uF
R157 100KR157 100K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
VCCVCCD_PLL 1.2V_VCCL_GXB
1.8V_B3_B4 1.8V_B7_B8 2.5V_B5_B6 2.5V_VCCA_VCCH_GXB VCCA
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
24 25Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
24 25Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
01
Cyclone IV GX FPGA Development Kit Board
B
24 25Wednesday, December 08, 2010
150-0311003-B1 (6XX-43286R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
FPGA DecouplingPlace 6 vias minimum on each X2Y cap.
FPGA VCC
FPGA VCCD_PLL FPGA VCCL_GXB
FPGA 1.8V VCCIO Banks 3 and 4 FPGA 1.8V VCCIO Banks 7 and 8 FPGA 2.5V VCCIO Banks 5 and 6 FPGA 2.5V VCCA_GXB and VCCH_GXB FPGA 2.5V VCCA and VCC_CLKIN
STANDOFF4STANDOFF4
STANDOFF1STANDOFF1
C182
220nF
C182
220nF
C176
220nF
C176
220nF
C11
4.7uF
C11
4.7uF
C179
470nF
C179
470nF
SCREW3SCREW3
+ C297
4V
Tantalum
330uF+ C297
4V
Tantalum
330uF
12
STANDOFF5STANDOFF5
C26
330uF
C26
330uF
C48
330uF
C48
330uF
C59
100nF
C59
100nF
C177
1uF
C177
1uF
STANDOFF3STANDOFF3
C233
10nF
C233
10nF
C40
220nF
C40
220nF
SCREW4SCREW4
C45
10nF
C45
10nF
C298
470nF
C298
470nF
C181
1uF
C181
1uFC271
10nF
C271
10nF
SCREW5SCREW5
C31
1uF
C31
1uF
C55
4.7uF
C55
4.7uF
C84
330uF
C84
330uF
C41
4.7uF
C41
4.7uF
C50
220nF
C50
220nF
C65
2.2uF
C65
2.2uF
C228
1uF
C228
1uF
C5
330uF
C5
330uF
C10
2.2uF
C10
2.2uF SCREW1SCREW1
STANDOFF2STANDOFF2
C9
330uF
C9
330uF
C49
4.7uF
C49
4.7uF
C299
470nF
C299
470nF
C66
330uF
C66
330uF
C47
22nF
C47
22nF
C22
47nF
C22
47nF
C60
100nF
C60
100nF
C46
330uF
C46
330uF
SCREW2SCREW2
C52
100nF
C52
100nF
C209
1uF
C209
1uF
C243
22nF
C243
22nF
C250
1uF
C250
1uF
+ C183
4V
Tantalum
330uF+ C183
4V
Tantalum
330uF
12
C18
330uF
C18
330uF
C57
22nF
C57
22nF
C38
4.7uF
C38
4.7uF
C64
2.2uF
C64
2.2uF