1

ST.MARTIN’S ENGG.COLLEGE

DHULAPALLY, SEC.BAD.

______________________________________________

COURSE FILE

SUBJECT: EDC

B SHUBHAKER

Asst.Professor

Department: ECE

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ST.MARTIN’S ENGG.COLLEGE

DHULAPALLY, SEC.BAD.

SYLLABUS

UNIT-I: P-N JUNCTION DIODEQualitative theory of p-n junction, p-n junction as a Diode, Diode equation, volt-ampere charecteristics,Temperature dependence of VI characteristic, Ideal versus practical-Resistance levels (static and dynamic),transition and diffusion capacitances, diode equivalent circuits, load line analysis,breakdown mechanisms in semi conductor diodes,zener diode characteristics.

SPECIAL PURPOSE ELECTRONIC DEVICESPrinciple of operation and characteristics of Tunnel diode (with the help of energy band diagram) and varactor diode, principle of operation of Schottky barrier diode, SCR and semiconductor photo diode.

UNIT-II: RECTIFIERS AND FILTERSThe P-N junction as a rectifiers, Half wave rectifier, Full wave rectifier ,Bridge rectifier, harmonic components in a rectifier circuit, Inductor filters, Capacitor filters, L-section filters, Pi-section filters,comparision of filters, voltage regulation using Zener diode.

UNIT-III: BIPOLAR JUNCTION TRANSISTORThe junction transistor, transistor current components, transistor as an amplifier, transistor construction, BJT operation, BJT symbol, common base, common emitter and common collector configurations, limits of operation, BJT specifications. the Uni junction transistor.

UNIT-IV: TRANSISTOR BIASING AND STABILIZATIONOperating point, the DC and AC load lines, need for biasing, fixed bias, collector feedback bias, emitter feedback bias, collector–emitter feedback bias, voltage divider bias, bias stability, stabilization factors, stabilization against variations in VBE and β, bias compensation using diodes and transistors, thermal runaway, thermal stability. BJT hybrid model, determination of h-parameters from transistor characteristics, analysis of a transistor amplifier circuit using h-parameters, comparison of CB, CE, CC amplifier configurations.

UNIT-V: FIELD EFFECT TRANSISTORThe junction field effect transistor (construction, principle of operation, symbol)-pinch –off voltage-volt-amp characteristics, the JFET small signal model, MOSFET(construction, principle of operation, symbol),MOSFET characteristics in enhancement and depletion modes

FET AMPLIFIERSFET common source amplifier, common drain amplifier, generalized FET amplifier, biasing FET, FET as voltage variable resistor, comparison of BJT and FET.

TEXT BOOKS:1. Milliman’s electronic devices and circuits-J.Millman,C.C.Halkias, and Satyabrata Jit,second ed..1998,TMH.2. Electronic devices and circuits-R.L.Boylestad and Louis Nashelsky,9 ed…2006,PEI/PHI.3. Introduction to electronic devices and circuits-Robert T.Paynter,PE.REFERENCES:1. Integrated electronics –J.Millman and Christos C.Halkias, 1991 ed..2008,TMH.2. Electronic devices and circuits –K.Lal kishore,2 ed..,2005,BSP.3. Electronic devices and circuits-Anil K.Maini,Varsha Agarwal,1 ed..2009,wiley india Pvt Ltd.4. Electronic devices and circuits-S.Salivahanan, N.Suresh kumar,A.Vallavaraj,2 ed..2008,TMH

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ST.MARTIN’S ENGG.COLLEGE

DHULAPALLY, SEC.BAD.

UNIT-I

1. Define and write the differences between materials?

INSULATOR:An insulator is a material that offers a very low level of conductivity under Pressure from an applied voltage source. In this material Forbidden energy gap is large (EG 6e.V).So, electron can not acquire enough energy and hence conduction is not possible. Ex: Diamond is a perfect insulator.SEMI CONDUCTOR:A semiconductor, is a material that has a conductivity level somewhere in between the extremes of an insulator and a conductor. Energy gap is only about 1ev. Ex: Germanium, Silicon(Energy gap of Germanium is about 0.785 ev and for silicon it is 1.21ev).CONDUCTOR:Conductor is a material that will support a generous flow of charge when a voltage source of limited magnitude is applied across its terminals. There is no energy gap in conductors. Conduction band and valence band are overlapped. Ex:Copper,Aluminium.DOPING:Adding impurities in a semiconductor is called Doping.Pure semiconductor is called Intrinsic semiconductor. Semiconductor with impurities added are called extrinsic semiconductor.

2. Write about extrinsic semiconductor material?

EXTRINSIC MATERIALS

The characteristics of semiconductor materials can be altered significantly by the addition of certain impurity atoms into the relatively pure semiconductor material. These impurities, although only added to perhaps 1 part in 10 million, can alter the band structure sufficiently to totally change the electrical properties of the material. A semiconductor material that has been subjected to the doping process is called an extrinsic material. There are two extrinsic materials of immeasurable importance to semiconductor device fabrication: n-type and p-type.n-Type Material

Both the n- and p-type materials are formed by adding a predetermined number of impurity atoms into a germanium or silicon base. The n-type is created by introducing those impurity elements that have five valence electrons (pentavalent), such as antimony, arsenic, and phosphorus. The effect of such impurity elements is indicated in

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Figure.1 Antimony impurity in n-type material

Fig.1 (using antimony as the impurity in a silicon base). Note that the four covalent bonds are still present. There is, however, an additional fifth electron due to the impurity atom, which is unassociated with any particular covalent bond. Diffused impurities with five valence electrons are called donor atoms. The effect of this doping process on the relative conductivity can best be described through the use of the energy-band diagram of Fig. 1.1.

Figure 1.1 Effect of donor impurities on the energy band structure. p-Type Material

The p-type material is formed by doping a pure germanium or silicon crystal with impurity atoms having three valence electrons. The elements most frequently used for this purpose are boron, gallium, and indium. The effect of one of these elements, boron, on a base of silicon is indicated in Fig. 1.2.

Note that there is now an insufficient number of electrons to complete the covalent bonds of the newly formed lattice. The resulting vacancy is called a hole and is represented by a small circle or positive sign due to the absence of a negative charge. Since the resulting vacancy will readily accept a ―free‖ electron: The diffused impurities with three valence electrons are called acceptor atoms.

Majority and Minority CarriersIn the intrinsic state, the number of free electrons in Ge or Si is due only to those few electrons

in the valence band that have acquired sufficient energy from thermal or light sources to break the covalent bond or to the few impurities that could not be removed. The vacancies left behind in the covalent bonding structure represent our very limited supply of holes. In an n-type material the number of holes has not changed significantly from this intrinsic level. The net result, therefore, is that the number of electrons far outweighs the number of holes. For this reason:

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In an n-type material (Fig. 1.13a) the electron is called the majority carrier and the hole the minority carrier.For the p-type material the number of holes far outweighs the number of electrons, as shown in Fig. 1.13b. Therefore: In a p-type material the hole is the majority carrier and the electron is the minority carrier. When the fifth electron of a donor atom leaves the parent atom, the atom remaining acquires a net positive charge: hence the positive sign in the donor-ion representation. For similar reasons, the negative sign appears in the acceptor ion.

Figure 1.13 (a) n-type material; (b) p-type material.Fermi Level in N & P type materials is shown in below Fig:

In N type material Fermi level is just below the conduction band. In P type material Fermi level is just above the valence band.

3. Explain the operation of PN junction diode in forward and reverse biases?

PN diode characteristics in forward bias and reverse bias regions:

The semiconductor diode is formed by simply bringing these materials together (constructed from the same base—Ge or Si), as shown in Fig. 1.14. At the instant the two materials are ―joined‖ the electrons and holes in the region of the junction will combine, resulting in a lack of carriers in the region near the junction. This region of uncovered positive and negative ions is called the depletion region due to the depletion of carriers in this region. Since the diode is a two-terminal device, the application of a voltage across its terminals leaves three possibilities: no bias (VD = 0 V), forward bias (VD >0 V), and reverse bias (VD< 0 V)

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Under no-bias (no applied voltage) conditions, any minority carriers (holes) in the n-type material that find themselves within the depletion region will pass directly into the p-type material. The closer the minority carrier is to the junction, the greater the attraction for the layer of negative ions and the less the opposition of the positive ions in the depletion region of the n-type material. For the purposes of future discussions we shall assume that all the minority carriers of the n-type material that find themselves in the depletion region due to their random motion will pass directly into the p-type material. Similar discussion can be applied to the minority carriers (electrons) of the p-type material. This carrier flow has been indicated in Fig. 1.14 for the minority carriers of each material. The majority carriers (electrons) of the n-type material must overcome the attractive forces of the layer of positive ions in the n-type material and the shield of negative ions in the p-type material to migrate into the area beyond the depletion region of the p-type material. However, the number of majority carriers is so large in the n-type material that there will invariably be a small number of majority carriers with sufficient kinetic energy to pass through the depletion region into the p-type material. Again, the same type of discussion can be applied to the majority carriers (holes) of the p-type material. The resulting flow due to the majority carriers is also shown in Fig. 1.14. In the absence of an applied bias voltage, the net flow of charge in any one direction for a semiconductor diode is zero. The symbol for a diode is repeated in Fig. 1.15 with the associated n- and p-type regions. Note that the arrow is associated with the p-type component and the bar with the n-type region. As indicated, for VD= 0 V, the current in any direction is 0 mA.

Figure 1.15 No-bias conditions for a semiconductor diode.Reverse-Bias Condition (VD < 0 V)

If an external potential of V volts is applied across the p-n junction such that the positive terminal is connected to the n-type material and the negative terminal is connected to the p-type material as shown in Fig. 1.16, the number of uncovered positive ions in the depletion region of the n-type material will increase due to the large number of ―free‖ electrons drawn to the positive potential of the applied voltage. For similar reasons, the number of uncovered negative ions will increase in the p-type material. The net effect, therefore, is a widening of the depletion region. This widening of the depletion region will establish too great a barrier for the majority carriers to overcome, effectively reducing the majority carrier flow to zero as shown in Fig. 1.16.

Figure 1.16 Reverse-biased p-n junction.

The number of minority carriers, however, that find themselves entering the depletion region will not change, resulting in minority-carrier flow vectors of the same magnitude indicated in Fig. 1.14 with no applied voltage the current that exists under reverse-bias conditions is called the reverse saturation current and is represented by Io.

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Forward-Bias Condition (VD > 0 V)A forward-bias or ―on‖ condition is established by applying the positive potential to the p-type material and the negative potential to the n-type material as shown in Fig. 1.18. A semiconductor diode is forward-biased when the association p-type and positive and n-type and negative has been established.

Figure 1.18 Forward-biased p-n junction

The application of a forward-bias potential VD will ―pressure‖ electrons in the n-type material and holes in the p-type material to recombine with the ions near the boundary and reduce the width of the depletion region as shown in Fig. 1.18. The resulting minority-carrier flow of electrons from the p-type material to the n-type material (and of holes from the n-type material to the p-type material) has not changed in magnitude (since the conduction level is controlled primarily by the limited number of impurities in the material), but the reduction in the width of the depletion region has resulted in a heavy majority flow across the junction. An electron of the n-type material now ―sees‖ a reduced barrier at the junction due to the reduced depletion region and a strong attraction for the positive potential applied to the p-type material. As the applied bias increases in magnitude the depletion region will continue to decrease in width until a flood of electrons can pass through the junction, resulting in an exponential rise in current as shown in the forward-bias region of the characteristics of Fig. 1.19. Note that the vertical scale of Fig. 1.19 is measured in milliamperes and the horizontal scale in the forward-bias region has a maximum of 1 V. Typically, therefore, the voltage across a forward-biased diode will be less than 1 V.

Figure 1.19 Silicon semiconductor diode characteristics.

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Equation for diodejunctioncurrent:

where VT = kT/q; VVD_ diode terminal voltage, VoltsIo _ temperature-dependent saturation current, µA T _ absolute temperature of p-n junction, Kk _ Boltzmann’s constant 1.38x 10 -23J/K) q _ electron charge 1.6x10-19 C

= empirical constant, 1 for Ge and 2 for Si

4. Write the temperature effect on PN junction diode?

Temperature EffectsTemperature can have a marked effect on the characteristics of a silicon semiconductor diode

as shown in Fig. 1.24. It has been found experimentally that the reverse saturation current Io will just about double in magnitude for every 10°C increase in temperature.

Figure 1.24 Variation in diode characteristics with temperature change.

It is not uncommon for a germanium diode with an Io in the order of 1 or 2 A at 25°C to have a leakage current of 100 A _ 0.1 mA at a temperature of 100°C. Typical values of Io for silicon are much lower than that of germanium for similar power and current levels. The result is that even at high temperatures the levels of Io for silicon diodes do not reach the same high levels obtained for germanium—a very important reason that silicon devices enjoy a significantly higher level of development and utilization in design. Fundamentally, the open-circuit equivalent in the reverse bias region is better realized at any temperature with silicon than with germanium. The increasing levels of Io with temperature account for the lower levels of threshold voltage, as shown in Fig. 1.24. Simply increase the level of Io in and not rise in diode current. Of course, the level of TK also will be increase, but the increasing level of Io will overpower the smaller percent change in TK. As the temperature increases the forward characteristics are actually becoming more ―ideal

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5. Explain about Transition and Diffusion Capacitance?

TRANSITION AND DIFFUSION CAPACITANCEElectronic devices are inherently sensitive to very high frequencies. Most shunt capacitive effects that can be ignored at lower frequencies because the reactance XC=1/2πfC is very large (open-circuit equivalent). This, however, cannot be ignored at very high frequencies. XC will become sufficiently small due to the high value of f to introduce a low-reactance ―shorting‖ path. In the p-n semiconductor diode, there are two capacitive effects to be considered. In the reverse-bias region we have the transition- or depletion-region capacitance (CT), while in the forward-bias region we have the diffusion (CD) or storage capacitance. Recall that the basic equation for the capacitance of a parallel-plate capacitor is defined by C= €A/d, where € is the permittivity of the dielectric (insulator) between the plates of area A separated by a distance d. In the reverse-bias region there is a depletion region (free of carriers) that behaves essentially like an insulator between the layers of opposite charge. Since the depletion width (d) will increase with increased reverse-bias potential, the resulting transition capacitance will decrease. The fact that the capacitance is dependent on the applied reverse-bias potential has application in a number of electronic systems. Although the effect described above will also be present in the forward-bias region, it is overshadowed by a capacitance effect directly dependent on the rate at which charge is injected into the regions just outside the depletion region. The capacitive effects described above are represented by a capacitor in parallel with the ideal diode, as shown in Fig. 1.38. For low- or mid-frequency applications (except in the power area), however, the capacitor is normally not included in the diode symbol.

6. What is the difference between LED and LCD?

A Light-Emitting-Diode (LED) display generates light energy as current is passed through the individual segments. It refers to the backlight system used in many newer LCD televisions and not the chips that produce the images. A liquid-crystal display (LCD) controls the reflection of available light. Traditional LCD TVs are normally back lit by fluorescent bulbs.

LCD TVs and LED TVs work by blocking light. The following explains how they work-

-A solution of TN liquid crystals is inserted between two perpendicularly aligned panes of polarized glass. It is possible to manipulate the intensity of light as it passes through this crystalline matrix and out of the glass panel at the other end by twisting one of the panes wrt the other.

-Depending on the voltage of the electrical charge running through them, liquid crystals will untwist so that the intensity of light that can pass through the second polarized pane is affected.

-Fundamentally, these displays can switch between light states (where the liquid crystals are fully twisted) and dark states (where the liquid crystals are fully untwisted), or somewhere along the gray scale in between.

The following are the advantages of LEDs over LCDs-LEDs are longer lasting than fluorescent bulbs.LEDs are more energy efficient than fluorescent bulbs.LEDs give greater contrast and better image quality than LCDs.

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7. What do you understand by LEDs? How do they work?

LEDs refer to the term Light Emitting Diode. LEDs are heavily doped p-n junctions which works under forward bias and emits spontaneous radiation. When the p-n junction is forward biased-The excess minority chargers accumulate at the junction boundary on either side. When they recombine, energy is released in the form of photons, having energy equal to or lesser than the band gap energy. The intensity of light emitted is directly proportional to the forward current.The reverse breakdown voltage is low (around 5V).

8. What are Laser Diodes?

Laser Diodes are compact transistor-like packages with two or more electrical leads. -Inside the package is a small semiconductor chip, containing the laser cavity. The chip contains a stack of layers with different doping and compositions that provide optical and electrical confinement.Lasing occurs when stimulated emission causes the amplification of photons confined to the lasing mode. Photons bounce back and forth between the front and back mirror. Hence, a diverging beam emerges from the laser diode package. They have applications in the telecommunications industry and in testing instrumentation.

9. Write about the conductivity of a semiconductor?

CONDUCTIVITY OF A SEMICONDUCTOR

With each hole - electron pair created, two charges - carrying particles are formed

One is negative (free e-) of mobility μn, and the other is positive (hole) of mobility μp.

The current density J is given by,

Where n = magnitude of free electron (negative) concentration,

p = magnitude of hole (positive) concentration,

σ = conductivity,

ε = electric field and

q = electron charge

Hence

The resistivity ρ is inversely proportional to the conductivity and is given by,

J=(n µn + p µp) q ε = σ ε ε

σ=(n µn + p µp) q

ρ = 1/ σ = 1 / (n µn + p µp) q

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For a pure (called intrinsic) semiconductor considered here,

Where, ni is the intrinsic concentration

In pure germanium at room temperature there is about one hole – electron pair for every 2 × 109

germanium atoms

With increasing temperature, the density of hole – electron pair increases and correspondingly, the

conductivity increases

The intrinsic concentration ni varies with temperature in accordance with the relationship,

Where A0 = material constant

T = temperature in degree Kelvin

EGO = energy gap at 0K in eV

K = Boltzmann constant in eV/K

The conductivity of Germanium (Silicon) increases approximately 6(8) percent per degree increase

in temperature

The resistivity (reciprocal of conductivity) of a semi conductor decreases exponentially where in

metals the resistivity increases almost linearly

Semiconductor has a negative temperature coefficient of resistance where as that of a metal is

positive and of much smaller magnitude

For most metals the resistance increase about 0.4 percent /oC increase in temperature

The constants EGO, μn,, μp and many other important physical quantities for Germanium and

Silicon are given in Table. Note that germanium has of the order of 1022 atoms/cm3, whereas at

room temperature (300K), ni = 1013/cm4. Hence only 1 atom in about 109 contributes a free

electron (and a hole) to the crystal because of broken covalent bonds. For silicon this ratio is even

smaller, about 1 atom in 1012

10. WRITE ABOUT THECHARGE DENSITIES IN A SEMICONDUCTOR?

Let ND equal the concentration of donor atoms, these are practically all ionized, ND positive

charges per cubic meter are contributed by the donor ions

Hence the total positive charge density is ND + p

n = p = ni

ni2 = A0 T3 𝑒

‒ 𝐸𝐺𝑂/𝐾𝑇

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Similarly, if NA is the concentration of acceptor ions, these contribute NA negative charges per

cubic meter

The total negative charge density is NA + n

Since the semiconductor is electrically neutral, the magnitude of the positive charge density must

equal that of the negative concentration, or

-------------------------------------------- (1)

Consider an n – type material having NA = 0. Since the number of electrons is much greater than

the number of holes in an n – type semiconductor (n >> p) then equation (1) reduces to

n≃ ND or nn ≃ ND

In a n – type material the free electron concentration nn is approximately equal to the density of

donor atoms

The concentration pn of holes in the n – type semiconductor is obtained from, nnpn =n2i

Thus,

Similarly, for a p - type semiconductor

According to the law of mass action, the product of the number of electrons in the conduction band

and the number of holes in the valence band must be constant

consider an n – type silicon in which dopant concentration is / . Find electron and hole 1017 𝑐𝑚3

concentration at 350 K, (intrinsic carrier concentration at 350 K is 4.18 / ).× 1011 𝑐𝑚3

SOLUTION: Electron concentration n = dopant concentration = / & hole concentration p = 1017 𝑐𝑚3

𝑛𝑖2

𝑛

= = 1.747 /(4.18 × 1011)2

1017 × 106 𝑐𝑚3

11. A silicon bar is doped with arsenic atoms/ . What is the equilibrium hole concentration at 1017 𝑐𝑚3

300 K? Where is the Fermi level ( ) of sample located relative to intrinsic Fermi level ( )? ( = 1.5 𝐸𝐹 𝐸𝑖 𝑛𝑖

/ )× 1010 𝑐𝑚3

SOLUTION: Electron n = = /𝑁𝐷 1017 𝑐𝑚3

Hole concentration p = 𝑛𝑖

2

𝑛

= = = 2.25 /1.5 × 1010

1017

2.25 × 1020

1017 × 103 𝑐𝑚3

For n – type material = 𝑁𝐷 𝑛𝑖 𝑒‒ (𝐸𝐹𝑖 ‒ 𝐸𝐹)/𝐾𝑇

ND + p =NA +n

pn = /NDn2i

nppp = ; pp≃ NA np =ni2/NAn2

i

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⟹1017 = 1.5 × 1010 𝑒‒ (𝐸𝐹𝑖 ‒ 𝐸𝐹)/𝐾𝑇

= 15.7⟹𝐸𝐹 ‒ 𝐸𝐹𝑖

𝐾𝑇

= ⟹ 𝐸𝐹 ‒ 𝐸𝐹𝑖15.7 × 1.38 × 10 ‒ 23 × 300

1.6 × 10 ‒ 19

= 0.4 eV

So Fermi level move up by 0.4 eV relative to intrinsic Fermi level

12. WRITE ABOUT THEDRIFT AND DIFFUSION CURRENTS?

The Conductivity associated with the conduction electrons could be written in the form,

σn = n μn q Where μn = mobility of the electrons

q = electron charge

Similarly for hole conduction,

σp = p μp q Where μp = mobility of holes

The current density associated with the drift of the electrons due to the applied field would be

given by, Jn = n μn qε

Similarly, Jp = p μp qε

However, an electron current may flow in a semiconductor even in the absence of an electric field,

i.e., if there exists a gradient of the electron density

Consequently, one deals in semiconductors frequently with two kinds of current: a drift current

(due to the electric field) and diffusion current (due to a gradient of the carrier concentration).

These concepts apply, of course, to electrons as well as to holes

The diffusion current density for electrons is Jn = q Dn Dn = Diffusion constant of the 𝐝𝐧𝐝𝐱

electrons in m2/sec

Similarly, diffusion current density for holes is Jp = q Dp ‒ 𝐝𝐩𝐝𝐱

Dp = diffusion constant of the holes in m2/sec

The hole current in any point x may be written as the sum of two contributions, one from the field

and one from the diffusion process: Jp = p μp q𝛆 – q 𝐃𝐩

𝐝𝐱 𝐝𝐩

Similarly, the total electron current density:

Jn = n μn q𝛆 + q 𝐃𝐧

𝐝𝐱 𝐝𝐧

There exists an important relationship between the diffusion coefficient and the mobility of the

carriers, which is known as the Einstein relation

For holes, Dp = (kT/q) μp

For electrons, Dn = (kT/q) μn

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Hence, the diffusion constant is proportional to the mobility,

= =VT𝐃𝐩𝛍𝐩

𝐃𝐧𝛍𝐧

Where VT = kT/q = T/11,600

13. Find the resistivity of (a) intrinsic silicon (b) p – type silicon with = / . Use = 1.5 𝑁𝐴 1016 𝑐𝑚3 𝑛𝑖 ×

/ and assume for intrinsic silicon = 1350 / V-S and = 480 / V-S and for doped 1010 𝑐𝑚3 𝜇𝑛 𝑐𝑚2 𝜇𝑝 𝑐𝑚2

silicon = 1110 / V-S and = 400 / V-S.𝜇𝑛 𝑐𝑚2 𝜇𝑝 𝑐𝑚2

SOLUTION:

(a) For intrinsic silicon resistivity ρ = 1

𝑞 (𝜇𝑛 n + 𝜇𝑝p)

For intrinsic silicon n = p = ni;

ρ = ⟹1

𝑞𝑛𝑖(𝜇𝑛 + 𝜇𝑝)

= 1

1.6 × 10 ‒ 19 × 1.5 × 1010(1350 + 480)

= 2.28 ohm-cm.× 105

(b) For doped silicon ρ = 1

𝑞 (𝜇𝑛 n + 𝜇𝑝 p)

Hole concentration p = = /𝑁𝐴 1016 𝑐𝑚3

Electron concentration n = 𝑛𝑖

2

𝑝 = (1.5 × 1010)2

1016

= 2.25 × 104/𝑐𝑚3

ρ = ∴1

1.6 × 10 ‒ 19(2.25 × 104 × 1110 + 1016 × 400)

= 1.56 ohm – cm.

14. Find the ratio of maximum resistivity to intrinsic resistivity (emax/ei)

Intrinsic conductivity σi = q ni (μn + μp)

Entrinsic conductivity σi = q (nμn + Pμp)

= q [n µn +n2

i

n µp]For maximum resistivity σ should be minimum

∴ = 0: n = And P = dσdn

niµp

µn

niµp

µn

σmin = q ni + q ni = 2 q ni µnµp µnµp µnµp

∴ = emax

e

µn + µp2 µn + µp

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15.EXPLAIN ABOUT THE CURRENT COMPONENTS IN A P-N DIODE?

, electron diffusion current𝑰𝒏𝒑

, hole current𝑰𝒑𝒑

, hole diffusion current𝑰𝒑𝒏

, electron current𝑰𝒏𝒏

region Distance 𝒏 region 𝒑

CurrentTransition region Total current, I

0.5 µm≈(a)

V

P n

‒+I(b)

Fig - 3(a): The hole and electron-current components vs, distance in a p-n junction diode. It is

assumed that no recombination takes place in the very narrow depletion region. (b) p-n junction diode

in forward bias

When a forward bias is applied to a diode, holes are injected into the n-side and electrons into the p-

side

The number of these injected minority carriers falls off exponentially with distance from the

junction as shown in fig.(3)(a)

The symbol Ipn(x) represents the hole current in the n material, and Inp(x) indicates the electron

current in the p-side as a function of x

Electrons crossing the junction at x = 0 from right to left constitute a current in the same direction

as holes crossing the junction from left to right

Hence the total current I at x = 0 is I = Ipn(0) + Inp(0)

Consequently, in the p-side, there must be a second component of current Ipp which, when added to

Inp, gives the total current I. Hence this hole current in the p-side Ipp(a majority carrier current) is

given by

Ipp(x) = I - Inp(x)

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This current is plotted as a function of distance as shown in fig.(3) as is also the corresponding

electron current Inn in the n material

For an un symmetrically doped diode, Ipn ≠ Inp

Current in a p-n diode is bipolar in character since it is made up of both positive and negative

carriers of electricity

The total current is constant throughout the device, but the proportion due to holes and that due to

electrons varies with distance

QUANTITATIVE THEORY OF THE p-n DIODE CURRENTS:

If the forward bias is applied to the diode, holes are injected from the p side into the n material. The

concentration pn of holes in the n-side is increased above its thermal equilibrium value pno and, is

given by pn(x) = pno + pn(0) …… (6)𝐞‒ 𝐱/𝐋𝐩

Where the parameter Lp is called the diffusion length for holes in the n material

Distance

p(x)

𝒑'(𝟎)

p0p’(x)

x

injected or excess hole concentration

= 𝒑 (𝒙) 𝒑𝟎 + 𝒑'(𝟎)𝒆‒ 𝒙/𝑳𝒑

Fig – 4: The hole concentration p(x) in n side as a function of distance x from the junction.‒

The injected or excess concentration at x = 0 is pn(0) = pn(0) pno‒

The diffusion hole current in the n-side is given by

…....... (7)

Taking the derivative of equation (6) and substituting in equation (7) we obtain

.......... (8)

This equation verifies that the hole current decreases exponentially with distance.

𝐈𝐩𝐧 =‒ 𝐪𝐀𝐃𝐩

𝐝𝐩𝐧

𝐝𝐱

= 𝐈𝐩𝐧(𝐱)𝐀𝐪𝐃𝐩 𝐩𝐧(𝟎)

𝐋𝐩𝐞 ‒

𝐱𝐋𝐩

17

THE LAW OF THE JUNCTION

If the barrier potential across the depletion layer is VB, then

.......... (9)

This is the Boltzmann relationship of kinetic gas theory

If we apply above equation to the case of an open-circuited p-n junction, then

pP = ppo, pn = pn0 and VB = V0

Consider now a junction biased in the forward direction by an applied voltage V

Then the barrier voltage is decreased from its equilibrium value by the amount V, VB = V0 - 𝐕𝐁 𝐕𝟎

V

Where, V0 = equilibrium value

At the edge of the depletion layer, x = 0, pn = pn(0), then the above equation (9) is

.…… (10)

Combining this equation with the above said equation (5), i.e., pp0=pn0 we obtain𝐞𝐕𝟎/𝐕𝐓

.…… (11)

This boundary condition is called the “law of the junction”. It indicates that, for a forward bias (V >

0), the hole concentration pn(0) at the junction is greater than the thermal-equilibrium value pn0.

A similar equation, valid for electrons, is obtained by interchanging p and n in above equation (11).

The hole concentration pn(0) injected into the n side at the junction is given by,

pn(0)=pn0( ) ……. (12)eV/VT ‒ 1

THE FORWARD CURRENTS:

The hole current Ipn(0) crossing the junction into the n-side at x = 0 is given by,

Ipn (𝟎) =𝐀𝐪𝐃𝐩 𝐩𝐧𝐨

𝐋𝐩(𝐞

𝐕/𝐕𝐓 ‒ 𝟏)

The electron current Inp(0) crossing the junction into the p-side is obtained from above equation by

interchanging n and p, or Inp (𝟎) =𝐀𝐪𝐃𝐧𝐧𝐩𝐨

𝐋𝐧(𝐞

𝐕/𝐕𝐓 ‒ 𝟏)

= pp pneVB/VT

p0 = pn(0)𝐞(𝐕𝟎 ‒ 𝐕)/𝐕𝐓

pn(0)=pn0𝐞𝐕/𝐕𝐓

18

The total diode current I is the sum of Ipn(0) and Inp(0), or I= I0(𝐞𝐕/𝐕𝐓 ‒ 𝟏)

where I0= + 𝐀𝐪𝐃𝐩𝐩𝐧𝟎

𝐋𝐩

𝐀𝐪𝐃𝐧𝐧𝐩𝟎

𝐋𝐧

Hence I0 is called the “reverse saturation current” and depends on doping concentration

I0= Where =A0T3Aq[ Dp

LpND+

Dn

LnNA] ni2

ni2 e

‒ EGO/KT

In other form, I0= VTAqni2 [ µp

LpND+

µn

LnNA]

From Einstein equation, Dp /μp = Dn /μn= VT

I0=Aq2 VT μn μp ni2 [ 1

Lpσn+

1Lnσp

]Where,σn=NDμnq and σp=NAμpq

EGO is a voltage which is numerically equal to the forbidden gap energy in electron volts. If we

consider the recombination of carriers, then the total current I, I = I0 …….. (13)(𝐞𝐕/𝛈𝐕𝐓 ‒ 𝟏)

Where, η ≈2 for small (rated) currents and η ≈1 for large currents

I0 depends on material and it is fixed for a given device. But varies with temperature,

= ……. (14)𝐈𝟎𝟐 𝐈𝟎𝟏 × 𝟐(𝑻𝟐 ‒ 𝑻𝟏)/𝟏𝟎

Where I01(I02) is the reverse saturation current at a temperature T1(T2)

I0 doubles for every 10oC rise in temperature. That is, it increases 7%/oC.

I0 is in the range of microamperes for a germanium diode and nano amperes for a silicon diode.

Since = 2 for small currents in silicon, the current increases as for the first several tenths of η eV/2VT

a volt and increases as only at higher voltageseV/VT

19

ST.MARTIN’S ENGG.COLLEGE

DHULAPALLY, SEC.BAD.

UNIT-II1.Explain about Regulated DC power supply?

For the operation of most of the electronics devices and circuits, a d.c. source is required. So it is advantageous to convert domestic a.c. supply into d.c.voltages. The process of converting a.c. voltage into d.c. voltage is called as rectification.This is achieved with i) Step-down Transformer, ii) Rectifier, iii) Filter and iv) Voltage regulator circuits.These elements constitute d.c. regulated power supply shown in the figure below.

Fig. Block diagram of Regulated D.C. Power Supply

Transformer – steps down 230V AC mains to low voltage AC.Rectifier – converts AC to DC, but the DC output is varying.Smoothing – smooth the DC from varying greatly to a small ripple.Regulator – eliminates ripple by setting DC output to a fixed voltage.

The block diagram of a regulated D.C. power supply consists of step-down transformer, rectifier, filter, voltage regulator and load.An ideal regulated power supply is an electronics circuit designed to provide a predetermined d.c. voltage Vo which is independent of the load current and variations in the input voltage ad temperature. If the output of a regulator circuit is a AC voltage then it is termed as voltage stabilizer, whereas if the output is a DC voltage then it is termed as voltage regulator.The elements of the regulated DC power supply are discussed as follows:

TRANSFORMER:

A transformer is a static device which transfers the energy from primary winding to secondary winding through the mutual induction principle, without changing the frequency.

The transformer winding to which the supply source is connected is called the primary, while the winding connected to the load is called secondary. If N1,N2 are the number of turns of the primary and secondary of the transformer then N1/N2 is called the turns ratio of the transformer.

RECTIFIER:

20

Any electrical device which offers a low resistance to the current in one direction but a high resistance to the current in the opposite direction is called rectifier. Such a device is capable of converting a sinusoidal input waveform, whose average value is zero, into a unidirectional waveform, with a non-zero average component.

A rectifier is a device which converts a.c. voltage (bi-directional) to pulsating d.c. voltage (Uni-directional).

2. Explain about the construction and operation of Half wave Rectifier?

The single – phase half wave rectifier is shown here

In positive half cycle, D is forward biased and conducts. Thus the output voltage is same as the input voltage. In the negative half cycle, D is reverse biased, and therefore output voltage is zero. The output voltage waveform is shown here.

The average output voltage of the rectifier is given by

The average output current is given by

When the diode is reverse biased, entire transformer voltage appears across the diode. The maximum voltage across the diode is Vm. The diode must be capable to withstand this voltage. Therefore PIV half wave rating of diode should be equal to Vm in case of single-phase rectifiers. The average current rating must be greater than Iavg

Zener Diode:The diodes designed to work in breakdown region are called zener diode. If the reverse voltage

exceeds the breakdown voltage, the zener diode will normally not be destroyed as long as the current does not exceed maximum value and the device closes not over load.

When a thermally generated carrier (part of the reverse saturation current) falls down thejunction and acquires energy of the applied potential, the carrier collides with crystal ions and imparts sufficient energy to disrupt a covalent bond. In addition to the original carrier, a new electron-hole pair is generated. This pair may pick up sufficient energy from the applied field to collide with another crystal ion and create still another electron-hole pair. This action continues and thereby disrupts the covalent bonds. The process is referred to as impact ionization, avalanche multiplication or avalanche breakdown.

21

There is a second mechanism that disrupts the covalent bonds. The use of a sufficiently strong electric field at the junction can cause a direct rupture of the bond. If the electric field exerts a strong force on a bound electron, the electron can be torn from the covalent bond thus causing the number of electron-hole pair combinations to multiply. This mechanism is called high field emission or Zener breakdown. The value of reverse voltage at which this occurs is controlled by the amount ot doping of the diode. A heavily doped diode has a low Zener breakdown voltage, while a lightly doped diode has a high Zener breakdown voltage.

At voltages above approximately 8V, the predominant mechanism is the avalanche breakdown. Since the Zener effect (avalanche) occurs at a predictable point, the diode can be used as a voltage reference. The reverse voltage at which the avalanche occurs is called the breakdown or Zener voltage.

A typical Zener diode characteristic is shown in fig. 1. The circuit symbol for the Zener diode is different from that of a regular diode, and is illustrated in the figure. The maximum reverse current, IZ(max), which the Zener diode can withstand is dependent on the design and construction of the diode. A design guideline that the minimum Zener current, where the characteristic curve remains at VZ (near the knee of the curve), is 0.1/ IZ(max).

Fig. 1 - Zener diode characteristicThe power handling capacity of these diodes is better. The power dissipation of a zener diode equals the product of its voltage and current.

PZ= VZ IZ

The amount of power which the zener diode can withstand ( VZ.IZ(max) ) is a limiting factor in power supply design.

3. Explain the working principle of Zener Regulator?

When zener diode is forward biased it works as a diode and drop across it is 0.7 V. When it works in breakdown region the voltage across it is constant (VZ) and the current through diode is decided by the external resistance. Thus, zener diode can be used as a voltage regulator in the configuration shown in fig. 2 for regulating the dc voltage. It maintains the output voltage constant even through the current through it changes.

22

The load line of the circuit is given by Vs= Is Rs + Vz. The load line is plotted along with zener characteristic in fig. 3. The intersection point of the load line and the zener characteristic gives the output voltage and zener current.

To operate the zener in breakdown region Vs should always be greater then Vz. Rs is used to limit the current. If the Vs voltage changes, operating point also changes simultaneously but voltage across zener is almost constant. The first approximation of zener diode is a voltage source of Vz magnitude and second approximation includes the resistance also. The two approximate equivalent circuits are shown in fig. 4.

If second approximation of zener diode is considered, the output voltage varies slightly as shown in fig. 5. The zener ON state resistance produces more I * R drop as the current increases. As the voltage varies form V1 to V2 the operating point shifts from Q1 to Q2.

The voltage at Q1 is

V1 = I1 RZ +VZ

and at Q2

V2 = I2 RZ +VZ

Thus, change in voltage is

V2 – V1 = ( I2 – I1 ) RZ

VZ =Δ IZ RZ

Zener Diode

Design of Zener regulator circuit:A zenere regulator circuit is shown in fig. 6. The varying load current is represented by a variable load resistance RL.

The zener will work in the breakdown region only if the Thevenin voltage across zener is more than VZ .

If zener is operating in breakdown region, the current through RS is given by

Fig. 6

23

and load current

Is= Iz + IL

The circuit is designed such that the diode always operates in the breakdown region and the voltage VZ across it remains fairly constant even though the current IZ through it vary considerably.

If the load IL should increase, the current IZ should decrease by the same percentage in order to maintain load current constant Is. This keeps the voltage drop across Rs constant and hence the output voltage.If the input voltage should increase, the zener diode passes a larger current, that extra voltage is dropped across the resistance Rs. If input voltage falls, the current IZ falls such that VZ is constant.

In the practical application the source voltage, vs, varies and the load current also varies. The design challenge is to choose a value of Rs which permits the diode to maintain a relatively constant output voltage, even when the input source voltage varies and the load current also varies.

We now analyze the circuit to determine the proper choice of Rs. For the circuit shown in figure,

(E-1)

(E-2)

The variable quantities in Equation (E-2) are vZ and iL. In order to assure that the diode remainsin the constant voltage (breakdown) region, we examine the two extremes of input/output conditions, as follows:

The current through the diode, iZ, is a minimum (IZ min) when the load current, iL is maximum (IL max) and the source voltage, vs is minimum (Vs min).

The current through the diode, iZ, is a maximum (IZ max) when the load current, iL, is minmum (iL min) and the source voltage vsis minimum(Vs max).

When these characteristics of the two extremes are inserted into Equation (E-1),

we find (E-3)

(E-4)In a practical problem, we know the range of input voltages, the range of output load currents, and the desired Zener voltage. Equation (E-4) thus represents one equation in two unknowns, the maximum and minimum Zener current. A second equation is found from the characteristic of zener. To avoid the non-constant portion of the characteristic curve, we use an accepted rule of thumb that the minimum Zener current should be 0.1 times the maximum (i.e., 10%), that is,

(E-5)

Solving the equations E-4 and E-5, we get,

(E-6)

Now that we can solve for the maximum Zener current, the value of Rs, is calculated from Equation (E-3).

24

Zener diodes are manufactured with breakdown voltages VZ in the range of a few volts to a few hundred volts. The manufacturer specifies the maximum power the diode can dissipate. For example, a 1W, 10 V zener can operate safely at currents up to 100mA.

EXAMPLE:4. Sketch the output vo and determine the dc level of the output for the network shown below

5. Repeat part (a) if the ideal diode is replaced by a silicon diode

6. Repeat part (a) and (b) if Vm is increased to 200V and compare solutions

Solution:4. In this situation the diode will conduct during the negative part of the input as shown in Fig. and vo will

appear as shown in the same figure. For the full period, the dc level is

5. Using a silicon diode, the output has the appearance of Fig.

5

25

6.

7. Explain about the FULL WAVE RECTIFIER?

BRIDGE NETWORK:

The dc level obtained from a sinusoidal input can be improved 100% using a process called full-wave

rectification.

The most familiar network for performing such a function appears in Fig. 1.8 with its four diodes in a bridge

configuration. During the period t = 0 to T/2 the polarity of the input is as shown in Fig. 1.9. The resulting

polarities across the ideal diodes are also shown in Fig. 1.9 to reveal that D2 and D3 are conducting while

D1 and D4 are in the “off” state.

The net result is the configuration of Fig. 1.10, with its indicated current and polarity across R. Since the

diodes are ideal the load voltage is vo = vi, as shown in the same figure.

Fig 1.8 Full wave bridge rectifier.

Fig 1.9 network of figure 1.8 for the period 0→ T/2 of the input voltage vi

26

Fig 1.10 conduction path for the positive region of vi

For the negative region of the input the conducting diodes are D1 and D4, resulting in the configuration

of Fig. 1.11. The important result is that the polarity across the load resistor R is the same as in Fig. 1.9,

establishing a second positive pulse, as shown in Fig. 1.11. Over one full cycle the input and output

voltages will appear as shown in Fig. 1.12.

Fig 1.11 conduction path for the negative region of vi

Fig 1.12 input and output waveforms for a full wave rectifier.

Fig 1.9 network of figure 1.8 for the period 0→ T/2 of the input voltage vi

Fig 1.10 conduction path for the positive region of vi

For the negative region of the input the conducting diodes are D1 and D4, resulting in the configuration

of Fig. 1.11. The important result is that the polarity across the load resistor R is the same as in Fig. 1.9,

establishing a second positive pulse, as shown in Fig. 1.11. Over one full cycle the input and output

voltages will appear as shown in Fig. 1.12.

27

Fig 1.11 conduction path for the negative region of vi

Fig 1.12 input and output waveforms for a full wave rectifier.

If silicon rather than ideal diodes are employed as shown in figure 1.13, an application of kirchoff’s voltage law

around the conduction path would result in

.......................... (1.3)

Fig 1.13 determining vomax for silicon diodes in the bridge configuration.

For situations where Vm >> 2VT, equation 1.4 can be applied for the average value with a relatively high level of

accuracy.

.......................... (1.4)

28

Then again, if Vm is sufficiently greater than 2VT, then equation 1.3 is often applied as a first approximation for

Vdc.

8. Explain about the CENTRE-TAPPED TRANSFORMER full wave rectifier?A second popular full-wave rectifier appears in Fig. 1.14 with only two diodes but requiring a center-tapped (CT)

transformer to establish the input signal across each section of the secondary of the transformer. During the

positive portion of vi applied to the primary of the transformer, the network will appear as shown in Fig. 1.15. D1

assumes the short-circuit equivalent and D2 the open-circuit equivalent, as determined by the secondary

voltages and the resulting current directions. The output voltage appears as shown in Fig. 1.15.

Fig 1.14 center-tapped transformer full-wave rectifier

Fig 1.15 Network conditions for the positive region of vi

29

1.16 Network conditions for negative region of vi

PIV:The network of Fig. 1.17 will help us determine the net PIV for each diode for this full-wave rectifier. Inserting

the maximum voltage for the secondary voltage and Vm as established by the adjoining loop will result in

Fig 1.17 determining the PIV level for the diode of the CT transformer full-wave rectifier

9. Determine the output waveform for the network of Fig. 1.18 and calculate the output dc level and the

required PIV of each diode.

Fig 1.18

Sol: The network will appear as shown in Fig. 1.19 for the positive region of the input voltage. Redrawing the

network will result in the configuration of Fig. 1.20, where

30

As shown in Fig. 1.20. For the negative part of the input the roles of the diodes will be interchanged and vo will

appear as shown in Fig. 1.21.

Fig 1.19 Network of figure 1.18 for positive region of vi

Fig 1.20 redrawn circuit of fig 1.19

Fig 1.21 resulting output

10. Write about FILTERS?

A rectifier should provide an output voltage that should be as smooth as possible. In practice, however,

output voltage from rectifiers consists of d.c. component and a.c. ripple

The a.c. component is made up of several dominant harmonics

When used on the rectifier output side, these are called d.c. filters, these tend to make the d.c. output

voltage and current as level as possible

The more common d.c. filter are of L, C and LC type as shown in figure 1.26 (a), (b) and (c)

31

Fig 1.26 (a)

Fig 1.26 (C)

An inductor L in series with load R1 figure 1.26 (a) reduces the ac component or ac ripples, considerably,. It

is because L in series with R offers high impedance to ac component but very low resistance to dc. Thus ac

component gets attenuated considerably.

A capacitor C across load R, figure 1.26(b) offers direct short circuit to ac component, these are therefore

not allowed to reach the load. However, dc gets stored in the form of energy in c and this allows the

maintenance of almost constant dc output voltage across the load.

11. COMPARE C AND L FILTERS?

If load resistance is low, ripple factor for L-filter is low and high for C-filter.

In both C-filter and L-filter, time constant should be large for better waveform, i.e. for low ripple factor, τ

should be high.

For L-filter, if R is lowered, τ = L/R increases, therefore ripple factor becomes low.

For C-filter, if R is increased, τ = RC increases, and ripple factor becomes low.

This shows that C-filter is suitable for load having low current consistently. L-filter is suited for loads

requiring high load current consistently.

A high value of C reduces ripple factor but increases the charging current and the diode current rating.

Inductor filter is bulky, weighty, expensive and causes extra ohmic loss as compared to C-filter. Besides, L-

filter is noisy in nature.

LC-FILTER

An L-C filter consists of inductor L in series with the load and capacitor C across the load. This filter

possesses the advantage of both L-filter and C-filter.

32

In addition, ripple factor in L-C filter has lower value than that obtained by either L-filter or C-filter for the

same value of L and C.

In L-C filter, inductor L blocks the dominant harmonics and capacitor C provides an easy path to the nth

harmonic ripple currents.

12. Determine the output waveform for the network in below figure

Sol: Past experience suggests that the diode will be in the “on” state for the positive region of VI - especially

when we note the aiding effect of V = 5 V. The network will then appear as shown in below and vo = vi = 5 V.

Substituting id = 0 at vd = 0 for the transition levels

V0 with diode in the on state

Fig: determining the transition level

33

For vi more negative than _5 V the diode will enter its open-circuit state, while for voltages more positive than

_5 V the diode is in the short-circuit state. The input and output voltages appear in Fig.

ST.MARTIN’S ENGG.COLLEGE

DHULAPALLY, SEC.BAD.

UNIT-III1.Explain the operation of Bipolar Junction Transistor?

A bipolar (junction) transistor (BJT) is a three-terminal electronic device constructed of doped semiconductor material and may be used in amplifying or switching applications. Bipolar transistors are so named because their operation involves both electrons and holes. Charge flow in a BJT is due to bidirectional diffusion of charge carriers across a junction between two regions of different charge concentrations. An NPN transistor can be considered as two diodes with a shared anode. In typical operation, the base-emitter junction is forward biased and the base– collector junction is reverse biased. In an NPN transistor, for example, when a positive voltage is applied to the base–emitter junction, the equilibrium between thermally generated carriers and the repelling electric field of the depletion region becomes unbalanced, allowing thermally excited electrons to inject into the base region. These electrons wander (or "diffuse") through the base from the region of high concentration near the emitter towards the region of low concentration near the collector. The electrons in the base are called minority carriers because the base is doped p-type which would make holes the majority carrier in the base.

To minimize the percentage of carriers that recombine before reaching the collector–base junction, the transistor's base region must be thin enough that carriers can diffuse across it in much less time than the semiconductor's minority carrier lifetime. In particular, the thickness of the base must be much less than the diffusion length of the electrons. The collector–base junction is reverse-biased, and so little electron injection occurs from the collector to the base, but electrons that diffuse through the base towards the collector are swept into the collector by the electric field in the depletion region of the collector–base junction. The thin shared base and asymmetric collector–emitter doping is what differentiates a bipolar transistor from two separate and oppositely biased diodes connected in series.

The proportion of electrons able to cross the base and reach the collector is a measure of the BJT efficiency. The heavy doping of the emitter region and light doping of the base region cause many more electrons to be injected from the emitter into the base than holes to be injected from the base into the emitter. The common-emitter current gain is represented by βF or hfe; it is approximately

34

the ratio of the DC collector current to the DC base current in forward-active region. It is typically greater than 100 for small-signal transistors but can be smaller in transistors designed for high-power applications. Another important parameter is the common-base current gain, αF. The common-base current gain is approximately the gain of current from emitter to collector in the forward-active region. This ratio usually has a value close to unity; between 0.98 and 0.998. Alpha and beta are more precisely related by the following identities (NPN transistor):

BJT consists of three differently doped semiconductor regions, the emitter region, the base region and the collector region. These regions are, respectively, p type, n type and p type in a PNP, and n type, p type and n type in a NPN transistor. Each semiconductor region is connected to a terminal, appropriately labeled: emitter (E), base (B) and collector (C).\ The base is physically located between the emitter and the collector and is made from lightly doped, high resistivity material. The collector surrounds the emitter region, making it almost impossible for the electrons injected into the base region to escape being collected, thus making the resulting value of α very close to unity, and so, giving the transistor a large β. A cross section view of a BJT indicates that the collector–base junction has a much larger area than the emitter– base junction.

Small changes in the voltage applied across the base–emitter terminals causes the current that flows between the emitter and the collector to change significantly. This effect can be used to amplify the input voltage or current. BJTs can be thought of as voltage-controlled current source, but are more simply characterized as current-controlled current sources, or current amplifiers, due to the low impedance at the base.

NPN

The symbol of an NPN Bipolar Junction TransistorNPN is one of the two types of bipolar transistors, in which the letters "N" (negative) and "P"

(positive) refer to the majority charge carriers inside the different regions of the transistor. Most bipolar transistors used today are NPN, because electron mobility is higher than hole mobility in semiconductors, allowing greater currents and faster operation. NPN transistors consist of a layer of P-doped semiconductor (the "base") between two N-doped layers. A small current entering the base in common-emitter mode is amplified in the collector output. In other terms, an NPN transistor is "on" when its base is pulled high relative to the emitter. The arrow in the NPN transistor symbol is on the emitter leg and points in the direction of the conventional current flow when the device is in forward active mode.

PNPThe other type of BJT is the PNP with the letters "P" and "N" referring to the majority

charge carriers inside the different regions of the transistor.

The symbol of a PNP Bipolar Junction Transistor.

PNP transistors consist of a layer of N-doped semiconductor between two layers of P-doped material. A small current leaving the base in common-emitter mode is amplified in the collector output. In other terms, a PNP transistor is "on" when its base is pulled low relative to the emitter. The

35

arrow in the PNP transistor symbol is on the emitter leg and points in the direction of the conventional current flow when the device is in forward active mode.

The construction and circuit symbols for both the NPN and PNP bipolar transistor are shown above with the arrow in the circuit symbol always showing the direction of conventional current flow between the base terminal and its emitter terminal, with the direction of the arrow pointing from the positive P-type region to the negative N-type region, exactly the same as for the standard diode symbol.

2. Explain the CB configuration input and output characteristics?

There are basically three possible ways to connect a Bipolar Transistor within an electronic circuit with each method of connection responding differently to its input signal as the static characteristics of the transistor vary with each circuit arrangement.

1. Common Base Configuration - has Voltage Gain but no Current Gain.2. Common Emitter Configuration - has both Current and Voltage Gain.3. Common Collector Configuration - has Current Gain but no Voltage Gain.

The Common Base Configuration.As its name suggests, in the Common Base or Grounded Base configuration, the BASE

connection is common to both the input signal and the output signal with the input signal being applied between the base and the emitter terminals. The corresponding output signal is taken from between the base and the collector terminals as shown with the base terminal grounded or connected to a fixed reference voltage point. The input current flowing into the emitter is quite large as its the sum of both the base current and collector current respectively therefore, the collector current output is less than the emitter current input resulting in a Current Gain for this type of circuit of less than "1", or in other words it "Attenuates" the signal.

The Common Base Amplifier Circuit

This type of amplifier configuration is a non-inverting voltage amplifier circuit, in that the signal voltages Vin and Vout are In-Phase. This type of arrangement is not very common due to its unusually high voltage gain characteristics. Its Output characteristics represent that of a forward biased diode while the Input characteristics represent that of an illuminated photo-diode. Also this type of configuration has a high ratio of Output to Input resistance or more importantly "Load" resistance (RL) to "Input" resistance (Rin) giving it a value of "Resistance Gain". Then the Voltage Gain for a common base can therefore be given asInput/ Output Characteristics

Common-Base:1. Input characteristics: The EB junction is essentially the same as a

forward biased diode, therefore the current-voltage characteristics is essentially the same as that of a diode:

Also the collector-base voltage V CB > 0 helps enhance the current IE to some extent

36

Output characteristics:As the CB junction is reverse biased, the current IC depends totally on IE. When IE=0,IC=ICB0

is the current caused by the minority carriers crossing the pn-junction. This is similar to the diode current-voltage characteristics seen before, except both axes are reversed (rotated 180 degrees), as both voltage ICB and current IC are defined in the opposite directions. When I E is increased IC=αIE+ICBO is increased correspondingly. Higher VCB can slightly increase α and there by IC.

AsIC<IE CB configuration does not have current-amplification effect.

3. Explain the operation of The Common Emitter Configuration?

In the Common Emitter or Grounded Emitter configuration, the input signal is applied between the base, while the output is taken from between the collector and the emitter as shown. This type of configuration is the most commonly used circuit for transistor based amplifiers and which represents the "normal" method of connection. The common emitter amplifier configuration produces the highest current and power gain of all the three bipolar transistor configurations. This is mainly because the input impedance is LOW as it is connected to a forward-biased junction, while the output impedance is HIGH as it is taken from a reverse-biased junction.

The Common Emitter Amplifier Circuit

In this type of configuration, the current flowing out of the transistor must be equal to the currents flowing into the transistor as the emitter current is given as Ie = Ic + Ib. Also, as the load resistance (RL) is connected in series with the collector, the Current gain of the Common EmitterTransistor Amplifier is quite large as it is the ratio of Ic/Ib and is given the symbol of Beta, (β).Since the relationship between these three currents is determined by the transistor itself, any small change in the base current will result in a large change in the collector current. Then, small changes in base current will thus control the current in the Emitter/Collector circuit.

By combining the expressions for both Alpha, α and Beta, β the mathematical relationship between these parameters and therefore the current gain of the amplifier can be given as:

37

Where: "Ic" is the current flowing into the collector terminal, "Ib" is the current flowing into the base terminal and "Ie" is the current flowing out of the emitter terminal.

Then to summarise, this type of bipolar transistor configuration has a greater input impedance, Current and Power gain than that of the common Base configuration but its Voltage gain is much lower. The common emitter is an inverting amplifier circuit resulting in the output signal being 180o out of phase with the input voltage signal.

4. Explain about the Common-Emitter input and output characteristics?

Input characteristics:Same as in the case of common-base configuration, the EB junction of the common-emitter configuration can also be considered as a forward biased diode, the current-voltage characteristics is similar to that of a diode:

The collector-emitter voltage VCE has little effect on IB.

Output characteristics:

The CB junction is reverse biased, the current

depends on the current IB. When IB=0,IC=ICEO the current caused by the minority carriers crossing the pn-junctions. When IB is increased IC is correspondingly increased by β.

5. Explain the operation of The Common Collector Configuration?

In the Common Collector or Grounded Collector configuration, the collector is now common and the input signal is connected to the Base, while the output is taken from the Emitter load as shown. This type of configuration is commonly known as a Voltage Follower or Emitter Follower circuit. The Emitter follower configuration is very useful for impedance matching applications because of the very high input impedance, in the region of hundreds of thousands of Ohms, and it has relatively low output impedance.

The Common Collector Amplifier Circuit

38

The Common Emitter configuration has a current gain equal to the β value of the transistor itself.In the common collector configuration the load resistance is situated in series with the emitter

so its current is equal to that of the emitter current. As the emitter current is the combination of the collector and base currents combined, the load resistance in this type of amplifier configuration also has both the collector current and the input current of the base flowing through it. Then the current gain of the circuit is given as:

This type of bipolar transistor configuration is a non-inverting amplifier circuit in that the signal voltages of Vin and Vout are "In-Phase". It has a voltage gain that is always less than "1" (unity). The load resistance of the common collector amplifier configuration receives both the base and collector currents giving a large current gain (as with the Common Emitter configuration) therefore, providing good current amplification with very little voltage gain.

6. Write the RELATIONSHIP BETWEEN TRANSISTOR CURRENTS?

While deriving various equations, following definitions should be kept in mind.

α = (IC/IE), (IC/IB), α = and β = β

1 + β β =α

1 ‒ α

(i) IC = IB = αIE = IE ββ

1 + β

(ii) IB = IC/ = IEβ IE

1 + β = (1 ‒ α)

(iii) IE = IC/ = α 1 + β

β βIB = (1 + β)𝐼B =IB

1 ‒ α

(iv) The three transistor d.c. currents always bear the following relation

IE : IB : IC : : 1: (1 α) : α‒

Incidentally, it may be noted that for ac currents, small letters ie, ib and ic are used.

7. Write about the LEAKAGE CURRENTS IN A TRANSISTOR?

39

CB CONFIGURATION

The leakage current ICBO where the subscripts CBO stand for ‘Collector to Base with emitter Open.’

Very often, it is simply written as ICO. It should be noted that,

(i) ICBO is exactly like the reverse saturation current IS or I0 of a reverse-biased diode.

(ii) ICBO is extremely temperature-dependent because it is made up of thermally-generated minority

carriers.

ICBO doubles for every 10oC rise in temperature for Ge and 6oC for Si.

Total collector current is actually the sum of two components:

(i) Current produced by normal transistor action i.e. component controlled by emitter current. Its

value is α IE and is due to majority carriers.

(ii) Temperature-dependent leakage current ICO due to minority carriers.

∴ IC=α IE + ICO

Since ICO << IC Hence α ≅ IC/IE

∴ IC=β IB+(1+ β) ICO

CE CONFIGURATION

For a common-emitter circuit of an NPN transistor whose base lead is open. It is found that despite

IB=0, there is a leakage current from collector to emitter. It is called ICEO, the subscripts CEO standing

for ‘Collector to Emitter with base Open’.

Taking this leakage current into account, the current distribution through a CE circuit becomes

IC = βIB + ICEO = βIB + (1+ β)ICO = βIB + ICO/(1 α)‒

(i) ∴ IC= αIB/(1 α) + ICO/(1 α)‒ ‒

Now βIB = αIE, Substituting this value above, we get,

IC= αIE + ICEO

Also, IB=IE IC‒

Substituting the value of IC from above, we have

(ii) IB = IE αIE ICEO = (1 α) IE ICEO‒ ‒ ‒ ‒

8. Explain the term THERMAL RUNAWAY?

The leakage current is extremely temperature-dependent. It almost doubles for every 10oC rise in

temperature in Ge and for every 6oC rise in Si.

Any increase in ICO is magnified (1+β) times i.e. 300 to 500 times. Even a slight increase in ICO will

affect IC considerably.

As IC increases, collector power dissipation increases which raises the operating temperature that leads

to further increase in IC.

If this succession of increases is allowed to continue, soon IC will increase beyond safe operating value

thereby damaging the transistor itself – a condition known as thermal runaway.

40

IMPORTANCE OF VCE

The voltage VCE is very important in checking whether the transistor is

(a) Defective

(b) Working in cut-off

(c) In saturation or dell into saturation

When VCE=VCC, the transistor is in cut-off i.e. it is turned OFF

When VCE=0, the transistor is in saturation i.e. it is turned fully ON

When VCE is less than zero i.e. negative, the transistor is said to be well into saturation. In practice,

both these conditions are avoided

For amplifier operation, VCE = VCC. 1 2

Normal operation of a transistor lies between the above two extreme conditions of cut-off and

saturation.

75+VCC

𝐈𝐂 =𝐕𝐂𝐂

𝐑𝐋

IB

+VBB

RL IC= 0

+VCC

VCE = VCC

IB=0

VCE = 0

(b)Fig. 4 (a) BJT in saturation region (b) BJT in Cut – Off region

RB

(a)

9. Explain the OPERATING REGIONS of a BJT?

A BJT has two junctions i.e. base-emitter and base-collector junctions either of which could be

forward-biased or reverse-biased. With two junctions, there are four possible combinations of bias

condition.

(i) Both junctions reverse-biased

(ii) Both junctions forward-biased

(iii)BE (Base-Emitter) junction forward-biased, BC (Base-Collector) junction reverse-biased

41

(iv)BE junction reverse-biased, BC junction forward-biased

Since condition (iv) is generally not used, we will tabulate the remaining three conditions below

TRANSISTOR OPERATION REGIONS

BE

JunctionBC Junction Region

RB* RB Cut-Off

FB** FB Saturation

FB RB Active

*Reverse-biased, **forward-biased

(A) CUT-OFF

This condition corresponds to reverse-bias for both base-emitter and base-collector junctions. In

fact, both diodes act like open circuits under these conditions, which is true for an ideal transistor.

In cut-off, VCE=VCC

(B) SATURATION

This condition corresponds to forward-bias for both base-emitter and base-collector junctions. The

transistor becomes saturated i.e. there is perfect short-circuit for both base-emitter and base-

collector diodes. In this case, VCE=0

(C) ACTIVE REGION

This condition corresponds to forward-bias for base-emitter junction and reverse bias for base-

collector junction. In this case, VCE > 0

10. Write about AVALANCHE MULTIPLICATION?

The maximum reverse-biasing voltage which may be applied before breakdown between the collector

and base terminals of the transistor, under the condition that the emitter lead be open-circuited, is

represented by the symbol BVCBO.

Breakdown may occur because of avalanche multiplication of the current ICO that crosses the collector

junction.

As a result of this multiplication, the current becomes MICO, in which M is the factor by which the

original current ICO is multiplied by the valance effect.

At a high enough voltage, namely, BVCBO, the multiplication factor M becomes nominally infinite and

the region of breakdown is then attained. Here the current rises abruptly, and large changes in current

accompany small changes in applied voltage.

42

The avalanche multiplication factor depends on the voltage VCB between collector and base. We shall

consider that M ≡𝟏

𝟏 ‒ (𝐕𝐂𝐁

𝐁𝐕𝐂𝐁𝐎)𝐧

The parameter n is found to be in the range of about 2 to 10, and controls the sharpness of the onset of

breakdown.

An analysis of avalanche breakdown for the CE configuration indicates that the collector-to-emitter

breakdown voltage with open-circuited base, designated BVCEO, is

BVCEO = BVCBO 𝐧 𝟏/𝐡𝐅𝐄

For an n-p-n germanium transistor, a reasonable value for n, determined experimentally, is n=6. If we

now take hFE=50, we find that BVCEO=0.52BVCBO.

11. Explain about REACH-THROUGH?

The second mechanism by which a transistor’s usefulness may be terminated as the collector voltage

is increased is called punch-through, or reach-through, and results from the increased width of the

collector-junction transition region with increased collector-junction voltage (the early effect).

As the voltage applied across the collector junction increases, the transition region penetrates deeper

into the collector and base. Because neutrality of charge must be maintained, the number of uncovered

charges on each side remains equal. Since the doping in the base is ordinarily substantially smaller

than that of the collector, the penetration of the transition region into the base is much larger than into

the collector. This process is known as Early Effect, or Base-width Modulation.

COMMON DATA FOR Q.NO. (2) TO Q.NO. (4)

50kΩ

5V

10V

3kΩ

+_

_

+

VBE = 0.8V, VCE,sat = 0.2V,hFE = β = 100

12. Determine the value of IB

(A)0.08 A (B) 0.084 mA (C) 3.27 A (D) 3.27 mA𝜇 𝜇

[Ans. B]

43

By KVL in emitter – base loop

5 = 50k.IB + VBE

= 84 µA⟹IB =5 ‒ 0.8

50k

13. Determine the value of IC

(A)0.084 (B) 0.084 mA (C) 3.27 A (D) 3.27 mA𝜇𝐴 𝜇

[Ans. D]

Le the device is in saturation then = 0.2VVCE

By KVL in collector – emitter loop

10 = 3k IC + VCE

= 3.27 mA⟹IC =10 ‒ 0.2

3k

For Saturation IB >IC

𝛽 =3.27100 = 32.7 µ𝐴

But = 84 µA. so it is in saturation IB

= 3.27 mA∴ IC

14. For a transistor circuit having = =2 A given =0.98.The value of isICO ICBO 𝜇 𝛼 𝐼𝐶𝐸𝑂

(A)1.96 A (B) 100 A (C) 3.96 A (D) 124 A𝜇 𝜇 𝜇 𝜇

[Ans. B] ICEO = (1 + β)ICBO

and β =∝

1 ‒∝

= = 49 0.98

1 ‒ 0.98

= 100 µA⟹ ICEO = (1 + 49)2 × 10 ‒ 6

15. Calculate base - emitter voltage for the circuit below

Given βR = 0.5 βF = 50 IS = 10–16

(A)0.143 V

(B) 0.835 V

(C) 0.532 V

(D)0.981 V

[Ans. B]

BE junction is forward bias, BC is reverse bias

IC = IS exp (VBE

Vt )IC = BFIB = 50 x 200 x 10–6 = 10–2A

VBE = Vt in = 0.259 in = 0.835V(IC

IS) ( 10 ‒ 2

10 ‒ 16)

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16. Explain about UJT and its operation?

A unijunction transistor (UJT) is an electronic semiconductor device that has only one junction. The UJT has three terminals: an emitter (E) and two bases (B1 and B2). The base is formed by lightly doped n-type bar of silicon. Two ohmic contacts B1 and B2 are attached at its ends. The emitter is of p-type and it is heavily doped. The resistance between B1 and B2, when the emitter is open-circuit is called interbase resistance.

The UJT is biased with a positive voltage between the two bases. This causes a potential drop along

the length of the device. When the emitter voltage is driven approximately one diode voltage above

the voltage at the point where the P diffusion (emitter) is, current will begin to flow from the emitter

into the base region. Because the base region is very lightly doped, the additional current (actually

charges in the base region) causes conductivity modulation which reduces the resistance of the portion

of the base between the emitter junction and the B2 terminal. This reduction in resistance means that

the emitter junction is more forward biased, and so even more current is injected. Overall, the effect is

a negative resistance at the emitter terminal. This is what makes the UJT useful, especially in simple

oscillator circuits.

Construction: A unijunction transistor is composed of a bar of N-type silicon having a P-type connection in the middle. Shown in Figure below(a). The connections at the ends of the bar are known as bases B1 and B2; the P-type mid-point is the emitter. With the emitter disconnected, the total resistance RBBO,is the sum of RB1 and RB2 as shown in Figure below(b). The intrinsic standoff ratio η is the ratio of RB1 to RBBO. It varies from 0.4 to 0.8 for different devices. The schematic symbol is Figure below(c)

Unijunction transistor: (a) Construction, (b) Model, (c) Symbol

The Uni-junction emitter current vs voltage characteristic curve (Figure below(a) ) shows that as VE increases, current IE increases up IP at the peak point. Beyond the peak point, current increases as voltage decreases in the negative resistance region. The voltage reaches a minimum at the valley point. The resistance of RB1, the saturation resistance is lowest at the valley point. VP is the voltage drop across RB1 plus a 0.7V diode drop; see Figure below(b). VV is estimated to be approximately 10% of VBB.

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UJT as a relaxation oscillator.

The relaxation oscillator in Figure below is an application of the unijunction oscillator. RE charges CE until the peak point. The unijunction emitter terminal has no effect on the capacitor until this point is reached. Once the capacitor voltage, VE, reaches the peak voltage point VP, the lowered emitter-base1 E-B1 resistance quickly discharges the capacitor. Once the capacitor discharges below the valley point VV, the E-RB1 resistance reverts back to high resistance, and the capacitor is free to charge again.

During capacitor discharge through the E-B1 saturation resistance, a pulse may be seen on the external B1 and B2 load resistors, Figure above. The load resistor at B1 needs to be low to not affect the discharge time. The external resistor at B2 is optional. It may be replaced by a short circuit. The approximate frequency is given by 1/f = T = RC. A more accurate expression for frequency is given in Figure above.

The charging resistor RE must fall within certain limits. It must be small enough to allow IP to flow based on the V BB supply less V P. It must be large enough to supply IV based on the VBB supply less VV.

81

ST.MARTIN’S ENGG.COLLEGE

DHULAPALLY, SEC.BAD.

UNIT-IV

TRANSISTOR BIASING AND STABILIZATION:

1. Explain about BIASING?

In order to produce distortion free output in amplifier circuits, the supply voltages and resistances establish a set of dc voltage VCEQ and ICQ to operate the transistor in the active region. These voltages and currents are called quiescent values which determine the operating point or Q-point for the transistor. The process of giving proper supply voltages and resistances for obtaining the desired Q-Point is called Biasing. The circuits used for getting the desired and proper operating point are known as biasing circuits. To establish the operating point in the active region biasing is required for transistors to be used as an amplifier. For analog circuit operation, the Q-point is placed so the transistor stays in active mode (does not shift to operation in the saturation region or cut-off region) when input is applied. For digital operation, the Q-point is placed so the transistor does the contrary - switches from "on" to "off" state. Often, Q-point is established near the center of active region of transistor characteristic to allow similar signal swings in positive and negative directions. Q-point should be stable. In particular, it should be insensitive to variations in transistor parameters (for example, should not shift if transistor is replaced by another of the same type), variations in temperature, variations in power supply voltage and so forth. The circuit must be practical: easily implemented and cost-effective.

BJT: Bipolar Junction Transistors:

Bipolar transistor amplifiers must be properly biased to operate correctly. In circuits made with individual devices (discrete circuits), biasing networks consisting of resistors are commonly employed. Much more elaborate biasing arrangements are used in integrated circuits, for example, bandgap voltage references and current mirrors.

Bias circuit requirements:For analog circuit operation, the Q-point is placed so the transistor stays in active mode (does

not shift to operation in the saturation region or cut-off region) when input is applied. For digital operation, the Q-point is placed so the transistor does the contrary - switches from "on" to "off" state. Often, Q-point is established near the center of active region of transistor characteristic to allow similar signal swings in positive and negative directions. Q-point should be stable. In particular, it should be insensitive to variations in transistor parameters (for example, should not shift if transistor is replaced by another of the same type), variations in temperature, variations in power supply voltage and so forth. The circuit must be practical: easily implemented and cost-effective.

2. Explain about Load line and write its importance?The concept of load line is very important in understanding the working of a transistor. It is

defined as the locus of operating points on the output characteristics of the transistor. It is the line on which the operating point moves when ac signal is applied to the transistor.

The dc load line gives the value of Ic and VCE corresponding to zero signal conditions. The ac load line gives the value of IC and VCE when ac signal is applied. AC load line is steeper than the dc load line but the two intersect at the Q-point determined by biasing dc voltages and currents. AC load line takes into account the ac load resistance while dc load line considers only the dc load resistance.

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3.Explain the importance of Q Point?The operating point of a device, also known as bias point, quiescent point, or Q-point, is the

point on the output characteristics that shows the DC collector–emitter voltage (Vce) and the collector current (Ic) with no input signal applied. The term is normally used in connection with devices such as transistors.

For bipolar junction transistors the bias point is chosen to keep the transistor operating in the active mode, using a variety of circuit techniques, establishing the Q-point DC voltage and current. A small signal is then applied on top of the Q-point bias voltage, thereby either modulating or switching the current, depending on the purpose of the circuit.

The quiescent point of operation is typically near the middle of DC load line. The process of obtaining certain DC collector current at a certain DC collector voltage by setting up operating point is called biasing.

After establishing the operating point, when input signal is applied, the output signal should not move the transistor either to saturation or to cut-off. However, this unwanted shift still might occur, due to the following reasons:

1. Parameters of transistors depend on junction temperature. As junction temperature increases, leakage current due to minority charge carriers (ICBO) increases. As ICBO increases, ICEO also increases, causing an increase in collector current IC. This produces heat at the collector junction. This process repeats, and, finally, Q-point may shift into the saturation region. Sometimes, the excess heat produced at the junction may even burn the transistor. This is known as thermal runaway.

2. When a transistor is replaced by another of the same type, the Q-point may shift, due to changes in parameters of the transistor, such as current gain (β) which varies slightly for each unique transistor.

To avoid a shift of Q-point, bias-stabilization is necessary. Various biasing circuits can be used for this purpose.

4.Explain about Collector-to-base bias?

ThiS configuration employs negative feedback to prevent thermal runaway and stabilize the operating point. In this form of biasing, the base resistor RB is connected to the collector instead of connecting it to the DC source VCC. So any thermal runaway will induce a voltage drop across the RC resistor that will throttle the transistor's base current.

If Vbe is held constant and temperature increases, then the collector current Ic increases. However, a larger Ic causes the voltage drop across resistor Rc to increase, which in turn reduces the voltage across the base resistor Rb. A lower base-resistor voltage drop reduces the base current Ib, which results in less collector current Ic. Because an increase in collector current with temperature is opposed, the operating point is kept stable.Merits:

Circuit stabilizes the operating point against variations in temperature and β (ie. replacement of transistor)

Demerits: In this circuit, to keep Ic independent of β, the following condition must be met:

which is the case when As β-value is fixed (and generally unknown) for a given transistor, this relation can be satisfied

either by keeping Rc fairly large or making Rb very low.

83

If Rc is large, a high Vcc is necessary, which increases cost as well as precautions necessary while handling.

If Rb is low, the reverse bias of the collector–base region is small, which limits the range of collector voltage swing that leaves the transistor in active mode.

The resistor Rb causes an AC feedback, reducing the voltage gain of the amplifier. This undesirable effect is a trade-off for greater Q-point stability.

5.Explain about the Voltage divider bias?

The voltage divider is formed using external resistors R1 and R2. The voltage across R2 forward biases the emitter junction. By proper selection of resistors R1 and R2, the operating point of the transistor can be made independent of β. In this circuit, the voltage divider holds the base voltage fixed independent of base current provided the divider current is large compared to the base current. However, even with a fixed base voltage, collector current varies with temperature (for example) so an emitter resistor is added to stabilize the Q-point, similar to the above circuits with emitter resistor.Merits:

Unlike above circuits, only one dc supply is necessary. Operating point is almost independent of β variation. Operating point stabilized against shift in temperature.

Demerits: As β-value is fixed for a given transistor, this relation can be satisfied either by keeping RE

fairly large, or making R1||R2 very low.

If RE is of large value, high VCC is necessary. This increases cost as well as precautions necessary while handling. If R1 || R2 is low, either R1 is low, or R2 is low, or both are low. A low R1 raises VB closer to VC, reducing the available swing in collector voltage, and limiting how large RC can be made without driving the transistor out of active mode. A low R2 lowers Vbe, reducing the allowed collector current. Lowering both resistor values draws more current from the power supply and lowers the input resistance of the amplifier as seen from the base.

AC as well as DC feedback is caused by RE, which reduces the AC voltage gain of the amplifier. A method to avoid AC feedback while retaining DC feedback is discussed below.

84

6.Explain about the Emitter bias?

When a split supply (dual power supply) is available, this biasing circuit is the most effective, and provides zero bias voltage at the emitter or collector for load. The negative supply VEE is used to forward-bias the emitter junction through RE. The positive supply VCC is used to reverse-bias the collector junction. Only two resistors are necessary for the common collector stage and four resistors for the common emitter or common base stage.

We know that,

VB - VE = Vbe

If RB is small enough, base voltage will be approximately zero. Therefore emitter current is,

IE = (VEE - Vbe)/RE

The operating point is independent of β if RE >> RB/βMerit:

Good stability of operating point similar to voltage divider bias.

Demerit:

This type can only be used when a split (dual) power supply is available.

7.Explain the importance of Stability Factor?

The degree of success achieved in stabilizing IC in the face of variations in ICO is expressed in terms of stability factor S and it is defined as the rate of change of IC w.r.t. ICO, keeping ß and VBE constant.

i.e. S = dIc/dIco at constant ß and VBE (or IB)

From above expression it is obvious that smaller is the value of S, higher is the stability. It is desirable to have as low stability factor as possible so as to achieve greater thermal stability. The ideal value of S is unity (because IC includes ICO) but it is never possible to achieve it in practice.

Stability Factor in case of CB circuit,

S = dIc/dIco = d(ßIE + Ico)/dIco 0+1 or S = 1

Stability factor in case of CE circuit

85

S = dIc/dIco = d[ßIß + (1+ ß) Ico]/dIco 1 + ß taking IB constant.

8.Explain about Stabilization?

It is desirable that once selected, the operating (or Q) point should remain stable i.e. the operating point should not shift its position owing to change in temperature etc. Unfortunately it is not possible in practice unless special efforts are made to achieve it. The maintenance of the operating point stable is called the stabilization.The stabilization of operating point is essential because ofa) Temperature dependence of IC(b) Individual variations and

(c)Thermal runaway

With the increase in temperature, the collector leakage current ICO, the current gain ß tend to increase and VBE required to produce a given collector current IC tends to decrease. Thus increase in temperature tends to cause increase in IC.The value of ß and VBE are not exactly the same for any two transistors even of the same type. So when a transistor is replaced by another one (even of the same type) the operating point (zero signals IC and VCE) is shifted.The collector current IC, being equal to ß IB + (1+ ß ) ICO, increases with the increase in temperature. This leads to increased power dissipation with further increase in temperature. Being a cumulative process, it can lead to thermal runaway resulting in burn out of the transistor.However, if by some modification, IC is made to fall with increase in temperature automatically, then decrease in the term ß can be made to neutralize the increase in the term (1 +ß ) ICO, thereby keeping IC almost constant. This will achieve thermal stability resulting in bias stability.The biasing network associated with the transistor should fulfill the requirements of (i) ensuring proper zero signal collector current, (ii) ensuring VCE not falling below 0.5 V for Ge transistors and 1 V for Si transistors at any instant and (iii) ensuring stabilization of operating point (zero signal IC and VCE)

9. Explain about Bias Compensation techniques?

Diode Compensation:

In the previous section, we looked at how four parameters (VCC, VBE, ICBO, and ) can affect the total collector current and, therefore, the Q-point of the amplifier. Diode compensation is a technique that is used to reduce the Q-point variations by selecting a diode that has temperature characteristics similar to the transistor. To make sure that the diode and transistor have the same temperature characteristics, we can use a BJT with the same specifications as the amplifier transistor that is diode-connected. This simply involves shorting the collector to the base as shown in the figure to the right for an npn BJT (this can also be done with pnp BJTs). As a reminder, the diode symbol and the model for the forward biased silicon diode are alsoshown to the right – remember that the current flows in the direction of the arrow and that, unlessan ideal diode is specified, the diode forward resistance and turn-on voltage must be included in all calculations.

86

The diode is connected in the base circuit of the amplifier as shown in Figure 7.9a, reproduced to the right. The addition of the diode in this manner allows temperature compensation since the VON of the diode varies in the same fashion as the VBE of the transistor. If the transistors used in the amplifier and to construct the diode are atched, he diode characteristics and base-emitter junction characteristics will be the same. Under these circumstances, variations in VBE due to changes in bias parameters will effectively be significantly reduced or cancelled.

Sensistor & Thermistor Compensation:

Sensistor is a resistor whose resistance changes with temperature.The resistance increases exponentially with temperature[1], that is the temperature coefficient is positive (eg. 0.7% per degree Celsius).[2]Sensistors are used in electronic circuits for compensation of temperature influence or as sensors of temperature for other circuits.[3]Sensistors are made by using semiconducting silicon and in their operation are similar to PTC-type thermistors.

For a silicon transistor

VBE,sat = 0.8V

= hFE = 100𝛽

VCE,sat = 0.2V is used in the circuit shown below

5V

200kΩ

+_

V cc (10V)

RC

10. Calculate the minimum value of RC for which the transistor remains in saturation

(A)4 k (B) 4.5Ω (C) 4.6kΩ (D) None of theseΩ

[Ans. C]

IB = 5 ‒ 0.8200 K = µA

= 2.1 mA𝐼𝐶max = 𝛽 IB

87

IC = 10 ‒ 0.2

RC

4.6 KΩRC ≥ 10 ‒ 0.2

2.1 =

11. Find the collector current (IC) when the transistor works in saturation region?

(A)2.1µA (B) 2.1mA (C) 21µA (D) None of these

88

[Ans. B]

When transistor is in saturation = 2.1 mAIC

12. In a PNP transistor operating in the active region, in the best region the main stream of current

is

(A)Drift of holes

(B) Diffusion of holes

(C) Diffusion of electrons

(D)Drift of electrons

[Ans. B]

13. For the BJT in the circuit shown Q1

below, . 𝛽 = ∞, 𝑉𝐵𝐸𝑜𝑛= 0.7𝑉, 𝑉𝐶𝐸𝑠𝑎𝑡

= 0.7𝑉

The switch is initially closed. At time , 𝑡 = 0

the switch is opened. The time at which 𝑡 Q1

leaves the active region is

(A)10 ms

(B) 25 ms

(C) 50 ms

(D)100 ms

5V

0.5 mA

‒ 𝟓𝑽 𝑸𝟏

𝒕 = 𝟎

𝟒.𝟑𝒌𝛀

𝟓𝝁𝑭

‒ 𝟏𝟎𝑽

[Ans. C]

Apply KVL at the BE junction

IE =‒ 5 ‒ 0.7 + 10

4.3𝑘Ω =4.3

4.3𝑘Ω = 1𝑚𝐴

Always ; At collection junctionIE = 1mA

ICap + (0.5mA) = 1mA ( ∵ β = ∞; IE = IC) always constantICap = 1 ‒ 0.5 = 0.5𝑚𝐴

VCE = VC ‒ VE⟹VC = VCE + VE

= 0.7 + (4.3)3 × 1 × 10 ‒ 3 = 0.7 + 4.3( ∵ VE = IERE)VC = 5V = Vcap

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or Vcap = Icapt𝑐 𝑡 =

𝑉𝐶𝑎𝑝 (𝐶)

𝐼𝐶𝑎𝑝=

(5) × 5 × 10 ‒ 6

0.5 × 10 ‒ 3 = 50𝑚𝑠

5V

0.5 mA

‒ 𝟓𝑽

𝒕 = 𝟎

𝟒.𝟑𝒌𝛀

𝟓𝒎𝑭

‒ 𝟏𝟎𝑽

𝑽𝑪

𝑽𝑬 = 𝑰𝑬𝑹𝑬

14. Explain about the Fixed Bias or Base Bias?

In this condition a single power source is applied to the collector and base of the transistor using only two resistors. Applying KVL to the circuit,

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Thus, by merely changing the value of the resistor the base current can be adjusted to the desired value. And by using the current gain (β) relationship, IC can also be found out accordingly. Hence the Q point can be adjusted just by changing the value of the resistor connected to the base.

15. Write about the Bipolar Junction Transistor Amplifier?To understand the concept of Bipolar Junction Transistor Amplifier, we should look through the diagram of a p-n-p transistor first.

Now as the input voltage is changed a little, say ΔVi of the emitter - base voltage changes the barrier height and the emitter current by ΔIE. This change in emitter current develops a voltage drop ΔVO across the load resistance RL, where,ΔVO = - RLΔIC

ΔVO gives the output voltage of the amplifier. There is a negative sign because of the collector current gives a voltage drop across RL with polarity opposite to the reference polarity. The voltage gain AV for the amplifier is given the ratio between the output voltages ΔVO to the input voltage ΔVi, so,

ΔIC / ΔIE = AI is called the current gain ratio of the transistor. From the figure diagram shown above we can see that an increase in the emitter voltage reduces the forward bias at the emitter junction thus decreases the collector current. It indicates that the output voltage and the input voltage are in phase. Now, finally the power gain Ap of the transistor is the ratio between the output power and the input power

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ST.MARTIN’S ENGG.COLLEGE

DHULAPALLY, SEC.BAD.

UNIT-V

1. Explain about the Small signal low frequency transistor Models?

All the transistor amplifiers are two port networks having two voltages and two currents. The positive directions of voltages and currents are shown in fig. 1.

Fig. 1

Out of four quantities two are independent and two are dependent. If the input current i1 and output voltage v2 are taken independent then other two quantities i2 and v1 can be expressed in terms of i1 and V2.

The equations can be written as

where h11, h12, h21 and h22 are called h-parameters.

= hi = input impedance with output short circuit to ac.

=hr = fraction of output voltage at input with input open circuited or reverse voltage gain with input open circuited to ac (dimensions).

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= hf = negative of current gain with output short circuited to ac.The current entering the load is negative of I2. This is also known as forward short circuit current gain.

= ho = output admittance with input open circuited to ac.

If these parameters are specified for a particular configuration, then suffixes e,b or c are also included, e.g. hfe ,h ib are h parameters of common emitter and common collector amplifiers

Using two equations the generalized model of the amplifier can be drawn as shown in fig. 2.

Fig. 2The hybrid model for a transistor amplifier can be derived as follow:Let us consider CE configuration as show in fig. 3. The variables, iB, iC ,vC, and vB represent total instantaneous currents and voltages iB and vC can be taken as independent variables and vB, IC as dependent variables.

Fig. 3vB = f1 (iB ,vC )

IC = f2 ( iB , vC ).

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Using Taylor 's series expression, and neglecting higher order terms we obtain.

The partial derivatives are taken keeping the collector voltage or base current constant. The vB, vC, iB, iC represent the small signal (incremental) base and collector current and voltage

and can be represented as vb ,ib ,vC ,iC

The model for CE configuration is shown in fig. 4.

Fig. 4

2. Analyze the transistor amplifier using h-parameters?

To form a transistor amplifier it is only necessary to connect an external load and signal source as indicated in fig. 1 and to bias the transistor properly.

Consider the two-port network of CE amplifier. RS is the source resistance and ZL is the load impedence h-parameters are assumed to be constant over the operating range. The ac equivalent circuit is shown in fig. 2. (Phasor notations are used assuming sinusoidal voltage input). The quantities of interest are the current gain, input impedence, voltage gain, and output impedence.

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3.Derive the expression for Current gain in CE Configuration?

For the transistor amplifier stage, Ai is defined as the ratio of output to input currents.

4. Derive the expression for Input Impedence of CE amplifier?

The impedence looking into the amplifier input terminals ( 1,1' ) is the input impedence Zi

5. Derive the expression for Voltage gain?The ratio of output voltage to input voltage gives the gain of the transistors.

Output Admittance:It is defined as

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Av is the voltage gain for an ideal voltage source (Rv = 0).

Consider input source to be a current source IS in parallel with a resistance RS as shown in fig. 3.

In this case, overall current gain AIS is defined as

6. Explain the Simplified common emitter hybrid model?

In most practical cases it is appropriate to obtain approximate values of A V , A i etc rather than calculating exact values. How the circuit can be modified without greatly reducing the accuracy. Fig. 4 shows the CE amplifier equivalent circuit in terms of h-parameters Since 1 / hoe in parallel with RL is approximately equal to RL if 1 / hoe >> RL then hoe may be neglected. Under these conditions.

Ic = hfe IB .hre vc = hre Ic RL = hre hfe Ib RL .

Fig. 4

Since h fe.h re 0.01, this voltage may be neglected in comparison with h ic Ib drop across h ie provided RL is not very large. If load resistance RL is small than hoe and hre can be neglected.

Output impedence seems to be infinite. When Vs = 0, and an external voltage is applied at the

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output we fined Ib = 0, I C = 0. True value depends upon RS and lies between 40 K and 80K.On the same lines, the calculations for CC and CB can be done.

CE amplifier with an emitter resistor:

The voltage gain of a CE stage depends upon hfe. This transistor parameter depends upon temperature, aging and the operating point. Moreover, hfe may vary widely from device to device, even for same type of transistor. To stabilize voltage gain A V of each stage, it should be independent of hfe. A simple and effective way is to connect an emitter resistor Re as shown in fig. 5. The resistor provides negative feedback and provide stabilization.

Fig. 5An approximate analysis of the circuit can be made using the simplified model.

7.Explain about FET and its importance?

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The Field Effect Transistor, or simply FET however, uses the voltage that is applied to their input terminal, called the Gate to control the current flowing through them resulting in the output current being proportional to the input voltage. As their operation relies on an electric field (hence the name field effect) generated by the input Gate voltage, this then makes the Field Effect Transistor a "VOLTAGE" operated device.

The Field Effect Transistor is a three terminal unipolar semiconductor device that has very similar characteristics to those of their Bipolar Transistor counterparts ie, high efficiency, instant operation, robust and cheap and can be used in most electronic circuit applications to replace their equivalent bipolar junction transistors (BJT). Field effect transistors can be made much smaller than an equivalent BJT transistor and along with their low power consumption and power dissipation makes them ideal for use in integrated circuits such as the CMOS range of digital logic chips. The field effect transistor is a three terminal device that is constructed with no PN-junctions within the main current carrying path between the Drain and the Source terminals, which correspond in function to the Collector and the Emitter respectively of the bipolar transistor. The current path between these two terminals is called the "channel" which may be made of either a P-type or an N-type semiconductor material. The control of current flowing in this channel is achieved by varying the voltage applied to the Gate. As their name implies, Bipolar Transistors are "Bipolar" devices because they operate with both types of charge carriers, Holes and Electrons. The Field Effect Transistor on the other hand is a "Unipolar" device that depends only on the conduction of electrons (N-channel) or holes (P-channel).

The Field Effect Transistor has one major advantage over its standard bipolar transistor, in that their input impedance, ( Rin ) is very high, (thousands of Ohms), while the BJT is comparatively low. This very high input impedance makes them very sensitive to input voltage signals, but the price of this high sensitivity also means that they can be easily damaged by static electricity. There are two main types of Field Effect Transistor, the Junction Field Effect Transistor or JFET and the Insulated-gate Field Effect Transistor or IGFET), which is more commonly known as the standard Metal Oxide Semiconductor Field Effect Transistor or MOSFET for short.

The Junction Field Effect TransistorA bipolar junction transistor is constructed using two PN-junctions in the main current

carrying path between the Emitter and the Collector terminals. The Junction Field Effect Transistor (JFET) has no PN-junctions but instead has a narrow piece of high-resistivity semiconductor material forming a "Channel" of either N-type or P-type silicon for the majority carriers to flow through with two ohmic electrical connections at either end commonly called the Drain and the Source respectively. There are two basic configurations of junction field effect transistor, the N-channel JFET and the P-channel JFET. The N-channel JFET's channel is doped with donor impurities meaning that the flow of current through the channel is negative (hence the term N-channel) in the form of electrons. Likewise, the P-channel JFET's channel is doped with acceptor impurities meaning that the flow of current through the channel is positive (hence the term P-channel) in the form of holes. N-channel JFET's have a greater channel conductivity (lower resistance) than their equivalent P-channel types, since electrons have a higher mobility through a conductor compared to holes. This makes the N-channel JFET's a more efficient conductor compared to their P-channel counterparts. There are two ohmic electrical connections at either end of the channel called the Drain and the Source. But within this channel there is a third electrical connection which is called the Gate terminal and this can also be a P-type or N-type material forming a PN-junction with the main channel. The relationship between the connections of a junction field effect transistor and a bipolar junction transistor are compared below.

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8. Comparison of connections between a JFET and a BJT?

Bipolar Transistor Field Effect Transistor

Emitter - (E) >> Source - (S)

Base - (B) >> Gate - (G)

Collector - (C) >> Drain - (D)

The symbols and basic construction for both configurations of JFETs are shown below.

The semiconductor "channel" of the Junction Field Effect Transistor is a resistive path through which a voltage VDS causes a current ID to flow. The JFET can conduct current equally well in either direction. A voltage gradient is thus formed down the length of the channel with this voltage becoming less positive as we go from the Drain terminal to the Source terminal. The PN-junction therefore has a high reverse bias at the Drain terminal and a lower reverse bias at the Source terminal. This bias causes a "depletion layer" to be formed within the channel and whose width increases with the bias. The magnitude of the current flowing through the channel between the Drain and the Source terminals is controlled by a voltage applied to the Gate terminal, which is a reverse-biased. In an N-channel JFET this Gate voltage is negative while for a P-channel JFET the Gate voltage is positive. The main difference between the JFET and a BJT device is that when the JFET junction is reverse-biased the Gate current is practically zero, whereas the Base current of the BJT is always some value greater than zero.

9. Bias arrangement for an N-channel JFET and corresponding circuit symbols?

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The cross sectional diagram above shows an N-type semiconductor channel with a P-type region called the Gate diffused into the N-type channel forming a reverse biased PN-junction and it is this junction which forms the depletion region around the Gate area when no external voltages are applied. JFETs are therefore known as depletion mode devices. This depletion region produces a potential gradient which is of varying thickness around the PN-junction and restrict the current flow through the channel by reducing its effective width and thus increasing the overall resistance of the channel itself. The most-depleted portion of the depletion region is in between the Gate and the Drain, while the least-depleted area is between the Gate and the Source. Then the JFET's channel conducts with zero bias voltage applied (i.e. the depletion region has near zero width).

With no external Gate voltage ( VG = 0 ), and a small voltage ( VDS ) applied between the Drain and the Source, maximum saturation current ( IDSS ) will flow through the channel from the Drain to the Source restricted only by the small depletion region around the junctions.If a small negative voltage ( -VGS ) is now applied to the Gate the size of the depletion region begins to increase reducing the overall effective area of the channel and thus reducing the current flowing through it, a sort of "squeezing" effect takes place. So by applying a reverse bias voltage increases the width of the depletion region which in turn reduces the conduction of the channel. Since the PN-junction is reverse biased, little current will flow into the gate connection. As the Gate voltage ( -VGS ) is made more negative, the width of the channel decreases until no more current flows between the Drain and the Source and the FET is said to be "pinched-off" (similar to the cut-off region for a BJT). The voltage at which the channel closes is called the "pinch-off voltage", ( VP ).

JFET Channel Pinched-off

In this pinch-off region the Gate voltage, VGS controls the channel current and VDS has little or no effect.

JFET Model

The result is that the FET acts more like a voltage controlled resistor which has zero resistance when VGS = 0 and maximum "ON" resistance ( RDS ) when the Gate voltage is very negative.

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Under normal operating conditions, the JFET gate is always negatively biased relative to the source.It is essential that the Gate voltage is never positive since if it is all the channel current will flow to the Gate and not to the Source, the result is damage to the JFET. Then to close the channel:

No Gate voltage ( VGS ) and VDS is increased from zero.No VDS and Gate control is decreased negatively from zero.VDS and VGS varying.

The P-channel Junction Field Effect Transistor operates the same as the N-channel above, with the following exceptions: 1). Channel current is positive due to holes, 2). The polarity of the biasing voltage needs to be reversed.The output characteristics of an N-channel JFET with the gate short-circuited to the source is given as

10. Explain the Output characteristic V-I curves of a typical junction FET?

The voltage VGS applied to the Gate controls the current flowing between the Drain and the Source terminals. VGS refers to the voltage applied between the Gate and the Source while VDS refers to the voltage applied between the Drain and the Source. Because a Junction Field Effect Transistor is a voltage controlled device, "NO current flows into the gate!" then the Sourcecurrent ( IS ) flowing out of the device equals the Drain current flowing into it and therefore ( ID = IS ).

The characteristics curves for a P-channel junction field effect transistor are the same as those

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above, except that the Drain current ID decreases with an increasing positive Gate-Source voltage, VGS.

The Drain current is zero when VGS = VP. For normal operation, VGS is biased to be somewhere between VP and 0. Then we can calculate the Drain current, ID for any given bias point in the saturation or active region as follows:

Drain current in the active region.

Note that the value of the Drain current will be between zero (pinch-off) and IDSS (maximum current). By knowing the Drain current ID and the Drain-Source voltage VDS the resistance of the channel ( ID ) is given as:

Where: gm is the "transconductance gain" since the JFET is a voltage controlled device and which represents the rate of change of the Drain current with respect to the change in Gate-Source voltage.

11. Write about Working of Insulated Gate Field Effect transistor(IGFET) or MOSFET in depletion mode?

Insulated gate field-effect transistors are unipolar devices just like JFETs: that is, the controlled current does not have to cross a PN junction. There is a PN junction inside the transistor, but its only purpose is to provide that non-conducting depletion region which is used to restrict current through the channel.

Here is a diagram of an N-channel IGFET of the "depletion" type:

Notice how the source and drain leads connect to either end of the N channel, and how the gate lead attaches to a metal plate separated from the channel by a thin insulating barrier. That barrier is sometimes made from silicon dioxide (the primary chemical compound found in sand), which is a very good insulator. Due to this Metal (gate) - Oxide (barrier) - Semiconductor (channel) construction, the IGFET is sometimes referred to as a MOSFET. There are other types of IGFET

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construction, though, and so "IGFET" is the better descriptor for this general class of transistors. Notice also how there are four connections to the IGFET. In practice, the substrate lead is directly connected to the source lead to make the two electrically common.

\With source and substrate common to each other, the N and P layers of the IGFET end

up being directly connected to each other through the outside wire. This connection prevents any voltage from being impressed across the PN junction. As a result, a depletion region exists between the two materials, but it can never be expanded or collapsed. JFET operation is based on the expansion of the PN junction's depletion region, but here in the IGFET that cannot happen, so IGFET operation must be based on a different effect. Indeed it is, for when a controlling voltage is applied between gate and source, the conductivity of the channel is changed as a result of the depletion region moving closer to or further away from the gate. In other words, the channel's effective width changes just as with the JFET, but this change in channel width is due to depletion region displacement rather than depletion region expansion.

In an N-channel IGFET, a controlling voltage applied positive (+) to the gate and negative (-) to the source has the effect of repelling the PN junction's depletion region, expanding the N-type channel and increasing conductivity:

Reversing the controlling voltage's polarity has the opposite effect, attracting the depletion region and narrowing the channel, consequently reducing channel conductivity:

The insulated gate allows for controlling voltages of any polarity without danger of forward-biasing a junction, as was the concern with JFETs. This type of IGFET, although its called a "depletion-type," actually has the capability of having its channel either depleted (channel narrowed) or enhanced (channel expanded). Input voltage polarity determines which way the channel will be influenced.

If the IGFET is an N-channel and the input voltage is connected so that the positive (+) side is on the gate while the negative (-) side is on the source, the channel will be enhanced as extra electrons build up on the channel side of the dielectric barrier. Think, "negative (-) correlates with N-type, thus enhancing the channel with the right type of charge carrier (electrons) and making it more conductive." Conversely, if the input voltage is connected to an N-channel IGFET the other way, so that negative (-) connects to the gate while positive (+) connects to the source, free electrons will be "robbed" from the channel as the gate-channel capacitor charges, thus depleting the channel of majority charge carriers and making it less conductive.For P-channel IGFETs, the input voltage polarity and channel effects follow the same rule. That is to say, it takes just the opposite polarity as an N-channel IGFET to either deplete or enhance:

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11. Explain about the Enhancement Mode MOSFET ?The Metal Oxide Silicon FET (MOSFET) or Metal Oxide Silicon Transistor (M.O.S.T.)

has an even higher input resistance (typically 1012 to 1015 ohms) than that of the JFET. In this device the gate is completely insulated from the rest of the transistor by a very thin layer of metal oxide (Silicon dioxide SiO2). Hence the general name applied to any device of this type, the IGFET or Insulated Gate FET.

Construction

The layers are laid down one by one, by diffusing various semiconductor materials with suitable doping levels and layers of insulation into the surface of the device under carefully controlled conditions at high temperatures. Parts of a layer may be removed by etching using photographic masks to make the required pattern of the electrodes etc. before the next layer is added. The insulating layers are made by laying down very thin layers of silicon dioxide; conductors are created by evaporating a metal such as aluminum on to the surface. The transistors produced in this way have a much higher quality than is possible using other methods, and many transistors can be produced at one time on a single slice of silicon, before the silicon slice is cut up into individual transistors or integrated circuits.

Fig. 4.1 Construction of a N Channel Enhancement Mode MOSFET

The gate has a voltage applied to it that makes it positive with respect to the source. This causes holes in the P type layer close to the silicon dioxide layer beneath the gate to be repelled down into the P type substrate and at the same time this positive potential on the gate attracts free electrons from the surrounding substrate material. These free electrons form a thin layer of charge carriers beneath the gate electrode (they can't reach the gate because of the insulating silicon dioxide layer) bridging the gap between the heavily doped source and drain areas. This layer is sometimes called an "inversion layer" because applying the gate voltage has caused the P type material immediately under the gate to firstly become "intrinsic" (with hardly any charge carriers) and then an N type layer within the P type substrate.

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Any further increase in the gate voltage attracts more charge carriers into the inversion layer, so reducing its resistance and increasing current flow between source and drain. Reducing the gate source voltage reduces current flow. When the power is switched off of course, the area beneath the gate reverts to P type once more. As well as the type described above, devices having N type substrates and P type (inversion layer)channels are also available. Operation is identical, but of course the polarity if the gate voltage is reversed.

The method of operation described is called "ENHANCEMENT MODE" as the application of gate source voltage makes a conducting channel "grow", therefore it enhances the channel. Other devices are available in which the application of a bias voltage reduces or "depletes" the conducting channel.

12. Explain the operation of Depletion Mode MOSFET?

Reducing The Conduction ChannelThe depletion mode MOSFET shown as a N channel device (P channel is also available)

in fig 5.1 is more usually made as a discrete component, i.e. a single transistor rather than IC form. In this device a thin layer of N type silicon is deposited just below the gate-insulating layer, and forms a conducting channel between source and drain. Thus when the gate source voltage VGS is zero, current (in the form of free electrons) can flow between source and drain. Note that the gate is totally insulated from the channel by the layer of silicon dioxide. Now that a conducting channel is present the gate does not need to cover the full width between source and drain. Because the gate is totally insulated from the rest of the transistor this device, like other IGFETs, has a very high input resistance.

Fig 5.1 Depletion Mode N Channel MOSFETIn the N channel device, shown in Fig. 5.2 the gate is made negative with respect to the source, which has the effect creating a depletion area free from charge carriers, beneath the gate. This restricts the depth of the conducting channel, so increasing channel resistance and reducing current flow through the device.

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Depletion mode MOSFETS are also available in which the gate extends the full width of the channel (from source to drain). In this case it is also possible to operate the transistor in enhancement mode. This is done by making the gate positive instead of negative. The positive voltage on the gate attracts more free electrons into the conducing channel while at the same time repelling holes down into the P type substrate. Thus the more positive the gate potential, the deeper, and lower resistance is the channel. Increasing positive bias thus increases current flow. This useful depletion/enhancement version has the disadvantage that, as the gate area is increased; the gate capacitance is also larger than true depletion types. This may present difficulties at higher frequencies.

Fig 5.6 Circuit Symbols for Depletion Mode MOSFETs (IGFETs)

Notice the solid bar indicating the presence of a conducting channel between source and drain.Note: Making the gate more negative reduces conduction between source & drain In N channel devices, but increases conduction between source & drain In P channel devices.

13. Explain the Applications of FETs?

Although FETs have a lower gain than bipolar transistors their very high input impedance makes them suitable for applications where input signals may be severely reduced if applied to a bipolar transistor base, which needs base current to operate. A useful feature of FETs is that they tend to produce less background noise than Bipolar types and so are useful in the initial stages of systems such as amplifiers; radios etc. where signal levels are very small and could be swamped by excessive background noise.

14. COMPARE MOS FET WITH JFET?

1) In JFET, the transverse electric field across the reverse biased P Njunction controls the conductivity of the channel. In FET Transverse electric field is induced across the insulating layer.

2)Input impedance of MOS FET is much higher (1010 to 1015 ) cmpared to that of

JFET (108 ) because gate is insulated from channel.3) The output characteristics of JFET are flatter than that of MOS FET because drain

resistance of JFET is much higher than MOS FET. 4) JFET is operated in depletion mode only where as MOSFET can be operated in

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depletion and enhancement mode. 5) MOSFET are easier to fabricate than JFET 6) MOSFETs are easily get damaged due to static change 7) In MOSFET source and drain can be interchanged 8) CMOSFETs dissipates very low power 9) MOS FETs are widely used in VLSI.

15. Explain about Common Source JFET Amplifier?

Small signal amplifiers can also be made using Field Effect Transistors or FET's . These devices have the advantage over bipolar transistors of having extremely high input impedance along with a low noise output making them ideal for use in amplifier circuits that have very small input signals. The design of an amplifier circuit based around a junction field effect transistor or "JFET", (n-channel FET) or even a metal oxide silicon FET or "MOSFET" is exactly the same principle as that for the bipolar transistor circuit. Firstly, a suitable quiescent point or "Q-point" needs to be found for the correct biasing of the JFET amplifier circuit with single amplifier configurations of Common-source (CS), Common-drain (CD) or Source-follower (SF) and the Common-gate (CG) available for most FET devices. These three JFET amplifier configurations correspond to the common-emitter, emitter-follower and the common-base configurations using bipolar transistors. The Common Source JFET Amplifier as this is the most widely used JFET amplifier design. The common source JFET amplifier circuit is shown below.

The amplifier circuit consists of an N-channel JFET, connected in a common source configuration. The JFET gate voltage Vg is biased through the potential divider network set up by resistors R1 and R2 and is biased to operate within its saturation region which is equivalent to the active region of the bipolar junction transistor. Unlike a bipolar transistor circuit, the junction FET takes virtually no input gate current allowing the gate to be treated as an open circuit. Then no input characteristics curves are required. Since the N-Channel JFET is a depletion mode device and is normally "ON", a negative gate voltage with respect to the source is required to modulate or control the drain current. This negative voltage can be provided by biasing from a separate power supply voltage or by a self biasing arrangement as long as a steady current flow through the JFET even when there is no input signal present and Vg maintains a reverse bias of the gate-source pn junction.

Any suitable pair of resistor values in the correct proportions would produce the correct

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biasing voltage so the DC gate biasing voltage Vg is given as:

The input signal, (Vin) of the common source JFET amplifier is applied between the Gate terminal and the zero volts rail, (0v). With a constant value of gate voltage Vg applied the JFET operates within its "Ohmic region" acting like a linear resistive device. The drain circuit contains the load resistor, Rd. The output voltage, Vout is developed across this load resistance. The efficiency of the common source JFET amplifier can be improved by the addition of a resistor, Rs included in the source lead with the same drain current flowing through this resistor. Resistor, Rs is also used to set the JFET amplifiers "Q-point".

When the JFET is switched fully "ON" a voltage drop equal to Rs x Id is developed across this resistor raising the potential of the source terminal above 0v or ground level. This voltage drop across Rs due to the drain current provides the necessary reverse biasing condition across the gate resistor, R2 effectively generating negative feedback. In order to keep the gate-source junction reverse biased, the source voltage, Vs needs to be higher than the gate voltage, Vg. This source voltage is therefore given as:

Then the Drain current, Id is also equal to the Source current, Is as "No Current" enters the Gate terminal and this can be given as:

This potential divider biasing circuit improves the stability of the common source JFET amplifier circuit when being fed from a single DC supply compared to that of a fixed voltage biasing circuit. Both resistor, Rs and the source by-pass capacitor, Cs serve basically the same function as the emitter resistor and capacitor in the common emitter bipolar transistor amplifier circuit, namely to provide good stability and prevent a reduction in the loss of the voltage gain. However, the price paid for a stabilized quiescent gate voltage is that more of the supply voltage is dropped across Rs.

The basic circuit and characteristics of a Common Source JFET Amplifier are very similar to that of the common emitter amplifier.Common Source JFET Amplifier Characteristics Curves

As with the common emitter bipolar circuit, the DC load line for the common source JFET amplifier produces a straight line equation whose gradient is given as: -1/(Rd + Rs) and that it crosses the vertical Id axis at point A equal to Vdd/(Rd + Rs). The other end of the load line crosses the horizontal axis at point B which is equal to the supply voltage, Vdd. The actual position of the Q-point on the DC load line is generally positioned at the mid centre point of the load line (for class-A operation) and is determined by the mean value of Vg which is biased negatively as the JFET is a depletion-mode device. Like the bipolar common emitter amplifier the output of the Common Source JFET Amplifier is 180o out of phase with the input signal.

One of the main disadvantages of using Depletion-mode JFET is that they need to be negatively biased. Should this bias fail for any reason the gate-source voltage may rise and

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become positive causing an increase in drain current resulting in failure of the drain voltage, Vd. Also the high channel resistance, Rds(on) of the junction FET, coupled with high quiescent steady state drain current makes these devices run hot so additional heatsink is required. However, most of the problems associated with using JFET's can be greatly reduced by using enhancement-mode MOSFET devices instead.

MOSFETs or Metal Oxide Semiconductor FET's have much higher input impedances and low channel resistances compared to the equivalent JFET. Also the biasing arrangements for MOSFETs are different and unless we bias them positively for N-channel devices and negatively for P-channel devices no drain current will flowCommon Gate amplifier

A common-gate amplifier is one of three basic single-stage field-effect transistor (FET) amplifier topologies, typically used as a current buffer or voltage amplifier. In this circuit the source terminal of the transistor serves as the input, the drain is the output and the gate is common to both, hence its name. The analogous bipolar junction transistor circuit is the common-base amplifier.

Figure 1: Basic N-channel common-gate circuit (neglecting biasing details); current source ID represents an active load; signal is applied at node Vin and output is taken from node Vout; output can be current or voltage

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Figure 2: Hybrid pi model with test source ix at output to find output resistance

The amplifier characteristics are summarized below in Table 1. The approximate expressions use the assumptions (usually accurate) rO >> RL and gmrO >> 1.

In general the overall voltage/current gain may be substantially less than the open/short circuit gains listed above (depending on the source and load resistances) due to the loading effect.Closed circuit voltage gain Taking input and output loading into consideration, the closed circuit voltage gain (that is, the gain with load RL and source with resistance RS both attached) of the common gate can be written as:

,

Which has the simple limiting forms

,

Depending upon whether gmRS is much larger or much smaller than one.In the second case RS << 1/gm and the Thévenin representation of the source is useful, producing the second form for the gain, typical of voltage amplifiers. Because the input impedance of the common-gate amplifier is very low, the cascode amplifier often is used instead. The cascode places a common-source amplifier between the voltage driver and the common-gate circuit to permit voltage amplification using a driver with RS >> 1/gm.

Common Drain amplifier or Source Follower.A common-drain amplifier, also known as a source follower, is one of three basic

single-stage field effect transistor (FET) amplifier topologies, typically used as a voltage buffer. In this circuit the gate terminal of the transistor serves as the input, the source is the output, and the drain is common to both (input and output), hence its name. The analogous bipolar junction transistor circuit is the common-collector amplifier. This circuit is used to transform impedances.

Basic N-channel JFET source follower circuit (neglecting biasing details).At low frequencies, the source follower has the following small signal characteristics

Voltage gain:

Current gain:

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Input impedance:

Output impedance:

The variable gm that is not listed in Figure 1 is the trans conductance of the device (usually given in units of Siemens.

16. Explain the biasing methods pFET Biasing methods.

Unlike BJTs, thermal runaway does not occur with FETs. However, the wide differences in maximum and minimum transfer characteristics make ID levels unpredictable with simple fixed-gate bias voltage. To obtain reasonable limits on quiescent drain currents ID and drain-source voltage VDS, source resistor and potential divider bias techniques must be used. With few exceptions, MOSFET bias circuits are similar to those used for JFETs. Various FET biasing circuits are discussed below

Fixed Bias.

DC bias of a FET device needs setting of gate-source voltage VGS to give desired drain current ID . For a JFET drain current is limited by the saturation current IDS.FET has such a high input impedance that no gate current flows and the dc voltage of the gate set by a voltage divider or a fixed battery voltage is not affected or loaded by the FET.Fixed dc bias is obtained using a battery VQG. This battery ensures that the gate is always negative with respect to source and no current flows through resistor RG and gate terminal that is IG =0. The battery provides a voltage VGS to bias the N-channel JFET, but no resulting current is drawn from the battery VGG. Resistor RG is included to allow any ac signal applied through capacitor C to develop across RG. While any ac signal will develop across RG, the dc voltage drop across RG is equal to IG RG i.e. 0 volt.

The gate-source voltage VGS is then

VGS = - VG – VS = – VGG – 0 = – VGG

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The drain -source current ID is then fixed by the gate-source voltage as determined by equation.

This current then causes a voltage drop across the drain resistor RD and is given as VRD = ID RD and output voltage , Vout = VDD – ID RD

Self-Bias.

This is the most common method for biasing a JFET. Self-bias circuit for N-channel JFET is shown in figure.

Since no gate current flows through the reverse-biased gate-source, the gate current IG = 0 and, therefore,vG = iG RG = 0 With a drain current ID the voltage at the S is Vs= ID Rs

The gate-source voltage is thenVGs = VG - Vs = 0 – ID Rs = – ID Rs

So voltage drop across resistance Rs provides the biasing voltage VGg and no external source is required for biasing and this is the reason that it is called self-biasing.

The operating point (i.e zero signal ID and VDS) can easily be determined from equation and equation given below VDS = VDD – ID (RD + RS)

Thus dc conditions of JFET amplifier are fully specified. Self biasing of a JFET stabilizes its quiescent operating point against any change in its parameters like trans conductance. Let the given JFET be replaced by another JFET having the double conductance then drain current will also try to be double but since any increase in voltage drop across Rs, therefore, gate-source voltage, VGS becomes more negative and thus increase in drain current is reduced.

Potential-Divider Biasing.

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A slightly modified form of dc bias is provided by the circuit shown in figure. The resistors RGl and RG2 form a potential divider across drain supply VDD. The voltage V2 across RG2 provides the necessary bias. The additional gate resistor RGl from gate to supply voltage facilitates in larger adjustment of the dc bias point and permits use of larger valued RS.

The gate is reverse biased so that IG = 0 and gate voltage

VG =V2 = (VDD/R G1 + R G2 ) *RG2

And VGS = VG – VS = VG - ID RS

The circuit is so designed that ID, Rs is greater than VD so that VGS is negative. This provides correct bias voltage.

The operating point can be determined as

ID = (V2 – VGS)/ RS

And

VDS = VDD – ID (RD + RS)

FET AS A VOLTAGE –VARIABLE RESISTOR (VVR):

FET is operated in the constant current portion of its output characteristics for the linear applications .In the region before pinch off , where Vds is small the drain to source resistance rd can be controlled by the bias voltage Vgs.The FET is useful as a voltage variable resistor (VVR) or Voltage Dependent resistor.

In JFET the drain source conductance gd = Id/Vds for small values of Vds which may be expressed as gd = gdo [ 1-( VgsVp)1/2 ] where gdo is the value of drain conductance when the bias voltage Vgs is zero.Small signal FET drain resistance rd varies with applied gate voltage Vgs and FET act like a VARIABLE PASSIVE RESISTOR.When VDS < VP, Id VDS, when VGS is constant. i.e., FET acts as a resistor.In this regionFET is used as a Voltage controlled resistor. Or Voltage variable resistor. Or Voltage dependant resistor.

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Differences between BJT and FET

FET is uni polar device – current ID is due to majority (Where as BJT is Bipolar) charge carries only.

FET is less noisy as there are no junctions(in conduction channel) FET

FET Input impedance is very high (100 M ) (due to reverse bias)

FET is voltage controlled device, BJT is current controlled device

FETs are easy to fabricate

FET performance does not change much with temperature. FET has –Ve temp. Coefficient, BJT has +Ve temp. coefficient.

FET has higher switching speeds

FET is useful for small signal operation only

BJT is cheaper than FET